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clk: tegra: pll: Change misc_reg count from 3 to 6 

New SoC's may have more than 3 MISC registers, so bump up the array size
and use a #define to be more informative about the value.

Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
hifive-unleashed-5.1
Bill Huang 2015-06-18 17:28:22 -04:00 committed by Thierry Reding
parent 204c85d124
commit 56fd27b31f
1 changed files with 3 additions and 1 deletions
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4
drivers/clk/tegra/clk.h
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@ -156,6 +156,8 @@ struct div_nmp {
u8 override_divp_shift;
};
#define MAX_PLL_MISC_REG_COUNT 6
/**
* struct tegra_clk_pll_params - PLL parameters
*
@ -225,7 +227,7 @@ struct tegra_clk_pll_params {
u32 iddq_bit_idx;
u32 aux_reg;
u32 dyn_ramp_reg;
u32 ext_misc_reg[3];
u32 ext_misc_reg[MAX_PLL_MISC_REG_COUNT];
u32 pmc_divnm_reg;
u32 pmc_divp_reg;
u32 flags;