ARM: tegra: dma: Fix critical data corruption bugs
Sometimes, due to high interrupt latency in the continuous mode of DMA transfer, the half buffer complete interrupt is handled after DMA has transferred the full buffer. When this is detected, stop DMA immediately and restart with the next buffer if the next buffer is ready. originally fixed by Victor(Weiguo) Pan <wpan@nvidia.com> In place of using the simple spin_lock()/spi_unlock() in the interrupt thread, using the spin_lock_irqsave() and spin_unlock_irqrestore(). The lock is shared between the normal process context and interrupt context. originally fixed by Laxman Dewangan (ldewangan@nvidia.com) The use of shadow registers caused memory corruption at physical address 0 because the enable bit was not shadowed, and assuming it needed to be set would enable an unconfigured dma block. Most of the register accesses don't need to know the previous state of the registers, and the few places that do need to modify only a few bits in the registers are the same ones that were sometimes incorrectly setting the enable bit. This patch convert tegra_dma_update_hardware to set the entire register, and the other users to read-modify-write, and drops the shadow registers completely. Also fixes missing locking in tegra_dma_allocate_channel Signed-off-by: Colin Cross <ccross@android.com>
This commit is contained in:
parent
699fe145d6
commit
5789fee934
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@ -121,17 +121,13 @@ struct tegra_dma_channel {
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void __iomem *addr;
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int mode;
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int irq;
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/* Register shadow */
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u32 csr;
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u32 ahb_seq;
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u32 ahb_ptr;
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u32 apb_seq;
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u32 apb_ptr;
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int req_transfer_count;
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};
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#define NV_DMA_MAX_CHANNELS 32
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static DEFINE_MUTEX(tegra_dma_lock);
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static DECLARE_BITMAP(channel_usage, NV_DMA_MAX_CHANNELS);
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static struct tegra_dma_channel dma_channels[NV_DMA_MAX_CHANNELS];
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@ -139,7 +135,6 @@ static void tegra_dma_update_hw(struct tegra_dma_channel *ch,
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struct tegra_dma_req *req);
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static void tegra_dma_update_hw_partial(struct tegra_dma_channel *ch,
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struct tegra_dma_req *req);
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static void tegra_dma_init_hw(struct tegra_dma_channel *ch);
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static void tegra_dma_stop(struct tegra_dma_channel *ch);
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void tegra_dma_flush(struct tegra_dma_channel *ch)
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@ -151,6 +146,9 @@ void tegra_dma_dequeue(struct tegra_dma_channel *ch)
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{
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struct tegra_dma_req *req;
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if (tegra_dma_is_empty(ch))
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return;
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req = list_entry(ch->list.next, typeof(*req), node);
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tegra_dma_dequeue_req(ch, req);
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@ -159,10 +157,10 @@ void tegra_dma_dequeue(struct tegra_dma_channel *ch)
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void tegra_dma_stop(struct tegra_dma_channel *ch)
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{
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unsigned int csr;
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unsigned int status;
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u32 csr;
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u32 status;
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csr = ch->csr;
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csr = readl(ch->addr + APB_DMA_CHAN_CSR);
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csr &= ~CSR_IE_EOC;
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writel(csr, ch->addr + APB_DMA_CHAN_CSR);
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@ -176,19 +174,16 @@ void tegra_dma_stop(struct tegra_dma_channel *ch)
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int tegra_dma_cancel(struct tegra_dma_channel *ch)
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{
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unsigned int csr;
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u32 csr;
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unsigned long irq_flags;
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spin_lock_irqsave(&ch->lock, irq_flags);
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while (!list_empty(&ch->list))
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list_del(ch->list.next);
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csr = ch->csr;
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csr = readl(ch->addr + APB_DMA_CHAN_CSR);
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csr &= ~CSR_REQ_SEL_MASK;
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csr |= CSR_REQ_SEL_INVALID;
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/* Set the enable as that is not shadowed */
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csr |= CSR_ENB;
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writel(csr, ch->addr + APB_DMA_CHAN_CSR);
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tegra_dma_stop(ch);
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@ -230,18 +225,15 @@ int tegra_dma_dequeue_req(struct tegra_dma_channel *ch,
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* - Finally stop or program the DMA to the next buffer in the
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* list.
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*/
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csr = ch->csr;
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csr = readl(ch->addr + APB_DMA_CHAN_CSR);
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csr &= ~CSR_REQ_SEL_MASK;
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csr |= CSR_REQ_SEL_INVALID;
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/* Set the enable as that is not shadowed */
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csr |= CSR_ENB;
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writel(csr, ch->addr + APB_DMA_CHAN_CSR);
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/* Get the transfer count */
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status = readl(ch->addr + APB_DMA_CHAN_STA);
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to_transfer = (status & STA_COUNT_MASK) >> STA_COUNT_SHIFT;
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req_transfer_count = (ch->csr & CSR_WCOUNT_MASK) >> CSR_WCOUNT_SHIFT;
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req_transfer_count = ch->req_transfer_count;
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req_transfer_count += 1;
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to_transfer += 1;
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@ -349,7 +341,9 @@ EXPORT_SYMBOL(tegra_dma_enqueue_req);
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struct tegra_dma_channel *tegra_dma_allocate_channel(int mode)
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{
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int channel;
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struct tegra_dma_channel *ch;
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struct tegra_dma_channel *ch = NULL;
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mutex_lock(&tegra_dma_lock);
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/* first channel is the shared channel */
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if (mode & TEGRA_DMA_SHARED) {
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@ -358,11 +352,14 @@ struct tegra_dma_channel *tegra_dma_allocate_channel(int mode)
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channel = find_first_zero_bit(channel_usage,
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ARRAY_SIZE(dma_channels));
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if (channel >= ARRAY_SIZE(dma_channels))
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return NULL;
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goto out;
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}
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__set_bit(channel, channel_usage);
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ch = &dma_channels[channel];
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ch->mode = mode;
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out:
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mutex_unlock(&tegra_dma_lock);
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return ch;
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}
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EXPORT_SYMBOL(tegra_dma_allocate_channel);
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@ -372,22 +369,27 @@ void tegra_dma_free_channel(struct tegra_dma_channel *ch)
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if (ch->mode & TEGRA_DMA_SHARED)
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return;
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tegra_dma_cancel(ch);
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mutex_lock(&tegra_dma_lock);
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__clear_bit(ch->id, channel_usage);
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mutex_unlock(&tegra_dma_lock);
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}
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EXPORT_SYMBOL(tegra_dma_free_channel);
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static void tegra_dma_update_hw_partial(struct tegra_dma_channel *ch,
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struct tegra_dma_req *req)
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{
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u32 apb_ptr;
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u32 ahb_ptr;
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if (req->to_memory) {
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ch->apb_ptr = req->source_addr;
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ch->ahb_ptr = req->dest_addr;
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apb_ptr = req->source_addr;
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ahb_ptr = req->dest_addr;
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} else {
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ch->apb_ptr = req->dest_addr;
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ch->ahb_ptr = req->source_addr;
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apb_ptr = req->dest_addr;
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ahb_ptr = req->source_addr;
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}
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writel(ch->apb_ptr, ch->addr + APB_DMA_CHAN_APB_PTR);
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writel(ch->ahb_ptr, ch->addr + APB_DMA_CHAN_AHB_PTR);
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writel(apb_ptr, ch->addr + APB_DMA_CHAN_APB_PTR);
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writel(ahb_ptr, ch->addr + APB_DMA_CHAN_AHB_PTR);
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req->status = TEGRA_DMA_REQ_INFLIGHT;
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return;
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@ -401,38 +403,39 @@ static void tegra_dma_update_hw(struct tegra_dma_channel *ch,
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int ahb_bus_width;
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int apb_bus_width;
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int index;
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unsigned long csr;
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u32 ahb_seq;
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u32 apb_seq;
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u32 ahb_ptr;
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u32 apb_ptr;
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u32 csr;
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ch->csr |= CSR_FLOW;
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ch->csr &= ~CSR_REQ_SEL_MASK;
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ch->csr |= req->req_sel << CSR_REQ_SEL_SHIFT;
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ch->ahb_seq &= ~AHB_SEQ_BURST_MASK;
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ch->ahb_seq |= AHB_SEQ_BURST_1;
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csr = CSR_IE_EOC | CSR_FLOW;
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ahb_seq = AHB_SEQ_INTR_ENB | AHB_SEQ_BURST_1;
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apb_seq = 0;
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csr |= req->req_sel << CSR_REQ_SEL_SHIFT;
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/* One shot mode is always single buffered,
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* continuous mode is always double buffered
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* */
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if (ch->mode & TEGRA_DMA_MODE_ONESHOT) {
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ch->csr |= CSR_ONCE;
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ch->ahb_seq &= ~AHB_SEQ_DBL_BUF;
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ch->csr &= ~CSR_WCOUNT_MASK;
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ch->csr |= ((req->size>>2) - 1) << CSR_WCOUNT_SHIFT;
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csr |= CSR_ONCE;
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ch->req_transfer_count = (req->size >> 2) - 1;
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} else {
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ch->csr &= ~CSR_ONCE;
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ch->ahb_seq |= AHB_SEQ_DBL_BUF;
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ahb_seq |= AHB_SEQ_DBL_BUF;
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/* In double buffered mode, we set the size to half the
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* requested size and interrupt when half the buffer
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* is full */
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ch->csr &= ~CSR_WCOUNT_MASK;
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ch->csr |= ((req->size>>3) - 1) << CSR_WCOUNT_SHIFT;
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ch->req_transfer_count = (req->size >> 3) - 1;
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}
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csr |= ch->req_transfer_count << CSR_WCOUNT_SHIFT;
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if (req->to_memory) {
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ch->csr &= ~CSR_DIR;
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ch->apb_ptr = req->source_addr;
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ch->ahb_ptr = req->dest_addr;
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apb_ptr = req->source_addr;
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ahb_ptr = req->dest_addr;
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apb_addr_wrap = req->source_wrap;
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ahb_addr_wrap = req->dest_wrap;
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ahb_bus_width = req->dest_bus_width;
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} else {
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ch->csr |= CSR_DIR;
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ch->apb_ptr = req->dest_addr;
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ch->ahb_ptr = req->source_addr;
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csr |= CSR_DIR;
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apb_ptr = req->dest_addr;
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ahb_ptr = req->source_addr;
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apb_addr_wrap = req->dest_wrap;
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ahb_addr_wrap = req->source_wrap;
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@ -461,8 +464,7 @@ static void tegra_dma_update_hw(struct tegra_dma_channel *ch,
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index++;
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} while (index < ARRAY_SIZE(apb_addr_wrap_table));
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BUG_ON(index == ARRAY_SIZE(apb_addr_wrap_table));
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ch->apb_seq &= ~APB_SEQ_WRAP_MASK;
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ch->apb_seq |= index << APB_SEQ_WRAP_SHIFT;
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apb_seq |= index << APB_SEQ_WRAP_SHIFT;
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/* set address wrap for AHB size */
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index = 0;
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index++;
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} while (index < ARRAY_SIZE(ahb_addr_wrap_table));
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BUG_ON(index == ARRAY_SIZE(ahb_addr_wrap_table));
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ch->ahb_seq &= ~AHB_SEQ_WRAP_MASK;
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ch->ahb_seq |= index << AHB_SEQ_WRAP_SHIFT;
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ahb_seq |= index << AHB_SEQ_WRAP_SHIFT;
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for (index = 0; index < ARRAY_SIZE(bus_width_table); index++) {
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if (bus_width_table[index] == ahb_bus_width)
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break;
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}
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BUG_ON(index == ARRAY_SIZE(bus_width_table));
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ch->ahb_seq &= ~AHB_SEQ_BUS_WIDTH_MASK;
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ch->ahb_seq |= index << AHB_SEQ_BUS_WIDTH_SHIFT;
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ahb_seq |= index << AHB_SEQ_BUS_WIDTH_SHIFT;
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for (index = 0; index < ARRAY_SIZE(bus_width_table); index++) {
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if (bus_width_table[index] == apb_bus_width)
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break;
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}
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BUG_ON(index == ARRAY_SIZE(bus_width_table));
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ch->apb_seq &= ~APB_SEQ_BUS_WIDTH_MASK;
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ch->apb_seq |= index << APB_SEQ_BUS_WIDTH_SHIFT;
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apb_seq |= index << APB_SEQ_BUS_WIDTH_SHIFT;
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ch->csr |= CSR_IE_EOC;
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writel(csr, ch->addr + APB_DMA_CHAN_CSR);
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writel(apb_seq, ch->addr + APB_DMA_CHAN_APB_SEQ);
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writel(apb_ptr, ch->addr + APB_DMA_CHAN_APB_PTR);
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writel(ahb_seq, ch->addr + APB_DMA_CHAN_AHB_SEQ);
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writel(ahb_ptr, ch->addr + APB_DMA_CHAN_AHB_PTR);
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/* update hw registers with the shadow */
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writel(ch->csr, ch->addr + APB_DMA_CHAN_CSR);
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writel(ch->apb_seq, ch->addr + APB_DMA_CHAN_APB_SEQ);
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writel(ch->apb_ptr, ch->addr + APB_DMA_CHAN_APB_PTR);
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writel(ch->ahb_seq, ch->addr + APB_DMA_CHAN_AHB_SEQ);
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writel(ch->ahb_ptr, ch->addr + APB_DMA_CHAN_AHB_PTR);
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csr = ch->csr | CSR_ENB;
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csr |= CSR_ENB;
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writel(csr, ch->addr + APB_DMA_CHAN_CSR);
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req->status = TEGRA_DMA_REQ_INFLIGHT;
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}
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static void tegra_dma_init_hw(struct tegra_dma_channel *ch)
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{
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/* One shot with an interrupt to CPU after transfer */
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ch->csr = CSR_ONCE | CSR_IE_EOC;
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ch->ahb_seq = AHB_SEQ_BUS_WIDTH_32 | AHB_SEQ_INTR_ENB;
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ch->apb_seq = APB_SEQ_BUS_WIDTH_32 | 1 << APB_SEQ_WRAP_SHIFT;
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}
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static void handle_oneshot_dma(struct tegra_dma_channel *ch)
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{
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struct tegra_dma_req *req;
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unsigned long irq_flags;
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spin_lock(&ch->lock);
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spin_lock_irqsave(&ch->lock, irq_flags);
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if (list_empty(&ch->list)) {
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spin_unlock(&ch->lock);
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spin_unlock_irqrestore(&ch->lock, irq_flags);
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return;
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}
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@ -528,8 +517,7 @@ static void handle_oneshot_dma(struct tegra_dma_channel *ch)
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if (req) {
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int bytes_transferred;
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bytes_transferred =
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(ch->csr & CSR_WCOUNT_MASK) >> CSR_WCOUNT_SHIFT;
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bytes_transferred = ch->req_transfer_count;
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bytes_transferred += 1;
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bytes_transferred <<= 2;
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@ -537,12 +525,12 @@ static void handle_oneshot_dma(struct tegra_dma_channel *ch)
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req->bytes_transferred = bytes_transferred;
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req->status = TEGRA_DMA_REQ_SUCCESS;
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spin_unlock(&ch->lock);
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spin_unlock_irqrestore(&ch->lock, irq_flags);
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/* Callback should be called without any lock */
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pr_debug("%s: transferred %d bytes\n", __func__,
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req->bytes_transferred);
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req->complete(req);
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spin_lock(&ch->lock);
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spin_lock_irqsave(&ch->lock, irq_flags);
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}
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if (!list_empty(&ch->list)) {
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@ -552,22 +540,55 @@ static void handle_oneshot_dma(struct tegra_dma_channel *ch)
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if (req->status != TEGRA_DMA_REQ_INFLIGHT)
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tegra_dma_update_hw(ch, req);
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}
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spin_unlock(&ch->lock);
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spin_unlock_irqrestore(&ch->lock, irq_flags);
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}
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static void handle_continuous_dma(struct tegra_dma_channel *ch)
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{
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struct tegra_dma_req *req;
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unsigned long irq_flags;
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spin_lock(&ch->lock);
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spin_lock_irqsave(&ch->lock, irq_flags);
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if (list_empty(&ch->list)) {
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spin_unlock(&ch->lock);
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spin_unlock_irqrestore(&ch->lock, irq_flags);
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return;
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}
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req = list_entry(ch->list.next, typeof(*req), node);
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if (req) {
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if (req->buffer_status == TEGRA_DMA_REQ_BUF_STATUS_EMPTY) {
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bool is_dma_ping_complete;
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is_dma_ping_complete = (readl(ch->addr + APB_DMA_CHAN_STA)
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& STA_PING_PONG) ? true : false;
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if (req->to_memory)
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is_dma_ping_complete = !is_dma_ping_complete;
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/* Out of sync - Release current buffer */
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if (!is_dma_ping_complete) {
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int bytes_transferred;
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bytes_transferred = ch->req_transfer_count;
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bytes_transferred += 1;
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bytes_transferred <<= 3;
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req->buffer_status = TEGRA_DMA_REQ_BUF_STATUS_FULL;
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req->bytes_transferred = bytes_transferred;
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req->status = TEGRA_DMA_REQ_SUCCESS;
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tegra_dma_stop(ch);
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if (!list_is_last(&req->node, &ch->list)) {
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struct tegra_dma_req *next_req;
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next_req = list_entry(req->node.next,
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typeof(*next_req), node);
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tegra_dma_update_hw(ch, next_req);
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}
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list_del(&req->node);
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/* DMA lock is NOT held when callbak is called */
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spin_unlock_irqrestore(&ch->lock, irq_flags);
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req->complete(req);
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return;
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}
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/* Load the next request into the hardware, if available
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* */
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if (!list_is_last(&req->node, &ch->list)) {
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@ -580,7 +601,7 @@ static void handle_continuous_dma(struct tegra_dma_channel *ch)
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req->buffer_status = TEGRA_DMA_REQ_BUF_STATUS_HALF_FULL;
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req->status = TEGRA_DMA_REQ_SUCCESS;
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/* DMA lock is NOT held when callback is called */
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spin_unlock(&ch->lock);
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spin_unlock_irqrestore(&ch->lock, irq_flags);
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if (likely(req->threshold))
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req->threshold(req);
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return;
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@ -591,8 +612,7 @@ static void handle_continuous_dma(struct tegra_dma_channel *ch)
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* the second interrupt */
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int bytes_transferred;
|
||||
|
||||
bytes_transferred =
|
||||
(ch->csr & CSR_WCOUNT_MASK) >> CSR_WCOUNT_SHIFT;
|
||||
bytes_transferred = ch->req_transfer_count;
|
||||
bytes_transferred += 1;
|
||||
bytes_transferred <<= 3;
|
||||
|
||||
|
@ -602,7 +622,7 @@ static void handle_continuous_dma(struct tegra_dma_channel *ch)
|
|||
list_del(&req->node);
|
||||
|
||||
/* DMA lock is NOT held when callbak is called */
|
||||
spin_unlock(&ch->lock);
|
||||
spin_unlock_irqrestore(&ch->lock, irq_flags);
|
||||
req->complete(req);
|
||||
return;
|
||||
|
||||
|
@ -610,7 +630,7 @@ static void handle_continuous_dma(struct tegra_dma_channel *ch)
|
|||
BUG();
|
||||
}
|
||||
}
|
||||
spin_unlock(&ch->lock);
|
||||
spin_unlock_irqrestore(&ch->lock, irq_flags);
|
||||
}
|
||||
|
||||
static irqreturn_t dma_isr(int irq, void *data)
|
||||
|
@ -674,7 +694,6 @@ int __init tegra_dma_init(void)
|
|||
|
||||
spin_lock_init(&ch->lock);
|
||||
INIT_LIST_HEAD(&ch->list);
|
||||
tegra_dma_init_hw(ch);
|
||||
|
||||
irq = INT_APB_DMA_CH0 + i;
|
||||
ret = request_threaded_irq(irq, dma_isr, dma_thread_fn, 0,
|
||||
|
|
Loading…
Reference in a new issue