net: thunderx: Add 81xx support to BGX driver
This patch adds support for BGX module on 81xx where a BGX can be split and have different LMACs configured in different modes. Signed-off-by: Sunil Goutham <sgoutham@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>hifive-unleashed-5.1
Sunil Goutham
David S. Miller
parent
0bcb7d510c
commit
57aaf63cb1
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@ -50,6 +50,7 @@ struct bgx {
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int lmac_count;
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void __iomem *reg_base;
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struct pci_dev *pdev;
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bool is_81xx;
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};
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static struct bgx *bgx_vnic[MAX_BGX_THUNDER];
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@ -803,9 +804,17 @@ static void bgx_print_qlm_mode(struct bgx *bgx, u8 lmacid)
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struct device *dev = &bgx->pdev->dev;
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struct lmac *lmac;
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char str[20];
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u8 dlm;
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if (lmacid > MAX_LMAC_PER_BGX)
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return;
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lmac = &bgx->lmac[lmacid];
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sprintf(str, "BGX%d QLM mode", bgx->bgx_id);
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dlm = (lmacid / 2) + (bgx->bgx_id * 2);
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if (!bgx->is_81xx)
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sprintf(str, "BGX%d QLM mode", bgx->bgx_id);
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else
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sprintf(str, "BGX%d DLM%d mode", bgx->bgx_id, dlm);
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switch (lmac->lmac_type) {
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case BGX_MODE_SGMII:
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@ -857,26 +866,81 @@ static void lmac_set_lane2sds(struct lmac *lmac)
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static void bgx_set_lmac_config(struct bgx *bgx, u8 idx)
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{
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struct lmac *lmac;
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struct lmac *olmac;
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u64 cmr_cfg;
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u8 lmac_type;
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u8 lane_to_sds;
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lmac = &bgx->lmac[idx];
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lmac->lmacid = idx;
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/* Read LMAC0 type to figure out QLM mode
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* This is configured by low level firmware
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if (!bgx->is_81xx) {
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/* Read LMAC0 type to figure out QLM mode
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* This is configured by low level firmware
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*/
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cmr_cfg = bgx_reg_read(bgx, 0, BGX_CMRX_CFG);
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lmac->lmac_type = (cmr_cfg >> 8) & 0x07;
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lmac->use_training =
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bgx_reg_read(bgx, 0, BGX_SPUX_BR_PMD_CRTL) &
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SPU_PMD_CRTL_TRAIN_EN;
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lmac_set_lane2sds(lmac);
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return;
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}
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/* On 81xx BGX can be split across 2 DLMs
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* firmware programs lmac_type of LMAC0 and LMAC2
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*/
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cmr_cfg = bgx_reg_read(bgx, 0, BGX_CMRX_CFG);
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lmac->lmac_type = (cmr_cfg >> 8) & 0x07;
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lmac->use_training =
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bgx_reg_read(bgx, 0, BGX_SPUX_BR_PMD_CRTL) &
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if ((idx == 0) || (idx == 2)) {
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cmr_cfg = bgx_reg_read(bgx, idx, BGX_CMRX_CFG);
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lmac_type = (u8)((cmr_cfg >> 8) & 0x07);
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lane_to_sds = (u8)(cmr_cfg & 0xFF);
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/* Check if config is not reset value */
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if ((lmac_type == 0) && (lane_to_sds == 0xE4))
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lmac->lmac_type = BGX_MODE_INVALID;
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else
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lmac->lmac_type = lmac_type;
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lmac->use_training =
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bgx_reg_read(bgx, idx, BGX_SPUX_BR_PMD_CRTL) &
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SPU_PMD_CRTL_TRAIN_EN;
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lmac_set_lane2sds(lmac);
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/* Set LMAC type of other lmac on same DLM i.e LMAC 1/3 */
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olmac = &bgx->lmac[idx + 1];
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olmac->lmac_type = lmac->lmac_type;
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olmac->use_training =
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bgx_reg_read(bgx, idx + 1, BGX_SPUX_BR_PMD_CRTL) &
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SPU_PMD_CRTL_TRAIN_EN;
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lmac_set_lane2sds(lmac);
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lmac_set_lane2sds(olmac);
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}
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}
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static bool is_dlm0_in_bgx_mode(struct bgx *bgx)
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{
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struct lmac *lmac;
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if (!bgx->is_81xx)
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return true;
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lmac = &bgx->lmac[1];
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if (lmac->lmac_type == BGX_MODE_INVALID)
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return false;
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return true;
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}
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static void bgx_get_qlm_mode(struct bgx *bgx)
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{
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struct lmac *lmac;
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struct lmac *lmac01;
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struct lmac *lmac23;
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u8 idx;
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/* Init all LMAC's type to invalid */
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for (idx = 0; idx < MAX_LMAC_PER_BGX; idx++) {
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lmac = &bgx->lmac[idx];
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lmac->lmac_type = BGX_MODE_INVALID;
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lmac->lmacid = idx;
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}
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/* It is assumed that low level firmware sets this value */
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bgx->lmac_count = bgx_reg_read(bgx, 0, BGX_CMR_RX_LMACS) & 0x7;
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if (bgx->lmac_count > MAX_LMAC_PER_BGX)
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@ -884,7 +948,28 @@ static void bgx_get_qlm_mode(struct bgx *bgx)
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for (idx = 0; idx < bgx->lmac_count; idx++)
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bgx_set_lmac_config(bgx, idx);
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bgx_print_qlm_mode(bgx, 0);
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if (!bgx->is_81xx) {
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bgx_print_qlm_mode(bgx, 0);
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return;
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}
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if (bgx->lmac_count) {
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bgx_print_qlm_mode(bgx, 0);
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bgx_print_qlm_mode(bgx, 2);
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}
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/* If DLM0 is not in BGX mode then LMAC0/1 have
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* to be configured with serdes lanes of DLM1
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*/
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if (is_dlm0_in_bgx_mode(bgx) || (bgx->lmac_count > 2))
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return;
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for (idx = 0; idx < bgx->lmac_count; idx++) {
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lmac01 = &bgx->lmac[idx];
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lmac23 = &bgx->lmac[idx + 2];
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lmac01->lmac_type = lmac23->lmac_type;
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lmac01->lane_to_sds = lmac23->lane_to_sds;
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}
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}
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#ifdef CONFIG_ACPI
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@ -1059,6 +1144,7 @@ static int bgx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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struct device *dev = &pdev->dev;
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struct bgx *bgx = NULL;
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u8 lmac;
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u16 sdevid;
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bgx = devm_kzalloc(dev, sizeof(*bgx), GFP_KERNEL);
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if (!bgx)
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@ -1080,6 +1166,10 @@ static int bgx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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goto err_disable_device;
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}
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pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &sdevid);
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if (sdevid == PCI_SUBSYS_DEVID_81XX_BGX)
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bgx->is_81xx = true;
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/* MAP configuration registers */
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bgx->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
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if (!bgx->reg_base) {
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@ -1105,6 +1195,8 @@ static int bgx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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if (err) {
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dev_err(dev, "BGX%d failed to enable lmac%d\n",
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bgx->bgx_id, lmac);
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while (lmac)
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bgx_lmac_disable(bgx, --lmac);
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goto err_enable;
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}
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}
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@ -9,6 +9,14 @@
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#ifndef THUNDER_BGX_H
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#define THUNDER_BGX_H
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/* PCI device ID */
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#define PCI_DEVICE_ID_THUNDER_BGX 0xA026
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/* Subsystem device IDs */
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#define PCI_SUBSYS_DEVID_88XX_BGX 0xA126
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#define PCI_SUBSYS_DEVID_81XX_BGX 0xA226
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#define PCI_SUBSYS_DEVID_83XX_BGX 0xA326
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#define MAX_BGX_THUNDER 8 /* Max 4 nodes, 2 per node */
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#define MAX_BGX_PER_CN88XX 2
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#define MAX_BGX_PER_CN81XX 2
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@ -215,6 +223,9 @@ enum LMAC_TYPE {
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BGX_MODE_XLAUI = 4, /* 4 lanes, 10.3125 Gbaud */
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BGX_MODE_10G_KR = 3,/* 1 lane, 10.3125 Gbaud */
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BGX_MODE_40G_KR = 4,/* 4 lanes, 10.3125 Gbaud */
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BGX_MODE_RGMII = 5,
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BGX_MODE_QSGMII = 6,
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BGX_MODE_INVALID = 7,
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};
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#endif /* THUNDER_BGX_H */
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