Merge tag 'gvt-fixes-2019-05-21' of https://github.com/intel/gvt-linux into drm-intel-fixes
gvt-fixes-2019-05-21 - vGPU reset fix with sane init breadcrumb (Weinan) - Fix TRTT handling to use context state (Yan) - Fix one error return (Dan) Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> From: Zhenyu Wang <zhenyuw@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190521062408.GH12913@zhen-hp.sh.intel.comhifive-unleashed-5.2
Joonas Lahtinen
commit
57cb853d1d
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@ -896,12 +896,16 @@ static int cmd_reg_handler(struct parser_exec_state *s,
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}
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/* TODO
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* Right now only scan LRI command on KBL and in inhibit context.
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* It's good enough to support initializing mmio by lri command in
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* vgpu inhibit context on KBL.
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* In order to let workload with inhibit context to generate
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* correct image data into memory, vregs values will be loaded to
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* hw via LRIs in the workload with inhibit context. But as
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* indirect context is loaded prior to LRIs in workload, we don't
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* want reg values specified in indirect context overwritten by
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* LRIs in workloads. So, when scanning an indirect context, we
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* update reg values in it into vregs, so LRIs in workload with
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* inhibit context will restore with correct values
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*/
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if ((IS_KABYLAKE(s->vgpu->gvt->dev_priv)
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|| IS_COFFEELAKE(s->vgpu->gvt->dev_priv)) &&
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if (IS_GEN(gvt->dev_priv, 9) &&
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intel_gvt_mmio_is_in_ctx(gvt, offset) &&
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!strncmp(cmd, "lri", 3)) {
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intel_gvt_hypervisor_read_gpa(s->vgpu,
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@ -1076,8 +1076,10 @@ static struct intel_vgpu_ppgtt_spt *ppgtt_populate_spt_by_guest_entry(
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} else {
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int type = get_next_pt_type(we->type);
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if (!gtt_type_is_pt(type))
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if (!gtt_type_is_pt(type)) {
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ret = -EINVAL;
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goto err;
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}
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spt = ppgtt_alloc_spt_gfn(vgpu, type, ops->get_pfn(we), ips);
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if (IS_ERR(spt)) {
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@ -1364,7 +1364,6 @@ static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset,
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static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset,
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void *p_data, unsigned int bytes)
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{
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struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
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u32 trtte = *(u32 *)p_data;
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if ((trtte & 1) && (trtte & (1 << 1)) == 0) {
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@ -1373,11 +1372,6 @@ static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset,
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return -EINVAL;
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}
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write_vreg(vgpu, offset, p_data, bytes);
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/* TRTTE is not per-context */
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mmio_hw_access_pre(dev_priv);
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I915_WRITE(_MMIO(offset), vgpu_vreg(vgpu, offset));
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mmio_hw_access_post(dev_priv);
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return 0;
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}
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@ -1385,15 +1379,6 @@ static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset,
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static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset,
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void *p_data, unsigned int bytes)
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{
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struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
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u32 val = *(u32 *)p_data;
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if (val & 1) {
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/* unblock hw logic */
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mmio_hw_access_pre(dev_priv);
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I915_WRITE(_MMIO(offset), val);
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mmio_hw_access_post(dev_priv);
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}
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write_vreg(vgpu, offset, p_data, bytes);
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return 0;
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}
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@ -108,12 +108,13 @@ static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = {
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{RCS0, GEN9_HALF_SLICE_CHICKEN5, 0xffff, true}, /* 0xe188 */
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{RCS0, GEN9_HALF_SLICE_CHICKEN7, 0xffff, true}, /* 0xe194 */
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{RCS0, GEN8_ROW_CHICKEN, 0xffff, true}, /* 0xe4f0 */
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{RCS0, TRVATTL3PTRDW(0), 0, false}, /* 0x4de0 */
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{RCS0, TRVATTL3PTRDW(1), 0, false}, /* 0x4de4 */
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{RCS0, TRNULLDETCT, 0, false}, /* 0x4de8 */
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{RCS0, TRINVTILEDETCT, 0, false}, /* 0x4dec */
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{RCS0, TRVADR, 0, false}, /* 0x4df0 */
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{RCS0, TRTTE, 0, false}, /* 0x4df4 */
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{RCS0, TRVATTL3PTRDW(0), 0, true}, /* 0x4de0 */
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{RCS0, TRVATTL3PTRDW(1), 0, true}, /* 0x4de4 */
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{RCS0, TRNULLDETCT, 0, true}, /* 0x4de8 */
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{RCS0, TRINVTILEDETCT, 0, true}, /* 0x4dec */
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{RCS0, TRVADR, 0, true}, /* 0x4df0 */
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{RCS0, TRTTE, 0, true}, /* 0x4df4 */
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{RCS0, _MMIO(0x4dfc), 0, true},
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{BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
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{BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
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@ -392,10 +393,7 @@ static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next,
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if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
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return;
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if (ring_id == RCS0 &&
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(IS_KABYLAKE(dev_priv) ||
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IS_BROXTON(dev_priv) ||
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IS_COFFEELAKE(dev_priv)))
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if (ring_id == RCS0 && IS_GEN(dev_priv, 9))
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return;
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if (!pre && !gen9_render_mocs.initialized)
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@ -470,11 +468,10 @@ static void switch_mmio(struct intel_vgpu *pre,
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continue;
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/*
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* No need to do save or restore of the mmio which is in context
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* state image on kabylake, it's initialized by lri command and
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* state image on gen9, it's initialized by lri command and
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* save or restore with context together.
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*/
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if ((IS_KABYLAKE(dev_priv) || IS_BROXTON(dev_priv)
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|| IS_COFFEELAKE(dev_priv)) && mmio->in_context)
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if (IS_GEN(dev_priv, 9) && mmio->in_context)
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continue;
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// save
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@ -298,12 +298,29 @@ static int copy_workload_to_ring_buffer(struct intel_vgpu_workload *workload)
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struct i915_request *req = workload->req;
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void *shadow_ring_buffer_va;
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u32 *cs;
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int err;
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if ((IS_KABYLAKE(req->i915) || IS_BROXTON(req->i915)
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|| IS_COFFEELAKE(req->i915))
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&& is_inhibit_context(req->hw_context))
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if (IS_GEN(req->i915, 9) && is_inhibit_context(req->hw_context))
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intel_vgpu_restore_inhibit_context(vgpu, req);
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/*
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* To track whether a request has started on HW, we can emit a
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* breadcrumb at the beginning of the request and check its
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* timeline's HWSP to see if the breadcrumb has advanced past the
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* start of this request. Actually, the request must have the
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* init_breadcrumb if its timeline set has_init_bread_crumb, or the
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* scheduler might get a wrong state of it during reset. Since the
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* requests from gvt always set the has_init_breadcrumb flag, here
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* need to do the emit_init_breadcrumb for all the requests.
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*/
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if (req->engine->emit_init_breadcrumb) {
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err = req->engine->emit_init_breadcrumb(req);
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if (err) {
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gvt_vgpu_err("fail to emit init breadcrumb\n");
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return err;
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}
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}
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/* allocate shadow ring buffer */
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cs = intel_ring_begin(workload->req, workload->rb_len / sizeof(u32));
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if (IS_ERR(cs)) {
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