drm/amdgpu: implement cgs gpu memory callbacks
This implements the cgs interface for allocating GPU memory. Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Chunming Zhou
Alex Deucher
parent
25da442779
commit
57ff96cf47
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@ -21,7 +21,11 @@
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*
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*
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*/
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#include <linux/list.h>
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#include <linux/slab.h>
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#include <linux/pci.h>
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#include <drm/drmP.h>
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#include <drm/amdgpu_drm.h>
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#include "amdgpu.h"
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#include "cgs_linux.h"
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#include "atom.h"
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@ -39,6 +43,30 @@ static int amdgpu_cgs_gpu_mem_info(void *cgs_device, enum cgs_gpu_mem_type type,
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uint64_t *mc_start, uint64_t *mc_size,
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uint64_t *mem_size)
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{
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CGS_FUNC_ADEV;
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switch(type) {
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case CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB:
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case CGS_GPU_MEM_TYPE__VISIBLE_FB:
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*mc_start = 0;
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*mc_size = adev->mc.visible_vram_size;
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*mem_size = adev->mc.visible_vram_size - adev->vram_pin_size;
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break;
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case CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB:
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case CGS_GPU_MEM_TYPE__INVISIBLE_FB:
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*mc_start = adev->mc.visible_vram_size;
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*mc_size = adev->mc.real_vram_size - adev->mc.visible_vram_size;
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*mem_size = *mc_size;
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break;
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case CGS_GPU_MEM_TYPE__GART_CACHEABLE:
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case CGS_GPU_MEM_TYPE__GART_WRITECOMBINE:
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*mc_start = adev->mc.gtt_start;
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*mc_size = adev->mc.gtt_size;
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*mem_size = adev->mc.gtt_size - adev->gart_pin_size;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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@ -47,11 +75,43 @@ static int amdgpu_cgs_gmap_kmem(void *cgs_device, void *kmem,
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uint64_t min_offset, uint64_t max_offset,
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cgs_handle_t *kmem_handle, uint64_t *mcaddr)
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{
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return 0;
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CGS_FUNC_ADEV;
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int ret;
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struct amdgpu_bo *bo;
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struct page *kmem_page = vmalloc_to_page(kmem);
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int npages = ALIGN(size, PAGE_SIZE) >> PAGE_SHIFT;
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struct sg_table *sg = drm_prime_pages_to_sg(&kmem_page, npages);
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ret = amdgpu_bo_create(adev, size, PAGE_SIZE, false,
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AMDGPU_GEM_DOMAIN_GTT, 0, sg, &bo);
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if (ret)
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return ret;
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ret = amdgpu_bo_reserve(bo, false);
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if (unlikely(ret != 0))
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return ret;
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/* pin buffer into GTT */
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ret = amdgpu_bo_pin_restricted(bo, AMDGPU_GEM_DOMAIN_GTT,
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min_offset, max_offset, mcaddr);
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amdgpu_bo_unreserve(bo);
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*kmem_handle = (cgs_handle_t)bo;
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return ret;
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}
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static int amdgpu_cgs_gunmap_kmem(void *cgs_device, cgs_handle_t kmem_handle)
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{
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struct amdgpu_bo *obj = (struct amdgpu_bo *)kmem_handle;
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if (obj) {
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int r = amdgpu_bo_reserve(obj, false);
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if (likely(r == 0)) {
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amdgpu_bo_unpin(obj);
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amdgpu_bo_unreserve(obj);
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}
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amdgpu_bo_unref(&obj);
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}
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return 0;
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}
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@ -61,46 +121,200 @@ static int amdgpu_cgs_alloc_gpu_mem(void *cgs_device,
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uint64_t min_offset, uint64_t max_offset,
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cgs_handle_t *handle)
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{
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return 0;
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CGS_FUNC_ADEV;
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uint16_t flags = 0;
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int ret = 0;
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uint32_t domain = 0;
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struct amdgpu_bo *obj;
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struct ttm_placement placement;
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struct ttm_place place;
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if (min_offset > max_offset) {
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BUG_ON(1);
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return -EINVAL;
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}
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/* fail if the alignment is not a power of 2 */
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if (((align != 1) && (align & (align - 1)))
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|| size == 0 || align == 0)
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return -EINVAL;
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switch(type) {
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case CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB:
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case CGS_GPU_MEM_TYPE__VISIBLE_FB:
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flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
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domain = AMDGPU_GEM_DOMAIN_VRAM;
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if (max_offset > adev->mc.real_vram_size)
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return -EINVAL;
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place.fpfn = min_offset >> PAGE_SHIFT;
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place.lpfn = max_offset >> PAGE_SHIFT;
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place.flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
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TTM_PL_FLAG_VRAM;
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break;
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case CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB:
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case CGS_GPU_MEM_TYPE__INVISIBLE_FB:
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flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
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domain = AMDGPU_GEM_DOMAIN_VRAM;
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if (adev->mc.visible_vram_size < adev->mc.real_vram_size) {
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place.fpfn =
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max(min_offset, adev->mc.visible_vram_size) >> PAGE_SHIFT;
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place.lpfn =
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min(max_offset, adev->mc.real_vram_size) >> PAGE_SHIFT;
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place.flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
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TTM_PL_FLAG_VRAM;
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}
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break;
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case CGS_GPU_MEM_TYPE__GART_CACHEABLE:
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domain = AMDGPU_GEM_DOMAIN_GTT;
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place.fpfn = min_offset >> PAGE_SHIFT;
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place.lpfn = max_offset >> PAGE_SHIFT;
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place.flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;
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break;
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case CGS_GPU_MEM_TYPE__GART_WRITECOMBINE:
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flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
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domain = AMDGPU_GEM_DOMAIN_GTT;
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place.fpfn = min_offset >> PAGE_SHIFT;
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place.lpfn = max_offset >> PAGE_SHIFT;
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place.flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT |
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TTM_PL_FLAG_UNCACHED;
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break;
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default:
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return -EINVAL;
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}
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*handle = 0;
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placement.placement = &place;
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placement.num_placement = 1;
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placement.busy_placement = &place;
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placement.num_busy_placement = 1;
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ret = amdgpu_bo_create_restricted(adev, size, PAGE_SIZE,
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true, domain, flags,
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NULL, &placement, &obj);
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if (ret) {
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DRM_ERROR("(%d) bo create failed\n", ret);
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return ret;
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}
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*handle = (cgs_handle_t)obj;
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return ret;
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}
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static int amdgpu_cgs_import_gpu_mem(void *cgs_device, int dmabuf_fd,
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cgs_handle_t *handle)
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{
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/* TODO */
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CGS_FUNC_ADEV;
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int r;
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uint32_t dma_handle;
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struct drm_gem_object *obj;
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struct amdgpu_bo *bo;
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struct drm_device *dev = adev->ddev;
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struct drm_file *file_priv = NULL, *priv;
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mutex_lock(&dev->struct_mutex);
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list_for_each_entry(priv, &dev->filelist, lhead) {
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rcu_read_lock();
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if (priv->pid == get_pid(task_pid(current)))
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file_priv = priv;
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rcu_read_unlock();
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if (file_priv)
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break;
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}
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mutex_unlock(&dev->struct_mutex);
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r = dev->driver->prime_fd_to_handle(dev,
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file_priv, dmabuf_fd,
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&dma_handle);
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spin_lock(&file_priv->table_lock);
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/* Check if we currently have a reference on the object */
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obj = idr_find(&file_priv->object_idr, dma_handle);
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if (obj == NULL) {
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spin_unlock(&file_priv->table_lock);
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return -EINVAL;
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}
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spin_unlock(&file_priv->table_lock);
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bo = gem_to_amdgpu_bo(obj);
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*handle = (cgs_handle_t)bo;
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return 0;
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}
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static int amdgpu_cgs_free_gpu_mem(void *cgs_device, cgs_handle_t handle)
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{
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/* TODO */
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struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
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if (obj) {
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int r = amdgpu_bo_reserve(obj, false);
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if (likely(r == 0)) {
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amdgpu_bo_kunmap(obj);
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amdgpu_bo_unpin(obj);
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amdgpu_bo_unreserve(obj);
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}
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amdgpu_bo_unref(&obj);
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}
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return 0;
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}
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static int amdgpu_cgs_gmap_gpu_mem(void *cgs_device, cgs_handle_t handle,
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uint64_t *mcaddr)
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{
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/* TODO */
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return 0;
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int r;
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u64 min_offset, max_offset;
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struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
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WARN_ON_ONCE(obj->placement.num_placement > 1);
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min_offset = obj->placements[0].fpfn << PAGE_SHIFT;
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max_offset = obj->placements[0].lpfn << PAGE_SHIFT;
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r = amdgpu_bo_reserve(obj, false);
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if (unlikely(r != 0))
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return r;
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r = amdgpu_bo_pin_restricted(obj, AMDGPU_GEM_DOMAIN_GTT,
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min_offset, max_offset, mcaddr);
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amdgpu_bo_unreserve(obj);
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return r;
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}
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static int amdgpu_cgs_gunmap_gpu_mem(void *cgs_device, cgs_handle_t handle)
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{
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/* TODO */
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return 0;
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int r;
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struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
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r = amdgpu_bo_reserve(obj, false);
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if (unlikely(r != 0))
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return r;
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r = amdgpu_bo_unpin(obj);
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amdgpu_bo_unreserve(obj);
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return r;
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}
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static int amdgpu_cgs_kmap_gpu_mem(void *cgs_device, cgs_handle_t handle,
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void **map)
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{
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/* TODO */
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return 0;
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int r;
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struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
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r = amdgpu_bo_reserve(obj, false);
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if (unlikely(r != 0))
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return r;
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r = amdgpu_bo_kmap(obj, map);
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amdgpu_bo_unreserve(obj);
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return r;
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}
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static int amdgpu_cgs_kunmap_gpu_mem(void *cgs_device, cgs_handle_t handle)
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{
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/* TODO */
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return 0;
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int r;
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struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
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r = amdgpu_bo_reserve(obj, false);
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if (unlikely(r != 0))
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return r;
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amdgpu_bo_kunmap(obj);
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amdgpu_bo_unreserve(obj);
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return r;
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}
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static uint32_t amdgpu_cgs_read_register(void *cgs_device, unsigned offset)
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