forcedeth: statistics supported
This patch introduces hw statistics for older devices that supported it. It breaks up the counters supported into separate versions. Signed-Off-By: Ayaz Abdulla <aabdulla@nvidia.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
parent
4e16ed1b0e
commit
57fff6986b
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@ -173,9 +173,10 @@
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#define DEV_HAS_MSI_X 0x0080 /* device supports MSI-X */
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#define DEV_HAS_MSI_X 0x0080 /* device supports MSI-X */
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#define DEV_HAS_POWER_CNTRL 0x0100 /* device supports power savings */
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#define DEV_HAS_POWER_CNTRL 0x0100 /* device supports power savings */
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#define DEV_HAS_PAUSEFRAME_TX 0x0200 /* device supports tx pause frames */
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#define DEV_HAS_PAUSEFRAME_TX 0x0200 /* device supports tx pause frames */
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#define DEV_HAS_STATISTICS 0x0400 /* device supports hw statistics */
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#define DEV_HAS_STATISTICS_V1 0x0400 /* device supports hw statistics version 1 */
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#define DEV_HAS_TEST_EXTENDED 0x0800 /* device supports extended diagnostic test */
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#define DEV_HAS_STATISTICS_V2 0x0800 /* device supports hw statistics version 2 */
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#define DEV_HAS_MGMT_UNIT 0x1000 /* device supports management unit */
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#define DEV_HAS_TEST_EXTENDED 0x1000 /* device supports extended diagnostic test */
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#define DEV_HAS_MGMT_UNIT 0x2000 /* device supports management unit */
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enum {
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enum {
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NvRegIrqStatus = 0x000,
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NvRegIrqStatus = 0x000,
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@ -487,7 +488,8 @@ union ring_type {
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/* Miscelaneous hardware related defines: */
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/* Miscelaneous hardware related defines: */
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#define NV_PCI_REGSZ_VER1 0x270
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#define NV_PCI_REGSZ_VER1 0x270
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#define NV_PCI_REGSZ_VER2 0x604
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#define NV_PCI_REGSZ_VER2 0x2d4
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#define NV_PCI_REGSZ_VER3 0x604
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/* various timeout delays: all in usec */
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/* various timeout delays: all in usec */
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#define NV_TXRX_RESET_DELAY 4
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#define NV_TXRX_RESET_DELAY 4
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@ -605,9 +607,6 @@ static const struct nv_ethtool_str nv_estats_str[] = {
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{ "tx_carrier_errors" },
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{ "tx_carrier_errors" },
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{ "tx_excess_deferral" },
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{ "tx_excess_deferral" },
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{ "tx_retry_error" },
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{ "tx_retry_error" },
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{ "tx_deferral" },
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{ "tx_packets" },
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{ "tx_pause" },
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{ "rx_frame_error" },
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{ "rx_frame_error" },
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{ "rx_extra_byte" },
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{ "rx_extra_byte" },
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{ "rx_late_collision" },
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{ "rx_late_collision" },
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@ -620,11 +619,17 @@ static const struct nv_ethtool_str nv_estats_str[] = {
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{ "rx_unicast" },
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{ "rx_unicast" },
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{ "rx_multicast" },
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{ "rx_multicast" },
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{ "rx_broadcast" },
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{ "rx_broadcast" },
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{ "rx_bytes" },
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{ "rx_pause" },
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{ "rx_drop_frame" },
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{ "rx_packets" },
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{ "rx_packets" },
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{ "rx_errors_total" }
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{ "rx_errors_total" },
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{ "tx_errors_total" },
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/* version 2 stats */
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{ "tx_deferral" },
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{ "tx_packets" },
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{ "rx_bytes" },
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{ "tx_pause" },
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{ "rx_pause" },
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{ "rx_drop_frame" }
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};
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};
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struct nv_ethtool_stats {
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struct nv_ethtool_stats {
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@ -637,9 +642,6 @@ struct nv_ethtool_stats {
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u64 tx_carrier_errors;
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u64 tx_carrier_errors;
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u64 tx_excess_deferral;
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u64 tx_excess_deferral;
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u64 tx_retry_error;
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u64 tx_retry_error;
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u64 tx_deferral;
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u64 tx_packets;
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u64 tx_pause;
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u64 rx_frame_error;
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u64 rx_frame_error;
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u64 rx_extra_byte;
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u64 rx_extra_byte;
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u64 rx_late_collision;
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u64 rx_late_collision;
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@ -652,13 +654,22 @@ struct nv_ethtool_stats {
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u64 rx_unicast;
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u64 rx_unicast;
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u64 rx_multicast;
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u64 rx_multicast;
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u64 rx_broadcast;
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u64 rx_broadcast;
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u64 rx_bytes;
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u64 rx_pause;
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u64 rx_drop_frame;
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u64 rx_packets;
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u64 rx_packets;
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u64 rx_errors_total;
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u64 rx_errors_total;
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u64 tx_errors_total;
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/* version 2 stats */
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u64 tx_deferral;
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u64 tx_packets;
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u64 rx_bytes;
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u64 tx_pause;
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u64 rx_pause;
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u64 rx_drop_frame;
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};
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};
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#define NV_DEV_STATISTICS_V2_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
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#define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
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/* diagnostics */
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/* diagnostics */
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#define NV_TEST_COUNT_BASE 3
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#define NV_TEST_COUNT_BASE 3
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#define NV_TEST_COUNT_EXTENDED 4
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#define NV_TEST_COUNT_EXTENDED 4
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@ -1275,6 +1286,61 @@ static void nv_mac_reset(struct net_device *dev)
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pci_push(base);
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pci_push(base);
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}
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}
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static void nv_get_hw_stats(struct net_device *dev)
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{
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struct fe_priv *np = netdev_priv(dev);
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u8 __iomem *base = get_hwbase(dev);
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np->estats.tx_bytes += readl(base + NvRegTxCnt);
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np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
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np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
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np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
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np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
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np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
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np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
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np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
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np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
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np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
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np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
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np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
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np->estats.rx_runt += readl(base + NvRegRxRunt);
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np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
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np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
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np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
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np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
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np->estats.rx_length_error += readl(base + NvRegRxLenErr);
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np->estats.rx_unicast += readl(base + NvRegRxUnicast);
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np->estats.rx_multicast += readl(base + NvRegRxMulticast);
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np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
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np->estats.rx_packets =
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np->estats.rx_unicast +
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np->estats.rx_multicast +
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np->estats.rx_broadcast;
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np->estats.rx_errors_total =
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np->estats.rx_crc_errors +
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np->estats.rx_over_errors +
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np->estats.rx_frame_error +
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(np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
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np->estats.rx_late_collision +
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np->estats.rx_runt +
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np->estats.rx_frame_too_long;
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np->estats.tx_errors_total =
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np->estats.tx_late_collision +
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np->estats.tx_fifo_errors +
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np->estats.tx_carrier_errors +
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np->estats.tx_excess_deferral +
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np->estats.tx_retry_error;
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if (np->driver_data & DEV_HAS_STATISTICS_V2) {
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np->estats.tx_deferral += readl(base + NvRegTxDef);
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np->estats.tx_packets += readl(base + NvRegTxFrame);
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np->estats.rx_bytes += readl(base + NvRegRxCnt);
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np->estats.tx_pause += readl(base + NvRegTxPause);
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np->estats.rx_pause += readl(base + NvRegRxPause);
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np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
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}
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}
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/*
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/*
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* nv_get_stats: dev->get_stats function
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* nv_get_stats: dev->get_stats function
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* Get latest stats value from the nic.
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* Get latest stats value from the nic.
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@ -3502,47 +3568,8 @@ static void nv_do_stats_poll(unsigned long data)
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{
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{
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struct net_device *dev = (struct net_device *) data;
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struct net_device *dev = (struct net_device *) data;
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struct fe_priv *np = netdev_priv(dev);
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struct fe_priv *np = netdev_priv(dev);
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u8 __iomem *base = get_hwbase(dev);
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np->estats.tx_bytes += readl(base + NvRegTxCnt);
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nv_get_hw_stats(dev);
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np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
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np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
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np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
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np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
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np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
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np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
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np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
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np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
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np->estats.tx_deferral += readl(base + NvRegTxDef);
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np->estats.tx_packets += readl(base + NvRegTxFrame);
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np->estats.tx_pause += readl(base + NvRegTxPause);
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np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
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np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
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np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
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np->estats.rx_runt += readl(base + NvRegRxRunt);
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np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
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np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
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np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
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np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
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np->estats.rx_length_error += readl(base + NvRegRxLenErr);
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np->estats.rx_unicast += readl(base + NvRegRxUnicast);
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np->estats.rx_multicast += readl(base + NvRegRxMulticast);
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np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
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np->estats.rx_bytes += readl(base + NvRegRxCnt);
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np->estats.rx_pause += readl(base + NvRegRxPause);
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np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
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np->estats.rx_packets =
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np->estats.rx_unicast +
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np->estats.rx_multicast +
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np->estats.rx_broadcast;
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np->estats.rx_errors_total =
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np->estats.rx_crc_errors +
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np->estats.rx_over_errors +
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np->estats.rx_frame_error +
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(np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
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np->estats.rx_late_collision +
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np->estats.rx_runt +
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np->estats.rx_frame_too_long;
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if (!np->in_shutdown)
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if (!np->in_shutdown)
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mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
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mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
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@ -4161,8 +4188,10 @@ static int nv_get_stats_count(struct net_device *dev)
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{
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{
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struct fe_priv *np = netdev_priv(dev);
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struct fe_priv *np = netdev_priv(dev);
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if (np->driver_data & DEV_HAS_STATISTICS)
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if (np->driver_data & DEV_HAS_STATISTICS_V1)
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return sizeof(struct nv_ethtool_stats)/sizeof(u64);
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return NV_DEV_STATISTICS_V1_COUNT;
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else if (np->driver_data & DEV_HAS_STATISTICS_V2)
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return NV_DEV_STATISTICS_V2_COUNT;
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else
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else
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return 0;
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return 0;
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}
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}
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mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
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mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
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/* start statistics timer */
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/* start statistics timer */
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if (np->driver_data & DEV_HAS_STATISTICS)
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if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2))
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mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
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mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
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spin_unlock_irq(&np->lock);
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spin_unlock_irq(&np->lock);
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@ -4846,7 +4875,9 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
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if (err < 0)
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if (err < 0)
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goto out_disable;
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goto out_disable;
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if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS))
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if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2))
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np->register_size = NV_PCI_REGSZ_VER3;
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else if (id->driver_data & DEV_HAS_STATISTICS_V1)
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np->register_size = NV_PCI_REGSZ_VER2;
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np->register_size = NV_PCI_REGSZ_VER2;
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else
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else
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np->register_size = NV_PCI_REGSZ_VER1;
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np->register_size = NV_PCI_REGSZ_VER1;
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@ -5295,83 +5326,83 @@ static struct pci_device_id pci_tbl[] = {
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},
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},
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{ /* CK804 Ethernet Controller */
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{ /* CK804 Ethernet Controller */
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
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.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
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.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1,
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},
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},
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{ /* CK804 Ethernet Controller */
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{ /* CK804 Ethernet Controller */
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
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.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
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.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1,
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},
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},
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{ /* MCP04 Ethernet Controller */
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{ /* MCP04 Ethernet Controller */
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
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.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
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.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1,
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},
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},
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{ /* MCP04 Ethernet Controller */
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{ /* MCP04 Ethernet Controller */
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
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.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
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.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1,
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},
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},
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{ /* MCP51 Ethernet Controller */
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{ /* MCP51 Ethernet Controller */
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
|
||||||
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL,
|
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1,
|
||||||
},
|
},
|
||||||
{ /* MCP51 Ethernet Controller */
|
{ /* MCP51 Ethernet Controller */
|
||||||
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
|
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
|
||||||
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL,
|
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1,
|
||||||
},
|
},
|
||||||
{ /* MCP55 Ethernet Controller */
|
{ /* MCP55 Ethernet Controller */
|
||||||
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
|
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
|
||||||
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
|
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
|
||||||
},
|
},
|
||||||
{ /* MCP55 Ethernet Controller */
|
{ /* MCP55 Ethernet Controller */
|
||||||
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
|
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
|
||||||
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
|
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
|
||||||
},
|
},
|
||||||
{ /* MCP61 Ethernet Controller */
|
{ /* MCP61 Ethernet Controller */
|
||||||
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16),
|
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16),
|
||||||
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
|
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
|
||||||
},
|
},
|
||||||
{ /* MCP61 Ethernet Controller */
|
{ /* MCP61 Ethernet Controller */
|
||||||
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17),
|
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17),
|
||||||
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
|
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
|
||||||
},
|
},
|
||||||
{ /* MCP61 Ethernet Controller */
|
{ /* MCP61 Ethernet Controller */
|
||||||
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18),
|
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18),
|
||||||
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
|
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
|
||||||
},
|
},
|
||||||
{ /* MCP61 Ethernet Controller */
|
{ /* MCP61 Ethernet Controller */
|
||||||
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19),
|
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19),
|
||||||
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
|
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
|
||||||
},
|
},
|
||||||
{ /* MCP65 Ethernet Controller */
|
{ /* MCP65 Ethernet Controller */
|
||||||
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20),
|
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20),
|
||||||
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
|
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
|
||||||
},
|
},
|
||||||
{ /* MCP65 Ethernet Controller */
|
{ /* MCP65 Ethernet Controller */
|
||||||
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21),
|
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21),
|
||||||
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
|
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
|
||||||
},
|
},
|
||||||
{ /* MCP65 Ethernet Controller */
|
{ /* MCP65 Ethernet Controller */
|
||||||
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22),
|
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22),
|
||||||
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
|
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
|
||||||
},
|
},
|
||||||
{ /* MCP65 Ethernet Controller */
|
{ /* MCP65 Ethernet Controller */
|
||||||
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23),
|
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23),
|
||||||
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
|
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
|
||||||
},
|
},
|
||||||
{ /* MCP67 Ethernet Controller */
|
{ /* MCP67 Ethernet Controller */
|
||||||
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_24),
|
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_24),
|
||||||
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
|
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
|
||||||
},
|
},
|
||||||
{ /* MCP67 Ethernet Controller */
|
{ /* MCP67 Ethernet Controller */
|
||||||
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_25),
|
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_25),
|
||||||
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
|
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
|
||||||
},
|
},
|
||||||
{ /* MCP67 Ethernet Controller */
|
{ /* MCP67 Ethernet Controller */
|
||||||
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_26),
|
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_26),
|
||||||
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
|
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
|
||||||
},
|
},
|
||||||
{ /* MCP67 Ethernet Controller */
|
{ /* MCP67 Ethernet Controller */
|
||||||
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_27),
|
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_27),
|
||||||
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
|
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
|
||||||
},
|
},
|
||||||
{0,},
|
{0,},
|
||||||
};
|
};
|
||||||
|
|
Loading…
Reference in a new issue