net: filter: Fix some more small issues in sparc JIT.
Fix mixed space and tabs. Put bpf_jit_load_*[] externs into bpf_jit.h "while(0)" --> "while (0)" "COND (X)" --> "COND(X)" Document branch offset calculations, and bpf_error's return sequence. Document the reason we need to emit three nops between the %y register write and the divide instruction. Remove erroneous trailing semicolons from emit_read_y() and emit_write_y(). Based upon feedback from Sam Ravnborg. Signed-off-by: David S. Miller <davem@davemloft.net>hifive-unleashed-5.1
David S. Miller
parent
7b56f76edf
commit
584c5e2ad3
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@ -38,6 +38,21 @@
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#define r_TMP G1
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#define r_TMP2 G2
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#define r_OFF G3
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/* assembly code in arch/sparc/net/bpf_jit_asm.S */
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extern u32 bpf_jit_load_word[];
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extern u32 bpf_jit_load_half[];
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extern u32 bpf_jit_load_byte[];
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extern u32 bpf_jit_load_byte_msh[];
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extern u32 bpf_jit_load_word_positive_offset[];
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extern u32 bpf_jit_load_half_positive_offset[];
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extern u32 bpf_jit_load_byte_positive_offset[];
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extern u32 bpf_jit_load_byte_msh_positive_offset[];
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extern u32 bpf_jit_load_word_negative_offset[];
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extern u32 bpf_jit_load_half_negative_offset[];
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extern u32 bpf_jit_load_byte_negative_offset[];
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extern u32 bpf_jit_load_byte_msh_negative_offset[];
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#else
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#define r_SKB %o0
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#define r_A %o1
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@ -195,5 +195,11 @@ bpf_jit_load_byte_msh_negative_offset:
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sll r_OFF, 2, r_X
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bpf_error:
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/* Make the JIT program return zero. The JIT epilogue
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* stores away the original %o7 into r_saved_O7. The
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* normal leaf function return is to use "retl" which
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* would evalute to "jmpl %o7 + 8, %g0" but we want to
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* use the saved value thus the sequence you see here.
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*/
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jmpl r_saved_O7 + 8, %g0
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clr %o0
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@ -11,20 +11,6 @@
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int bpf_jit_enable __read_mostly;
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/* assembly code in arch/sparc/net/bpf_jit_asm.S */
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extern u32 bpf_jit_load_word[];
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extern u32 bpf_jit_load_half[];
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extern u32 bpf_jit_load_byte[];
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extern u32 bpf_jit_load_byte_msh[];
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extern u32 bpf_jit_load_word_positive_offset[];
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extern u32 bpf_jit_load_half_positive_offset[];
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extern u32 bpf_jit_load_byte_positive_offset[];
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extern u32 bpf_jit_load_byte_msh_positive_offset[];
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extern u32 bpf_jit_load_word_negative_offset[];
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extern u32 bpf_jit_load_half_negative_offset[];
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extern u32 bpf_jit_load_byte_negative_offset[];
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extern u32 bpf_jit_load_byte_msh_negative_offset[];
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static inline bool is_simm13(unsigned int value)
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{
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return value + 0x1000 < 0x2000;
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@ -65,22 +51,22 @@ static void bpf_flush_icache(void *start_, void *end_)
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#define F2(X, Y) (OP(X) | OP2(Y))
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#define F3(X, Y) (OP(X) | OP3(Y))
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#define CONDN COND (0x0)
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#define CONDE COND (0x1)
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#define CONDLE COND (0x2)
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#define CONDL COND (0x3)
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#define CONDLEU COND (0x4)
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#define CONDCS COND (0x5)
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#define CONDNEG COND (0x6)
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#define CONDVC COND (0x7)
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#define CONDA COND (0x8)
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#define CONDNE COND (0x9)
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#define CONDG COND (0xa)
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#define CONDGE COND (0xb)
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#define CONDGU COND (0xc)
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#define CONDCC COND (0xd)
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#define CONDPOS COND (0xe)
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#define CONDVS COND (0xf)
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#define CONDN COND(0x0)
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#define CONDE COND(0x1)
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#define CONDLE COND(0x2)
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#define CONDL COND(0x3)
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#define CONDLEU COND(0x4)
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#define CONDCS COND(0x5)
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#define CONDNEG COND(0x6)
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#define CONDVC COND(0x7)
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#define CONDA COND(0x8)
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#define CONDNE COND(0x9)
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#define CONDG COND(0xa)
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#define CONDGE COND(0xb)
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#define CONDGU COND(0xc)
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#define CONDCC COND(0xd)
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#define CONDPOS COND(0xe)
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#define CONDVS COND(0xf)
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#define CONDGEU CONDCC
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#define CONDLU CONDCS
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@ -172,7 +158,7 @@ do { /* sethi %hi(K), REG */ \
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/* Emit
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*
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* OP r_A, r_X, r_A
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* OP r_A, r_X, r_A
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*/
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#define emit_alu_X(OPCODE) \
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do { \
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@ -195,7 +181,7 @@ do { \
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* is zero.
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*/
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#define emit_alu_K(OPCODE, K) \
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do { \
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do { \
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if (K) { \
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unsigned int _insn = OPCODE; \
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_insn |= RS1(r_A) | RD(r_A); \
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@ -204,7 +190,7 @@ do { \
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} else { \
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emit_set_const(K, r_TMP); \
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*prog++ = _insn | RS2(r_TMP); \
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} \
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} \
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} \
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} while (0)
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@ -222,37 +208,37 @@ do { \
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do { unsigned int _off = offsetof(STRUCT, FIELD); \
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BUILD_BUG_ON(FIELD_SIZEOF(STRUCT, FIELD) != sizeof(void *)); \
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*prog++ = LDPTRI | RS1(BASE) | S13(_off) | RD(DEST); \
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} while(0)
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} while (0)
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#define emit_load32(BASE, STRUCT, FIELD, DEST) \
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do { unsigned int _off = offsetof(STRUCT, FIELD); \
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BUILD_BUG_ON(FIELD_SIZEOF(STRUCT, FIELD) != sizeof(u32)); \
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*prog++ = LD32I | RS1(BASE) | S13(_off) | RD(DEST); \
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} while(0)
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} while (0)
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#define emit_load16(BASE, STRUCT, FIELD, DEST) \
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do { unsigned int _off = offsetof(STRUCT, FIELD); \
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BUILD_BUG_ON(FIELD_SIZEOF(STRUCT, FIELD) != sizeof(u16)); \
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*prog++ = LD16I | RS1(BASE) | S13(_off) | RD(DEST); \
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} while(0)
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} while (0)
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#define __emit_load8(BASE, STRUCT, FIELD, DEST) \
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do { unsigned int _off = offsetof(STRUCT, FIELD); \
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*prog++ = LD8I | RS1(BASE) | S13(_off) | RD(DEST); \
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} while(0)
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} while (0)
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#define emit_load8(BASE, STRUCT, FIELD, DEST) \
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do { BUILD_BUG_ON(FIELD_SIZEOF(STRUCT, FIELD) != sizeof(u8)); \
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__emit_load8(BASE, STRUCT, FIELD, DEST); \
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} while(0)
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} while (0)
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#define emit_ldmem(OFF, DEST) \
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do { *prog++ = LD32I | RS1(FP) | S13(-(OFF)) | RD(DEST); \
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} while(0)
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} while (0)
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#define emit_stmem(OFF, SRC) \
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do { *prog++ = LD32I | RS1(FP) | S13(-(OFF)) | RD(SRC); \
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} while(0)
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} while (0)
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#define cpu_off offsetof(struct thread_info, cpu)
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@ -292,16 +278,16 @@ do { void *_here = image + addrs[i] - 8; \
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#define emit_branch(BR_OPC, DEST) \
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do { unsigned int _here = addrs[i] - 8; \
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*prog++ = BR_OPC | WDISP22((DEST) - _here); \
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} while(0)
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} while (0)
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#define emit_branch_off(BR_OPC, OFF) \
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do { *prog++ = BR_OPC | WDISP22(OFF); \
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} while(0)
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} while (0)
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#define emit_jump(DEST) emit_branch(BA, DEST)
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#define emit_read_y(REG) *prog++ = RD_Y | RD(REG);
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#define emit_write_y(REG) *prog++ = WR_Y | IMMED | RS1(REG) | S13(0);
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#define emit_read_y(REG) *prog++ = RD_Y | RD(REG)
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#define emit_write_y(REG) *prog++ = WR_Y | IMMED | RS1(REG) | S13(0)
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#define emit_cmp(R1, R2) \
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*prog++ = (SUBCC | RS1(R1) | RS2(R2) | RD(G0))
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@ -333,6 +319,35 @@ do { *prog++ = BR_OPC | WDISP22(OFF); \
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#define emit_release_stack(SZ) \
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*prog++ = (ADD | IMMED | RS1(SP) | S13(SZ) | RD(SP))
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/* A note about branch offset calculations. The addrs[] array,
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* indexed by BPF instruction, records the address after all the
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* sparc instructions emitted for that BPF instruction.
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*
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* The most common case is to emit a branch at the end of such
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* a code sequence. So this would be two instructions, the
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* branch and it's delay slot.
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*
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* Therefore by default the branch emitters calculate the branch
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* offset field as:
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*
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* destination - (addrs[i] - 8)
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*
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* This "addrs[i] - 8" is the address of the branch itself or
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* what "." would be in assembler notation. The "8" part is
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* how we take into consideration the branch and it's delay
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* slot mentioned above.
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*
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* Sometimes we need to emit a branch earlier in the code
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* sequence. And in these situations we adjust "destination"
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* to accomodate this difference. For example, if we needed
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* to emit a branch (and it's delay slot) right before the
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* final instruction emitted for a BPF opcode, we'd use
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* "destination + 4" instead of just plain "destination" above.
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*
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* This is why you see all of these funny emit_branch() and
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* emit_jump() calls with adjusted offsets.
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*/
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void bpf_jit_compile(struct sk_filter *fp)
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{
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unsigned int cleanup_addr, proglen, oldproglen = 0;
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@ -493,6 +508,10 @@ void bpf_jit_compile(struct sk_filter *fp)
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}
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emit_write_y(G0);
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#ifdef CONFIG_SPARC32
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/* The Sparc v8 architecture requires
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* three instructions between a %y
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* register write and the first use.
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*/
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emit_nop();
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emit_nop();
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emit_nop();
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