ARM: S5PV210: Remove usage of clk_p83 and add clk_pclk_dsys clock\
The clk_p83 clock, which is the PCLK clock for DSYS domain, is of type 'struct clk' whereas on S5PV210, this clock is suitable to be of type clksrc_clk clock (since it has a clock divider). So this patch replaces the 'struct clk' type clock to 'struct clksrc_clk' type clock for the PCLK DSYS clock. This patch modifies the following. 1. Remove definitions and usage of 'clk_p83' clock. 2. Adds 'clk_pclk_dsys' clock which is of type 'struct clksrc_clk'. 3. Replace all usage of clk_p83 with clk_pclk_dsys clock. 4. Adds clk_pclk_dsys into list of clocks to be registered. Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
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@ -125,6 +125,15 @@ static struct clksrc_clk clk_hclk_dsys = {
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.reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
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};
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static struct clksrc_clk clk_pclk_dsys = {
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.clk = {
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.name = "pclk_dsys",
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.id = -1,
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.parent = &clk_hclk_dsys.clk,
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},
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.reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
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};
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static struct clksrc_clk clk_hclk_psys = {
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.clk = {
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.name = "hclk_psys",
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@ -155,18 +164,12 @@ static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
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return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
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}
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static struct clk clk_p83 = {
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.name = "pclk83",
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.id = -1,
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};
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static struct clk clk_p66 = {
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.name = "pclk66",
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.id = -1,
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};
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static struct clk *sys_clks[] = {
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&clk_p83,
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&clk_p66
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};
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@ -397,6 +400,7 @@ static struct clksrc_clk *sysclks[] = {
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&clk_hclk_dsys,
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&clk_hclk_psys,
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&clk_pclk_msys,
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&clk_pclk_dsys,
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};
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#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
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@ -410,7 +414,7 @@ void __init_or_cpufreq s5pv210_setup_clocks(void)
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unsigned long hclk_dsys;
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unsigned long hclk_psys;
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unsigned long pclk_msys;
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unsigned long pclk83;
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unsigned long pclk_dsys;
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unsigned long pclk66;
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unsigned long apll;
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unsigned long mpll;
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@ -450,19 +454,18 @@ void __init_or_cpufreq s5pv210_setup_clocks(void)
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hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk);
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hclk_psys = clk_get_rate(&clk_hclk_psys.clk);
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pclk_msys = clk_get_rate(&clk_pclk_msys.clk);
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pclk83 = hclk_dsys / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK83);
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pclk_dsys = clk_get_rate(&clk_pclk_dsys.clk);
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pclk66 = hclk_psys / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK66);
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printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n"
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"HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
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armclk, hclk_msys, hclk_dsys, hclk_psys,
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pclk_msys, pclk83, pclk66);
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pclk_msys, pclk_dsys, pclk66);
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clk_f.rate = armclk;
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clk_h.rate = hclk_psys;
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clk_p.rate = pclk66;
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clk_p66.rate = pclk66;
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clk_p83.rate = pclk83;
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for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
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s3c_set_clksrc(&clksrcs[ptr], true);
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