EDAC, altera: Add Arria10 L2 Cache ECC handling
Add a private data structure for Arria10 L2 cache ECC and the probe function for it. The Arria10 ECC device IRQs are in a shared register so the ECC Manager parent/child relationship requires a different probe function. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Cc: devicetree@vger.kernel.org Cc: dinguyen@opensource.altera.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux@arm.linux.org.uk Cc: linux-edac <linux-edac@vger.kernel.org> Link: http://lkml.kernel.org/r/1458576106-24505-8-git-send-email-tthayer@opensource.altera.com Signed-off-by: Borislav Petkov <bp@suse.de>hifive-unleashed-5.1
Thor Thayer
Borislav Petkov
parent
8b39ab7290
commit
588cb03ea2
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@ -24,6 +24,7 @@
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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@ -549,6 +550,7 @@ module_platform_driver(altr_edac_driver);
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const struct edac_device_prv_data ocramecc_data;
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const struct edac_device_prv_data l2ecc_data;
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const struct edac_device_prv_data a10_l2ecc_data;
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static irqreturn_t altr_edac_device_handler(int irq, void *dev_id)
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{
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@ -673,6 +675,8 @@ static void altr_create_edacdev_dbgfs(struct edac_device_ctl_info *edac_dci,
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static const struct of_device_id altr_edac_device_of_match[] = {
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#ifdef CONFIG_EDAC_ALTERA_L2C
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{ .compatible = "altr,socfpga-l2-ecc", .data = (void *)&l2ecc_data },
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{ .compatible = "altr,socfpga-a10-l2-ecc",
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.data = (void *)&a10_l2ecc_data },
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#endif
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#ifdef CONFIG_EDAC_ALTERA_OCRAM
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{ .compatible = "altr,socfpga-ocram-ecc",
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@ -941,6 +945,24 @@ static int altr_l2_check_deps(struct altr_edac_device_dev *device)
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return -ENODEV;
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}
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static irqreturn_t altr_edac_a10_l2_irq(struct altr_edac_device_dev *dci,
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bool sberr)
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{
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if (sberr) {
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regmap_write(dci->edac->ecc_mgr_map,
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A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST,
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A10_SYSGMR_MPU_CLEAR_L2_ECC_SB);
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edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);
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} else {
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regmap_write(dci->edac->ecc_mgr_map,
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A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST,
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A10_SYSGMR_MPU_CLEAR_L2_ECC_MB);
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edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
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panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
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}
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return IRQ_HANDLED;
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}
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const struct edac_device_prv_data l2ecc_data = {
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.setup = altr_l2_check_deps,
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.ce_clear_mask = 0,
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@ -955,8 +977,217 @@ const struct edac_device_prv_data l2ecc_data = {
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.trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE,
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};
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const struct edac_device_prv_data a10_l2ecc_data = {
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.setup = altr_l2_check_deps,
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.ce_clear_mask = ALTR_A10_L2_ECC_SERR_CLR,
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.ue_clear_mask = ALTR_A10_L2_ECC_MERR_CLR,
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.irq_status_mask = A10_SYSMGR_ECC_INTSTAT_L2,
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.dbgfs_name = "altr_l2_trigger",
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.alloc_mem = l2_alloc_mem,
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.free_mem = l2_free_mem,
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.ecc_enable_mask = ALTR_A10_L2_ECC_EN_CTL,
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.ce_set_mask = ALTR_A10_L2_ECC_CE_INJ_MASK,
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.ue_set_mask = ALTR_A10_L2_ECC_UE_INJ_MASK,
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.set_err_ofst = ALTR_A10_L2_ECC_INJ_OFST,
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.ecc_irq_handler = altr_edac_a10_l2_irq,
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.trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE,
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};
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#endif /* CONFIG_EDAC_ALTERA_L2C */
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/********************* Arria10 EDAC Device Functions *************************/
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/*
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* The Arria10 EDAC Device Functions differ from the Cyclone5/Arria5
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* because 2 IRQs are shared among the all ECC peripherals. The ECC
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* manager manages the IRQs and the children.
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* Based on xgene_edac.c peripheral code.
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*/
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static irqreturn_t altr_edac_a10_irq_handler(int irq, void *dev_id)
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{
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irqreturn_t rc = IRQ_NONE;
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struct altr_arria10_edac *edac = dev_id;
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struct altr_edac_device_dev *dci;
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int irq_status;
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bool sberr = (irq == edac->sb_irq) ? 1 : 0;
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int sm_offset = sberr ? A10_SYSMGR_ECC_INTSTAT_SERR_OFST :
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A10_SYSMGR_ECC_INTSTAT_DERR_OFST;
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regmap_read(edac->ecc_mgr_map, sm_offset, &irq_status);
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if ((irq != edac->sb_irq) && (irq != edac->db_irq)) {
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WARN_ON(1);
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} else {
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list_for_each_entry(dci, &edac->a10_ecc_devices, next) {
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if (irq_status & dci->data->irq_status_mask)
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rc = dci->data->ecc_irq_handler(dci, sberr);
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}
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}
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return rc;
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}
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static int altr_edac_a10_device_add(struct altr_arria10_edac *edac,
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struct device_node *np)
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{
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struct edac_device_ctl_info *dci;
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struct altr_edac_device_dev *altdev;
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char *ecc_name = (char *)np->name;
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struct resource res;
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int edac_idx;
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int rc = 0;
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const struct edac_device_prv_data *prv;
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/* Get matching node and check for valid result */
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const struct of_device_id *pdev_id =
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of_match_node(altr_edac_device_of_match, np);
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if (IS_ERR_OR_NULL(pdev_id))
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return -ENODEV;
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/* Get driver specific data for this EDAC device */
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prv = pdev_id->data;
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if (IS_ERR_OR_NULL(prv))
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return -ENODEV;
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if (!devres_open_group(edac->dev, altr_edac_a10_device_add, GFP_KERNEL))
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return -ENOMEM;
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rc = of_address_to_resource(np, 0, &res);
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if (rc < 0) {
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edac_printk(KERN_ERR, EDAC_DEVICE,
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"%s: no resource address\n", ecc_name);
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goto err_release_group;
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}
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edac_idx = edac_device_alloc_index();
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dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name,
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1, ecc_name, 1, 0, NULL, 0,
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edac_idx);
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if (!dci) {
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edac_printk(KERN_ERR, EDAC_DEVICE,
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"%s: Unable to allocate EDAC device\n", ecc_name);
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rc = -ENOMEM;
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goto err_release_group;
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}
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altdev = dci->pvt_info;
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dci->dev = edac->dev;
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altdev->edac_dev_name = ecc_name;
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altdev->edac_idx = edac_idx;
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altdev->edac = edac;
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altdev->edac_dev = dci;
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altdev->data = prv;
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altdev->ddev = *edac->dev;
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dci->dev = &altdev->ddev;
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dci->ctl_name = "Altera ECC Manager";
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dci->mod_name = ecc_name;
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dci->dev_name = ecc_name;
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altdev->base = devm_ioremap_resource(edac->dev, &res);
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if (IS_ERR(altdev->base)) {
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rc = PTR_ERR(altdev->base);
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goto err_release_group1;
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}
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/* Check specific dependencies for the module */
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if (altdev->data->setup) {
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rc = altdev->data->setup(altdev);
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if (rc)
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goto err_release_group1;
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}
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rc = edac_device_add_device(dci);
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if (rc) {
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dev_err(edac->dev, "edac_device_add_device failed\n");
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rc = -ENOMEM;
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goto err_release_group1;
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}
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altr_create_edacdev_dbgfs(dci, prv);
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list_add(&altdev->next, &edac->a10_ecc_devices);
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devres_remove_group(edac->dev, altr_edac_a10_device_add);
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return 0;
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err_release_group1:
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edac_device_free_ctl_info(dci);
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err_release_group:
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edac_printk(KERN_ALERT, EDAC_DEVICE, "%s: %d\n", __func__, __LINE__);
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devres_release_group(edac->dev, NULL);
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edac_printk(KERN_ERR, EDAC_DEVICE,
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"%s:Error setting up EDAC device: %d\n", ecc_name, rc);
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return rc;
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}
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static int altr_edac_a10_probe(struct platform_device *pdev)
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{
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struct altr_arria10_edac *edac;
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struct device_node *child;
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int rc;
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edac = devm_kzalloc(&pdev->dev, sizeof(*edac), GFP_KERNEL);
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if (!edac)
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return -ENOMEM;
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edac->dev = &pdev->dev;
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platform_set_drvdata(pdev, edac);
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INIT_LIST_HEAD(&edac->a10_ecc_devices);
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edac->ecc_mgr_map = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
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"altr,sysmgr-syscon");
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if (IS_ERR(edac->ecc_mgr_map)) {
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edac_printk(KERN_ERR, EDAC_DEVICE,
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"Unable to get syscon altr,sysmgr-syscon\n");
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return PTR_ERR(edac->ecc_mgr_map);
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}
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edac->sb_irq = platform_get_irq(pdev, 0);
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rc = devm_request_irq(&pdev->dev, edac->sb_irq,
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altr_edac_a10_irq_handler,
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IRQF_SHARED, dev_name(&pdev->dev), edac);
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if (rc) {
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edac_printk(KERN_ERR, EDAC_DEVICE, "No SBERR IRQ resource\n");
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return rc;
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}
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edac->db_irq = platform_get_irq(pdev, 1);
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rc = devm_request_irq(&pdev->dev, edac->db_irq,
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altr_edac_a10_irq_handler,
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IRQF_SHARED, dev_name(&pdev->dev), edac);
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if (rc) {
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edac_printk(KERN_ERR, EDAC_DEVICE, "No DBERR IRQ resource\n");
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return rc;
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}
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for_each_child_of_node(pdev->dev.of_node, child) {
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if (!of_device_is_available(child))
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continue;
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if (of_device_is_compatible(child, "altr,socfpga-a10-l2-ecc"))
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altr_edac_a10_device_add(edac, child);
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}
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return 0;
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}
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static const struct of_device_id altr_edac_a10_of_match[] = {
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{ .compatible = "altr,socfpga-a10-ecc-manager" },
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{},
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};
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MODULE_DEVICE_TABLE(of, altr_edac_a10_of_match);
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static struct platform_driver altr_edac_a10_driver = {
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.probe = altr_edac_a10_probe,
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.driver = {
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.name = "socfpga_a10_ecc_manager",
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.of_match_table = altr_edac_a10_of_match,
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},
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};
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module_platform_driver(altr_edac_a10_driver);
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MODULE_LICENSE("GPL v2");
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MODULE_AUTHOR("Thor Thayer");
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MODULE_DESCRIPTION("EDAC Driver for Altera Memories");
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@ -219,12 +219,39 @@ struct altr_sdram_mc_data {
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#define ALTR_L2_ECC_INJS BIT(1)
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#define ALTR_L2_ECC_INJD BIT(2)
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/* Arria10 General ECC Block Module Defines */
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#define A10_SYSMGR_ECC_INTSTAT_SERR_OFST 0x9C
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#define A10_SYSMGR_ECC_INTSTAT_DERR_OFST 0xA0
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#define A10_SYSMGR_ECC_INTSTAT_L2 BIT(0)
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#define A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST 0xA8
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#define A10_SYSGMR_MPU_CLEAR_L2_ECC_SB BIT(15)
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#define A10_SYSGMR_MPU_CLEAR_L2_ECC_MB BIT(31)
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/* Arria 10 L2 ECC Management Group Defines */
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#define ALTR_A10_L2_ECC_CTL_OFST 0x0
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#define ALTR_A10_L2_ECC_EN_CTL BIT(0)
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#define ALTR_A10_L2_ECC_STATUS 0xFFD060A4
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#define ALTR_A10_L2_ECC_STAT_OFST 0xA4
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#define ALTR_A10_L2_ECC_SERR_PEND BIT(0)
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#define ALTR_A10_L2_ECC_MERR_PEND BIT(0)
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#define ALTR_A10_L2_ECC_CLR_OFST 0x4
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#define ALTR_A10_L2_ECC_SERR_CLR BIT(15)
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#define ALTR_A10_L2_ECC_MERR_CLR BIT(31)
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#define ALTR_A10_L2_ECC_INJ_OFST ALTR_A10_L2_ECC_CTL_OFST
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#define ALTR_A10_L2_ECC_CE_INJ_MASK 0x00000101
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#define ALTR_A10_L2_ECC_UE_INJ_MASK 0x00010101
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struct altr_edac_device_dev;
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struct edac_device_prv_data {
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int (*setup)(struct altr_edac_device_dev *device);
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int ce_clear_mask;
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int ue_clear_mask;
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int irq_status_mask;
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char dbgfs_name[20];
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void * (*alloc_mem)(size_t size, void **other);
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void (*free_mem)(void *p, size_t size, void *other);
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@ -232,16 +259,31 @@ struct edac_device_prv_data {
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int ce_set_mask;
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int ue_set_mask;
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int set_err_ofst;
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irqreturn_t (*ecc_irq_handler)(struct altr_edac_device_dev *dci,
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bool sb);
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int trig_alloc_sz;
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};
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struct altr_edac_device_dev {
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struct list_head next;
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void __iomem *base;
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int sb_irq;
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int db_irq;
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const struct edac_device_prv_data *data;
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struct dentry *debugfs_dir;
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char *edac_dev_name;
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struct altr_arria10_edac *edac;
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struct edac_device_ctl_info *edac_dev;
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struct device ddev;
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int edac_idx;
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};
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struct altr_arria10_edac {
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struct device *dev;
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struct regmap *ecc_mgr_map;
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int sb_irq;
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int db_irq;
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struct list_head a10_ecc_devices;
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};
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#endif /* #ifndef _ALTERA_EDAC_H */
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