x86/mce/AMD, EDAC/mce_amd: Define and use tables for known SMCA IP types
Scalable MCA defines a number of IP types. An MCA bank on an SMCA system is defined as one of these IP types. A bank's type is uniquely identified by the combination of the HWID and MCATYPE values read from its MCA_IPID register. Add the required tables in order to be able to lookup error descriptions based on a bank's type and the error's extended error code. [ bp: Align comments, simplify a bit. ] Signed-off-by: Yazen Ghannam <Yazen.Ghannam@amd.com> Signed-off-by: Borislav Petkov <bp@suse.de> Link: http://lkml.kernel.org/r/1472741832-1690-1-git-send-email-Yazen.Ghannam@amd.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>hifive-unleashed-5.1
Yazen Ghannam
Thomas Gleixner
parent
856095b179
commit
5896820e0a
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@ -337,44 +337,47 @@ extern void apei_mce_report_mem_error(int corrected,
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* Scalable MCA.
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*/
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#ifdef CONFIG_X86_MCE_AMD
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enum amd_ip_types {
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SMCA_F17H_CORE = 0, /* Core errors */
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SMCA_DF, /* Data Fabric */
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SMCA_UMC, /* Unified Memory Controller */
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SMCA_PB, /* Parameter Block */
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SMCA_PSP, /* Platform Security Processor */
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SMCA_SMU, /* System Management Unit */
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N_AMD_IP_TYPES
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};
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struct amd_hwid {
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const char *name;
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unsigned int hwid;
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};
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extern struct amd_hwid amd_hwids[N_AMD_IP_TYPES];
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enum amd_core_mca_blocks {
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/* These may be used by multiple smca_hwid_mcatypes */
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enum smca_bank_types {
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SMCA_LS = 0, /* Load Store */
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SMCA_IF, /* Instruction Fetch */
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SMCA_L2_CACHE, /* L2 cache */
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SMCA_DE, /* Decoder unit */
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RES, /* Reserved */
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SMCA_EX, /* Execution unit */
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SMCA_L2_CACHE, /* L2 Cache */
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SMCA_DE, /* Decoder Unit */
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SMCA_EX, /* Execution Unit */
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SMCA_FP, /* Floating Point */
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SMCA_L3_CACHE, /* L3 cache */
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N_CORE_MCA_BLOCKS
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SMCA_L3_CACHE, /* L3 Cache */
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SMCA_CS, /* Coherent Slave */
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SMCA_PIE, /* Power, Interrupts, etc. */
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SMCA_UMC, /* Unified Memory Controller */
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SMCA_PB, /* Parameter Block */
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SMCA_PSP, /* Platform Security Processor */
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SMCA_SMU, /* System Management Unit */
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N_SMCA_BANK_TYPES
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};
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extern const char * const amd_core_mcablock_names[N_CORE_MCA_BLOCKS];
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enum amd_df_mca_blocks {
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SMCA_CS = 0, /* Coherent Slave */
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SMCA_PIE, /* Power management, Interrupts, etc */
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N_DF_BLOCKS
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struct smca_bank_name {
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const char *name; /* Short name for sysfs */
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const char *long_name; /* Long name for pretty-printing */
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};
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extern const char * const amd_df_mcablock_names[N_DF_BLOCKS];
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extern struct smca_bank_name smca_bank_names[N_SMCA_BANK_TYPES];
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#define HWID_MCATYPE(hwid, mcatype) ((hwid << 16) | mcatype)
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struct smca_hwid_mcatype {
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unsigned int bank_type; /* Use with smca_bank_types for easy indexing. */
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u32 hwid_mcatype; /* (hwid,mcatype) tuple */
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u32 xec_bitmap; /* Bitmap of valid ExtErrorCodes; current max is 21. */
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};
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struct smca_bank_info {
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struct smca_hwid_mcatype *type;
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u32 type_instance;
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};
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extern struct smca_bank_info smca_banks[MAX_NR_BANKS];
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#endif
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#endif /* _ASM_X86_MCE_H */
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@ -63,34 +63,55 @@ static const char * const th_names[] = {
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"execution_unit",
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};
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/* Define HWID to IP type mappings for Scalable MCA */
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struct amd_hwid amd_hwids[] = {
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[SMCA_F17H_CORE] = { "f17h_core", 0xB0 },
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[SMCA_DF] = { "data_fabric", 0x2E },
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[SMCA_UMC] = { "umc", 0x96 },
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[SMCA_PB] = { "param_block", 0x5 },
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[SMCA_PSP] = { "psp", 0xFF },
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[SMCA_SMU] = { "smu", 0x1 },
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struct smca_bank_name smca_bank_names[] = {
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[SMCA_LS] = { "load_store", "Load Store Unit" },
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[SMCA_IF] = { "insn_fetch", "Instruction Fetch Unit" },
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[SMCA_L2_CACHE] = { "l2_cache", "L2 Cache" },
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[SMCA_DE] = { "decode_unit", "Decode Unit" },
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[SMCA_EX] = { "execution_unit", "Execution Unit" },
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[SMCA_FP] = { "floating_point", "Floating Point Unit" },
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[SMCA_L3_CACHE] = { "l3_cache", "L3 Cache" },
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[SMCA_CS] = { "coherent_slave", "Coherent Slave" },
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[SMCA_PIE] = { "pie", "Power, Interrupts, etc." },
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[SMCA_UMC] = { "umc", "Unified Memory Controller" },
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[SMCA_PB] = { "param_block", "Parameter Block" },
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[SMCA_PSP] = { "psp", "Platform Security Processor" },
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[SMCA_SMU] = { "smu", "System Management Unit" },
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};
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EXPORT_SYMBOL_GPL(amd_hwids);
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EXPORT_SYMBOL_GPL(smca_bank_names);
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const char * const amd_core_mcablock_names[] = {
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[SMCA_LS] = "load_store",
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[SMCA_IF] = "insn_fetch",
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[SMCA_L2_CACHE] = "l2_cache",
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[SMCA_DE] = "decode_unit",
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[RES] = "",
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[SMCA_EX] = "execution_unit",
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[SMCA_FP] = "floating_point",
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[SMCA_L3_CACHE] = "l3_cache",
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};
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EXPORT_SYMBOL_GPL(amd_core_mcablock_names);
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static struct smca_hwid_mcatype smca_hwid_mcatypes[] = {
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/* { bank_type, hwid_mcatype, xec_bitmap } */
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const char * const amd_df_mcablock_names[] = {
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[SMCA_CS] = "coherent_slave",
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[SMCA_PIE] = "pie",
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/* ZN Core (HWID=0xB0) MCA types */
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{ SMCA_LS, HWID_MCATYPE(0xB0, 0x0), 0x1FFFEF },
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{ SMCA_IF, HWID_MCATYPE(0xB0, 0x1), 0x3FFF },
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{ SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2), 0xF },
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{ SMCA_DE, HWID_MCATYPE(0xB0, 0x3), 0x1FF },
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/* HWID 0xB0 MCATYPE 0x4 is Reserved */
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{ SMCA_EX, HWID_MCATYPE(0xB0, 0x5), 0x7FF },
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{ SMCA_FP, HWID_MCATYPE(0xB0, 0x6), 0x7F },
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{ SMCA_L3_CACHE, HWID_MCATYPE(0xB0, 0x7), 0xFF },
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/* Data Fabric MCA types */
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{ SMCA_CS, HWID_MCATYPE(0x2E, 0x0), 0x1FF },
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{ SMCA_PIE, HWID_MCATYPE(0x2E, 0x1), 0xF },
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/* Unified Memory Controller MCA type */
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{ SMCA_UMC, HWID_MCATYPE(0x96, 0x0), 0x3F },
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/* Parameter Block MCA type */
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{ SMCA_PB, HWID_MCATYPE(0x05, 0x0), 0x1 },
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/* Platform Security Processor MCA type */
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{ SMCA_PSP, HWID_MCATYPE(0xFF, 0x0), 0x1 },
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/* System Management Unit MCA type */
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{ SMCA_SMU, HWID_MCATYPE(0x01, 0x0), 0x1 },
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};
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EXPORT_SYMBOL_GPL(amd_df_mcablock_names);
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struct smca_bank_info smca_banks[MAX_NR_BANKS];
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EXPORT_SYMBOL_GPL(smca_banks);
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static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks);
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static DEFINE_PER_CPU(unsigned int, bank_map); /* see which banks are on */
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@ -108,6 +129,36 @@ void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt;
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* CPU Initialization
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*/
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static void get_smca_bank_info(unsigned int bank)
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{
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unsigned int i, hwid_mcatype, cpu = smp_processor_id();
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struct smca_hwid_mcatype *type;
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u32 high, instanceId;
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u16 hwid, mcatype;
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/* Collect bank_info using CPU 0 for now. */
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if (cpu)
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return;
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if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_IPID(bank), &instanceId, &high)) {
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pr_warn("Failed to read MCA_IPID for bank %d\n", bank);
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return;
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}
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hwid = high & MCI_IPID_HWID;
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mcatype = (high & MCI_IPID_MCATYPE) >> 16;
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hwid_mcatype = HWID_MCATYPE(hwid, mcatype);
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for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) {
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type = &smca_hwid_mcatypes[i];
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if (hwid_mcatype == type->hwid_mcatype) {
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smca_banks[bank].type = type;
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smca_banks[bank].type_instance = instanceId;
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break;
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}
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}
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}
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struct thresh_restart {
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struct threshold_block *b;
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int reset;
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@ -425,6 +476,9 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
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int offset = -1;
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for (bank = 0; bank < mca_cfg.banks; ++bank) {
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if (mce_flags.smca)
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get_smca_bank_info(bank);
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for (block = 0; block < NR_BLOCKS; ++block) {
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address = get_block_address(cpu, address, low, high, bank, block);
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if (!address)
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@ -283,6 +283,27 @@ static const char * const smca_smu_mce_desc[] = {
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"SMU RAM ECC or parity error",
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};
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struct smca_mce_desc {
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const char * const *descs;
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unsigned int num_descs;
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};
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static struct smca_mce_desc smca_mce_descs[] = {
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[SMCA_LS] = { smca_ls_mce_desc, ARRAY_SIZE(smca_ls_mce_desc) },
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[SMCA_IF] = { smca_if_mce_desc, ARRAY_SIZE(smca_if_mce_desc) },
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[SMCA_L2_CACHE] = { smca_l2_mce_desc, ARRAY_SIZE(smca_l2_mce_desc) },
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[SMCA_DE] = { smca_de_mce_desc, ARRAY_SIZE(smca_de_mce_desc) },
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[SMCA_EX] = { smca_ex_mce_desc, ARRAY_SIZE(smca_ex_mce_desc) },
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[SMCA_FP] = { smca_fp_mce_desc, ARRAY_SIZE(smca_fp_mce_desc) },
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[SMCA_L3_CACHE] = { smca_l3_mce_desc, ARRAY_SIZE(smca_l3_mce_desc) },
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[SMCA_CS] = { smca_cs_mce_desc, ARRAY_SIZE(smca_cs_mce_desc) },
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[SMCA_PIE] = { smca_pie_mce_desc, ARRAY_SIZE(smca_pie_mce_desc) },
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[SMCA_UMC] = { smca_umc_mce_desc, ARRAY_SIZE(smca_umc_mce_desc) },
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[SMCA_PB] = { smca_pb_mce_desc, ARRAY_SIZE(smca_pb_mce_desc) },
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[SMCA_PSP] = { smca_psp_mce_desc, ARRAY_SIZE(smca_psp_mce_desc) },
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[SMCA_SMU] = { smca_smu_mce_desc, ARRAY_SIZE(smca_smu_mce_desc) },
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};
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static bool f12h_mc0_mce(u16 ec, u8 xec)
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{
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bool ret = false;
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@ -827,175 +848,32 @@ static void decode_mc6_mce(struct mce *m)
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pr_emerg(HW_ERR "Corrupted MC6 MCE info?\n");
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}
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static void decode_f17h_core_errors(const char *ip_name, u8 xec,
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unsigned int mca_type)
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{
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const char * const *error_desc_array;
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size_t len;
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pr_emerg(HW_ERR "%s Error: ", ip_name);
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switch (mca_type) {
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case SMCA_LS:
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error_desc_array = smca_ls_mce_desc;
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len = ARRAY_SIZE(smca_ls_mce_desc) - 1;
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if (xec == 0x4) {
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pr_cont("Unrecognized LS MCA error code.\n");
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return;
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}
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break;
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case SMCA_IF:
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error_desc_array = smca_if_mce_desc;
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len = ARRAY_SIZE(smca_if_mce_desc) - 1;
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break;
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case SMCA_L2_CACHE:
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error_desc_array = smca_l2_mce_desc;
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len = ARRAY_SIZE(smca_l2_mce_desc) - 1;
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break;
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case SMCA_DE:
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error_desc_array = smca_de_mce_desc;
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len = ARRAY_SIZE(smca_de_mce_desc) - 1;
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break;
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case SMCA_EX:
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error_desc_array = smca_ex_mce_desc;
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len = ARRAY_SIZE(smca_ex_mce_desc) - 1;
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break;
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case SMCA_FP:
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error_desc_array = smca_fp_mce_desc;
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len = ARRAY_SIZE(smca_fp_mce_desc) - 1;
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break;
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case SMCA_L3_CACHE:
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error_desc_array = smca_l3_mce_desc;
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len = ARRAY_SIZE(smca_l3_mce_desc) - 1;
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break;
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default:
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pr_cont("Corrupted MCA core error info.\n");
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return;
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}
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if (xec > len) {
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pr_cont("Unrecognized %s MCA bank error code.\n",
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amd_core_mcablock_names[mca_type]);
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return;
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}
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pr_cont("%s.\n", error_desc_array[xec]);
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}
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static void decode_df_errors(u8 xec, unsigned int mca_type)
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{
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const char * const *error_desc_array;
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size_t len;
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pr_emerg(HW_ERR "Data Fabric Error: ");
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switch (mca_type) {
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case SMCA_CS:
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error_desc_array = smca_cs_mce_desc;
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len = ARRAY_SIZE(smca_cs_mce_desc) - 1;
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break;
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case SMCA_PIE:
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error_desc_array = smca_pie_mce_desc;
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len = ARRAY_SIZE(smca_pie_mce_desc) - 1;
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break;
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default:
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pr_cont("Corrupted MCA Data Fabric info.\n");
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return;
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}
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if (xec > len) {
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pr_cont("Unrecognized %s MCA bank error code.\n",
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amd_df_mcablock_names[mca_type]);
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return;
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}
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pr_cont("%s.\n", error_desc_array[xec]);
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}
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/* Decode errors according to Scalable MCA specification */
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static void decode_smca_errors(struct mce *m)
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{
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u32 addr = MSR_AMD64_SMCA_MCx_IPID(m->bank);
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unsigned int hwid, mca_type, i;
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u8 xec = XEC(m->status, xec_mask);
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const char * const *error_desc_array;
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struct smca_hwid_mcatype *type;
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unsigned int bank_type;
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const char *ip_name;
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u32 low, high;
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size_t len;
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u8 xec = XEC(m->status, xec_mask);
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if (rdmsr_safe(addr, &low, &high)) {
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pr_emerg(HW_ERR "Invalid IP block specified.\n");
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if (m->bank >= ARRAY_SIZE(smca_banks))
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return;
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}
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hwid = high & MCI_IPID_HWID;
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mca_type = (high & MCI_IPID_MCATYPE) >> 16;
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pr_emerg(HW_ERR "MC%d IPID value: 0x%08x%08x\n", m->bank, high, low);
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/*
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* Based on hwid and mca_type values, decode errors from respective IPs.
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* Note: mca_type values make sense only in the context of an hwid.
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*/
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for (i = 0; i < ARRAY_SIZE(amd_hwids); i++)
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if (amd_hwids[i].hwid == hwid)
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break;
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switch (i) {
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case SMCA_F17H_CORE:
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ip_name = (mca_type == SMCA_L3_CACHE) ?
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"L3 Cache" : "F17h Core";
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return decode_f17h_core_errors(ip_name, xec, mca_type);
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break;
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case SMCA_DF:
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return decode_df_errors(xec, mca_type);
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break;
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case SMCA_UMC:
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error_desc_array = smca_umc_mce_desc;
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len = ARRAY_SIZE(smca_umc_mce_desc) - 1;
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break;
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case SMCA_PB:
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error_desc_array = smca_pb_mce_desc;
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len = ARRAY_SIZE(smca_pb_mce_desc) - 1;
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break;
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case SMCA_PSP:
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error_desc_array = smca_psp_mce_desc;
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len = ARRAY_SIZE(smca_psp_mce_desc) - 1;
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break;
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case SMCA_SMU:
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error_desc_array = smca_smu_mce_desc;
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len = ARRAY_SIZE(smca_smu_mce_desc) - 1;
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break;
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default:
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pr_emerg(HW_ERR "HWID:%d does not match any existing IPs.\n", hwid);
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type = smca_banks[m->bank].type;
|
||||
if (!type)
|
||||
return;
|
||||
|
||||
bank_type = type->bank_type;
|
||||
ip_name = smca_bank_names[bank_type].long_name;
|
||||
|
||||
pr_emerg(HW_ERR "%s Extended Error Code: %d\n", ip_name, xec);
|
||||
|
||||
/* Only print the decode of valid error codes */
|
||||
if (xec < smca_mce_descs[bank_type].num_descs &&
|
||||
(type->xec_bitmap & BIT_ULL(xec))) {
|
||||
pr_emerg(HW_ERR "%s Error: ", ip_name);
|
||||
pr_cont("%s.\n", smca_mce_descs[bank_type].descs[xec]);
|
||||
}
|
||||
|
||||
ip_name = amd_hwids[i].name;
|
||||
pr_emerg(HW_ERR "%s Error: ", ip_name);
|
||||
|
||||
if (xec > len) {
|
||||
pr_cont("Unrecognized %s MCA bank error code.\n", ip_name);
|
||||
return;
|
||||
}
|
||||
|
||||
pr_cont("%s.\n", error_desc_array[xec]);
|
||||
}
|
||||
|
||||
static inline void amd_decode_err_code(u16 ec)
|
||||
|
|
|
|||
Loading…
Reference in New Issue