powerpc/64s: Move POWER machine check defines into mce_power.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>hifive-unleashed-5.1
Nicholas Piggin
Michael Ellerman
parent
88c6511a8c
commit
58c8d17f2e
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@ -24,97 +24,6 @@
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#include <linux/bitops.h>
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/*
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* Machine Check bits on power7 and power8
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*/
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#define P7_SRR1_MC_LOADSTORE(srr1) ((srr1) & PPC_BIT(42)) /* P8 too */
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/* SRR1 bits for machine check (On Power7 and Power8) */
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#define P7_SRR1_MC_IFETCH(srr1) ((srr1) & PPC_BITMASK(43, 45)) /* P8 too */
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#define P7_SRR1_MC_IFETCH_UE (0x1 << PPC_BITLSHIFT(45)) /* P8 too */
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#define P7_SRR1_MC_IFETCH_SLB_PARITY (0x2 << PPC_BITLSHIFT(45)) /* P8 too */
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#define P7_SRR1_MC_IFETCH_SLB_MULTIHIT (0x3 << PPC_BITLSHIFT(45)) /* P8 too */
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#define P7_SRR1_MC_IFETCH_SLB_BOTH (0x4 << PPC_BITLSHIFT(45))
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#define P7_SRR1_MC_IFETCH_TLB_MULTIHIT (0x5 << PPC_BITLSHIFT(45)) /* P8 too */
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#define P7_SRR1_MC_IFETCH_UE_TLB_RELOAD (0x6 << PPC_BITLSHIFT(45)) /* P8 too */
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#define P7_SRR1_MC_IFETCH_UE_IFU_INTERNAL (0x7 << PPC_BITLSHIFT(45))
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/* SRR1 bits for machine check (On Power8) */
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#define P8_SRR1_MC_IFETCH_ERAT_MULTIHIT (0x4 << PPC_BITLSHIFT(45))
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/* DSISR bits for machine check (On Power7 and Power8) */
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#define P7_DSISR_MC_UE (PPC_BIT(48)) /* P8 too */
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#define P7_DSISR_MC_UE_TABLEWALK (PPC_BIT(49)) /* P8 too */
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#define P7_DSISR_MC_ERAT_MULTIHIT (PPC_BIT(52)) /* P8 too */
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#define P7_DSISR_MC_TLB_MULTIHIT_MFTLB (PPC_BIT(53)) /* P8 too */
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#define P7_DSISR_MC_SLB_PARITY_MFSLB (PPC_BIT(55)) /* P8 too */
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#define P7_DSISR_MC_SLB_MULTIHIT (PPC_BIT(56)) /* P8 too */
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#define P7_DSISR_MC_SLB_MULTIHIT_PARITY (PPC_BIT(57)) /* P8 too */
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/*
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* DSISR bits for machine check (Power8) in addition to above.
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* Secondary DERAT Multihit
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*/
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#define P8_DSISR_MC_ERAT_MULTIHIT_SEC (PPC_BIT(54))
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/* SLB error bits */
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#define P7_DSISR_MC_SLB_ERRORS (P7_DSISR_MC_ERAT_MULTIHIT | \
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P7_DSISR_MC_SLB_PARITY_MFSLB | \
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P7_DSISR_MC_SLB_MULTIHIT | \
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P7_DSISR_MC_SLB_MULTIHIT_PARITY)
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#define P8_DSISR_MC_SLB_ERRORS (P7_DSISR_MC_SLB_ERRORS | \
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P8_DSISR_MC_ERAT_MULTIHIT_SEC)
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/*
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* Machine Check bits on power9
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*/
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#define P9_SRR1_MC_LOADSTORE(srr1) (((srr1) >> PPC_BITLSHIFT(42)) & 1)
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#define P9_SRR1_MC_IFETCH(srr1) ( \
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PPC_BITEXTRACT(srr1, 45, 0) | \
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PPC_BITEXTRACT(srr1, 44, 1) | \
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PPC_BITEXTRACT(srr1, 43, 2) | \
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PPC_BITEXTRACT(srr1, 36, 3) )
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/* 0 is reserved */
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#define P9_SRR1_MC_IFETCH_UE 1
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#define P9_SRR1_MC_IFETCH_SLB_PARITY 2
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#define P9_SRR1_MC_IFETCH_SLB_MULTIHIT 3
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#define P9_SRR1_MC_IFETCH_ERAT_MULTIHIT 4
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#define P9_SRR1_MC_IFETCH_TLB_MULTIHIT 5
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#define P9_SRR1_MC_IFETCH_UE_TLB_RELOAD 6
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/* 7 is reserved */
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#define P9_SRR1_MC_IFETCH_LINK_TIMEOUT 8
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#define P9_SRR1_MC_IFETCH_LINK_TABLEWALK_TIMEOUT 9
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/* 10 ? */
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#define P9_SRR1_MC_IFETCH_RA 11
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#define P9_SRR1_MC_IFETCH_RA_TABLEWALK 12
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#define P9_SRR1_MC_IFETCH_RA_ASYNC_STORE 13
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#define P9_SRR1_MC_IFETCH_LINK_ASYNC_STORE_TIMEOUT 14
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#define P9_SRR1_MC_IFETCH_RA_TABLEWALK_FOREIGN 15
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/* DSISR bits for machine check (On Power9) */
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#define P9_DSISR_MC_UE (PPC_BIT(48))
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#define P9_DSISR_MC_UE_TABLEWALK (PPC_BIT(49))
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#define P9_DSISR_MC_LINK_LOAD_TIMEOUT (PPC_BIT(50))
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#define P9_DSISR_MC_LINK_TABLEWALK_TIMEOUT (PPC_BIT(51))
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#define P9_DSISR_MC_ERAT_MULTIHIT (PPC_BIT(52))
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#define P9_DSISR_MC_TLB_MULTIHIT_MFTLB (PPC_BIT(53))
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#define P9_DSISR_MC_USER_TLBIE (PPC_BIT(54))
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#define P9_DSISR_MC_SLB_PARITY_MFSLB (PPC_BIT(55))
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#define P9_DSISR_MC_SLB_MULTIHIT_MFSLB (PPC_BIT(56))
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#define P9_DSISR_MC_RA_LOAD (PPC_BIT(57))
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#define P9_DSISR_MC_RA_TABLEWALK (PPC_BIT(58))
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#define P9_DSISR_MC_RA_TABLEWALK_FOREIGN (PPC_BIT(59))
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#define P9_DSISR_MC_RA_FOREIGN (PPC_BIT(60))
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/* SLB error bits */
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#define P9_DSISR_MC_SLB_ERRORS (P9_DSISR_MC_ERAT_MULTIHIT | \
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P9_DSISR_MC_SLB_PARITY_MFSLB | \
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P9_DSISR_MC_SLB_MULTIHIT_MFSLB)
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enum MCE_Version {
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MCE_V1 = 1,
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};
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@ -161,6 +161,98 @@ static int mce_handle_flush_derrors(uint64_t dsisr, uint64_t slb, uint64_t tlb,
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return 1;
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}
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/*
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* Machine Check bits on power7 and power8
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*/
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#define P7_SRR1_MC_LOADSTORE(srr1) ((srr1) & PPC_BIT(42)) /* P8 too */
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/* SRR1 bits for machine check (On Power7 and Power8) */
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#define P7_SRR1_MC_IFETCH(srr1) ((srr1) & PPC_BITMASK(43, 45)) /* P8 too */
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#define P7_SRR1_MC_IFETCH_UE (0x1 << PPC_BITLSHIFT(45)) /* P8 too */
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#define P7_SRR1_MC_IFETCH_SLB_PARITY (0x2 << PPC_BITLSHIFT(45)) /* P8 too */
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#define P7_SRR1_MC_IFETCH_SLB_MULTIHIT (0x3 << PPC_BITLSHIFT(45)) /* P8 too */
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#define P7_SRR1_MC_IFETCH_SLB_BOTH (0x4 << PPC_BITLSHIFT(45))
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#define P7_SRR1_MC_IFETCH_TLB_MULTIHIT (0x5 << PPC_BITLSHIFT(45)) /* P8 too */
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#define P7_SRR1_MC_IFETCH_UE_TLB_RELOAD (0x6 << PPC_BITLSHIFT(45)) /* P8 too */
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#define P7_SRR1_MC_IFETCH_UE_IFU_INTERNAL (0x7 << PPC_BITLSHIFT(45))
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/* SRR1 bits for machine check (On Power8) */
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#define P8_SRR1_MC_IFETCH_ERAT_MULTIHIT (0x4 << PPC_BITLSHIFT(45))
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/* DSISR bits for machine check (On Power7 and Power8) */
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#define P7_DSISR_MC_UE (PPC_BIT(48)) /* P8 too */
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#define P7_DSISR_MC_UE_TABLEWALK (PPC_BIT(49)) /* P8 too */
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#define P7_DSISR_MC_ERAT_MULTIHIT (PPC_BIT(52)) /* P8 too */
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#define P7_DSISR_MC_TLB_MULTIHIT_MFTLB (PPC_BIT(53)) /* P8 too */
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#define P7_DSISR_MC_SLB_PARITY_MFSLB (PPC_BIT(55)) /* P8 too */
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#define P7_DSISR_MC_SLB_MULTIHIT (PPC_BIT(56)) /* P8 too */
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#define P7_DSISR_MC_SLB_MULTIHIT_PARITY (PPC_BIT(57)) /* P8 too */
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/*
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* DSISR bits for machine check (Power8) in addition to above.
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* Secondary DERAT Multihit
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*/
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#define P8_DSISR_MC_ERAT_MULTIHIT_SEC (PPC_BIT(54))
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/* SLB error bits */
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#define P7_DSISR_MC_SLB_ERRORS (P7_DSISR_MC_ERAT_MULTIHIT | \
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P7_DSISR_MC_SLB_PARITY_MFSLB | \
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P7_DSISR_MC_SLB_MULTIHIT | \
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P7_DSISR_MC_SLB_MULTIHIT_PARITY)
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#define P8_DSISR_MC_SLB_ERRORS (P7_DSISR_MC_SLB_ERRORS | \
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P8_DSISR_MC_ERAT_MULTIHIT_SEC)
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/*
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* Machine Check bits on power9
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*/
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#define P9_SRR1_MC_LOADSTORE(srr1) (((srr1) >> PPC_BITLSHIFT(42)) & 1)
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#define P9_SRR1_MC_IFETCH(srr1) ( \
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PPC_BITEXTRACT(srr1, 45, 0) | \
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PPC_BITEXTRACT(srr1, 44, 1) | \
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PPC_BITEXTRACT(srr1, 43, 2) | \
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PPC_BITEXTRACT(srr1, 36, 3) )
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/* 0 is reserved */
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#define P9_SRR1_MC_IFETCH_UE 1
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#define P9_SRR1_MC_IFETCH_SLB_PARITY 2
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#define P9_SRR1_MC_IFETCH_SLB_MULTIHIT 3
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#define P9_SRR1_MC_IFETCH_ERAT_MULTIHIT 4
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#define P9_SRR1_MC_IFETCH_TLB_MULTIHIT 5
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#define P9_SRR1_MC_IFETCH_UE_TLB_RELOAD 6
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/* 7 is reserved */
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#define P9_SRR1_MC_IFETCH_LINK_TIMEOUT 8
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#define P9_SRR1_MC_IFETCH_LINK_TABLEWALK_TIMEOUT 9
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/* 10 ? */
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#define P9_SRR1_MC_IFETCH_RA 11
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#define P9_SRR1_MC_IFETCH_RA_TABLEWALK 12
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#define P9_SRR1_MC_IFETCH_RA_ASYNC_STORE 13
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#define P9_SRR1_MC_IFETCH_LINK_ASYNC_STORE_TIMEOUT 14
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#define P9_SRR1_MC_IFETCH_RA_TABLEWALK_FOREIGN 15
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/* DSISR bits for machine check (On Power9) */
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#define P9_DSISR_MC_UE (PPC_BIT(48))
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#define P9_DSISR_MC_UE_TABLEWALK (PPC_BIT(49))
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#define P9_DSISR_MC_LINK_LOAD_TIMEOUT (PPC_BIT(50))
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#define P9_DSISR_MC_LINK_TABLEWALK_TIMEOUT (PPC_BIT(51))
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#define P9_DSISR_MC_ERAT_MULTIHIT (PPC_BIT(52))
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#define P9_DSISR_MC_TLB_MULTIHIT_MFTLB (PPC_BIT(53))
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#define P9_DSISR_MC_USER_TLBIE (PPC_BIT(54))
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#define P9_DSISR_MC_SLB_PARITY_MFSLB (PPC_BIT(55))
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#define P9_DSISR_MC_SLB_MULTIHIT_MFSLB (PPC_BIT(56))
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#define P9_DSISR_MC_RA_LOAD (PPC_BIT(57))
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#define P9_DSISR_MC_RA_TABLEWALK (PPC_BIT(58))
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#define P9_DSISR_MC_RA_TABLEWALK_FOREIGN (PPC_BIT(59))
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#define P9_DSISR_MC_RA_FOREIGN (PPC_BIT(60))
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/* SLB error bits */
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#define P9_DSISR_MC_SLB_ERRORS (P9_DSISR_MC_ERAT_MULTIHIT | \
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P9_DSISR_MC_SLB_PARITY_MFSLB | \
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P9_DSISR_MC_SLB_MULTIHIT_MFSLB)
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static long mce_handle_derror_p7(uint64_t dsisr)
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{
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return mce_handle_flush_derrors(dsisr,
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