MIPS: BCM63XX: use a switch for external irq config
Makes the code a bit more readable and easier to add support for new chips. Signed-off-by: Maxime Bizon <mbizon@freebox.fr> Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4093/ Signed-off-by: John Crispin <blogic@openwrt.org>
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@ -438,7 +438,8 @@ static int bcm63xx_external_irq_set_type(struct irq_data *d,
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reg = bcm_perf_readl(regaddr);
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irq %= 4;
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if (BCMCPU_IS_6348()) {
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switch (bcm63xx_get_cpu_id()) {
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case BCM6348_CPU_ID:
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if (levelsense)
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reg |= EXTIRQ_CFG_LEVELSENSE_6348(irq);
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else
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@ -451,9 +452,13 @@ static int bcm63xx_external_irq_set_type(struct irq_data *d,
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reg |= EXTIRQ_CFG_BOTHEDGE_6348(irq);
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else
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reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq);
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}
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break;
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if (BCMCPU_IS_6338() || BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
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case BCM6328_CPU_ID:
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case BCM6338_CPU_ID:
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case BCM6345_CPU_ID:
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case BCM6358_CPU_ID:
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case BCM6368_CPU_ID:
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if (levelsense)
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reg |= EXTIRQ_CFG_LEVELSENSE(irq);
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else
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@ -466,6 +471,9 @@ static int bcm63xx_external_irq_set_type(struct irq_data *d,
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reg |= EXTIRQ_CFG_BOTHEDGE(irq);
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else
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reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
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break;
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default:
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BUG();
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}
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bcm_perf_writel(reg, regaddr);
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