drm/nouveau/fb/ramnva3: Reclocking script for GDDR3
Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>hifive-unleashed-5.1
Roy Spliet
Ben Skeggs
parent
b0c7336b1a
commit
598a39e79a
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@ -33,6 +33,8 @@
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#include <subdev/clock/nva3.h>
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#include <subdev/clock/pll.h>
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#include <subdev/gpio.h>
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#include <subdev/timer.h>
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#include <engine/fifo.h>
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@ -43,6 +45,9 @@
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#include "nv50.h"
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/* XXX: Remove when memx gains GPIO support */
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extern int nv50_gpio_location(int line, u32 *reg, u32 *shift);
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struct nva3_ramfuc {
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struct ramfuc base;
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struct ramfuc_reg r_0x001610;
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@ -81,6 +86,7 @@ struct nva3_ramfuc {
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struct ramfuc_reg r_0x111400;
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struct ramfuc_reg r_0x611200;
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struct ramfuc_reg r_mr[4];
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struct ramfuc_reg r_gpioFBVREF;
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};
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struct nva3_ltrain {
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@ -357,15 +363,22 @@ nva3_ram_timing_calc(struct nouveau_fb *pfb, u32 *timing)
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struct nva3_ram *ram = (void *)pfb->ram;
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struct nvbios_ramcfg *cfg = &ram->base.target.bios;
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int tUNK_base, tUNK_40_0, prevCL;
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u32 cur3, cur7, cur8;
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u32 cur2, cur3, cur7, cur8;
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cur2 = nv_rd32(pfb, 0x100228);
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cur3 = nv_rd32(pfb, 0x10022c);
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cur7 = nv_rd32(pfb, 0x10023c);
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cur8 = nv_rd32(pfb, 0x100240);
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if (T(CWL) == 0)
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/* Observed on DDR2 */
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switch ((!T(CWL)) * ram->base.type) {
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case NV_MEM_TYPE_DDR2:
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T(CWL) = T(CL) - 1;
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break;
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case NV_MEM_TYPE_GDDR3:
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T(CWL) = ((cur2 & 0xff000000) >> 24) + 1;
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break;
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}
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prevCL = (cur3 & 0x000000ff) + 1;
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tUNK_base = ((cur7 & 0x00ff0000) >> 16) - prevCL;
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@ -389,10 +402,10 @@ nva3_ram_timing_calc(struct nouveau_fb *pfb, u32 *timing)
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T(13);
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timing[5] = T(RFC) << 24 |
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max_t(u8,T(RCDRD), T(RCDWR)) << 16 |
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(T(CWL) + 6) << 8 |
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max_t(u8, (T(CWL) + 6), (T(CL) + 2)) << 8 |
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T(RP);
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timing[6] = (0x5a + T(CL)) << 16 |
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(6 - T(CL) + T(CWL)) << 8 |
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max_t(u8, 1, (6 - T(CL) + T(CWL))) << 8 |
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(0x50 + T(CL) - T(CWL));
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timing[7] = (cur7 & 0xff000000) |
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((tUNK_base + T(CL)) << 16) |
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@ -401,6 +414,7 @@ nva3_ram_timing_calc(struct nouveau_fb *pfb, u32 *timing)
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switch (ram->base.type) {
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case NV_MEM_TYPE_DDR2:
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case NV_MEM_TYPE_GDDR3:
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tUNK_40_0 = prevCL - (cur8 & 0xff);
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if (tUNK_40_0 > 0)
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timing[8] |= T(CL);
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@ -439,6 +453,17 @@ nouveau_sddr3_dll_disable(struct nva3_ramfuc *fuc, u32 *mr)
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}
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}
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static void
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nouveau_gddr3_dll_disable(struct nva3_ramfuc *fuc, u32 *mr)
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{
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u32 mr1_old = ram_rd32(fuc, mr[1]);
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if (!(mr1_old & 0x40)) {
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ram_wr32(fuc, mr[1], mr[1]);
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ram_nsec(fuc, 1000);
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}
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}
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static void
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nva3_ram_lock_pll(struct nva3_ramfuc *fuc, struct nva3_clock_info *mclk)
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{
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@ -449,6 +474,29 @@ nva3_ram_lock_pll(struct nva3_ramfuc *fuc, struct nva3_clock_info *mclk)
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ram_mask(fuc, 0x004000, 0x00000010, 0x00000010);
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}
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static void
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nva3_ram_fbvref(struct nva3_ramfuc *fuc, u32 val)
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{
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struct nouveau_gpio *gpio = nouveau_gpio(fuc->base.pfb);
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struct dcb_gpio_func func;
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u32 reg, sh, gpio_val;
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int ret;
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if (gpio->get(gpio, 0, 0x2e, DCB_GPIO_UNUSED) != val) {
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ret = gpio->find(gpio, 0, 0x2e, DCB_GPIO_UNUSED, &func);
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if (ret)
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return;
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nv50_gpio_location(func.line, ®, &sh);
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gpio_val = ram_rd32(fuc, gpioFBVREF);
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if (gpio_val & (8 << sh))
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val = !val;
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ram_mask(fuc, gpioFBVREF, (0x3 << sh), ((val | 0x2) << sh));
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ram_nsec(fuc, 20000);
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}
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}
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static int
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nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
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{
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@ -531,6 +579,9 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
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case NV_MEM_TYPE_DDR3:
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ret = nouveau_sddr3_calc(&ram->base);
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break;
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case NV_MEM_TYPE_GDDR3:
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ret = nouveau_gddr3_calc(&ram->base);
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break;
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default:
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ret = -ENOSYS;
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break;
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@ -582,17 +633,26 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
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ram_block(fuc);
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ram_nsec(fuc, 2000);
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if (!next->bios.ramcfg_10_02_10)
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ram_mask(fuc, 0x111100, 0x04020000, 0x04020000); /*XXX*/
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if (!next->bios.ramcfg_10_02_10) {
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if (ram->base.type == NV_MEM_TYPE_GDDR3)
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ram_mask(fuc, 0x111100, 0x04020000, 0x00020000);
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else
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ram_mask(fuc, 0x111100, 0x04020000, 0x04020000);
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}
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/* If we're disabling the DLL, do it now */
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switch (next->bios.ramcfg_10_DLLoff * ram->base.type) {
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case NV_MEM_TYPE_DDR3:
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nouveau_sddr3_dll_disable(fuc, ram->base.mr);
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break;
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case NV_MEM_TYPE_GDDR3:
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nouveau_gddr3_dll_disable(fuc, ram->base.mr);
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break;
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}
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if (fuc->r_gpioFBVREF.addr && next->bios.timing_10_ODT)
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nva3_ram_fbvref(fuc, 0);
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/* Brace RAM for impact */
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ram_wr32(fuc, 0x1002d4, 0x00000001);
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ram_wr32(fuc, 0x1002d0, 0x00000001);
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@ -728,6 +788,10 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
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}
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unk714 |= 0x00000010;
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break;
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case NV_MEM_TYPE_GDDR3:
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r111100 |= 0x30000000;
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unk714 |= 0x00000020;
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break;
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default:
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break;
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}
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@ -753,11 +817,18 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
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ram_mask(fuc, 0x100718, 0xffffffff, unk718);
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ram_mask(fuc, 0x111100, 0xffffffff, r111100);
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if (fuc->r_gpioFBVREF.addr && !next->bios.timing_10_ODT)
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nva3_ram_fbvref(fuc, 1);
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/* Reset DLL */
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if (!next->bios.ramcfg_10_DLLoff)
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nouveau_sddr2_dll_reset(fuc);
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ram_nsec(fuc, 14000);
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if (ram->base.type == NV_MEM_TYPE_GDDR3) {
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ram_nsec(fuc, 31000);
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} else {
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ram_nsec(fuc, 14000);
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}
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if (ram->base.type == NV_MEM_TYPE_DDR3) {
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ram_wr32(fuc, 0x100264, 0x1);
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@ -859,8 +930,12 @@ nva3_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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struct nouveau_oclass *oclass, void *data, u32 datasize,
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struct nouveau_object **pobject)
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{
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struct nouveau_fb *pfb = nouveau_fb(parent);
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struct nouveau_gpio *gpio = nouveau_gpio(pfb);
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struct dcb_gpio_func func;
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struct nva3_ram *ram;
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int ret, i;
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u32 reg, shift;
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ret = nv50_ram_create(parent, engine, oclass, &ram);
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*pobject = nv_object(ram);
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@ -870,6 +945,7 @@ nva3_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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switch (ram->base.type) {
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case NV_MEM_TYPE_DDR2:
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case NV_MEM_TYPE_DDR3:
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case NV_MEM_TYPE_GDDR3:
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ram->base.calc = nva3_ram_calc;
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ram->base.prog = nva3_ram_prog;
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ram->base.tidy = nva3_ram_tidy;
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@ -928,6 +1004,12 @@ nva3_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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ram->fuc.r_mr[3] = ramfuc_reg(0x1002e4);
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}
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ret = gpio->find(gpio, 0, 0x2e, DCB_GPIO_UNUSED, &func);
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if (ret == 0) {
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nv50_gpio_location(func.line, ®, &shift);
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ram->fuc.r_gpioFBVREF = ramfuc_reg(reg);
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}
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return 0;
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}
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@ -54,7 +54,7 @@ nv50_gpio_reset(struct nouveau_gpio *gpio, u8 match)
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}
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}
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static int
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int
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nv50_gpio_location(int line, u32 *reg, u32 *shift)
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{
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const u32 nv50_gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 };
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