crypto: qce - allow building only hashes/ciphers
Allow the user to choose whether to build support for all algorithms (default), hashes-only, or skciphers-only. The QCE engine does not appear to scale as well as the CPU to handle multiple crypto requests. While the ipq40xx chips have 4-core CPUs, the QCE handles only 2 requests in parallel. Ipsec throughput seems to improve when disabling either family of algorithms, sharing the load with the CPU. Enabling skciphers-only appears to work best. Signed-off-by: Eneas U de Queiroz <cotequeiroz@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Eneas U de Queiroz
Herbert Xu
parent
8ceda88320
commit
59e056cda4
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@ -618,6 +618,14 @@ config CRYPTO_DEV_QCE
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tristate "Qualcomm crypto engine accelerator"
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depends on ARCH_QCOM || COMPILE_TEST
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depends on HAS_IOMEM
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help
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This driver supports Qualcomm crypto engine accelerator
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hardware. To compile this driver as a module, choose M here. The
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module will be called qcrypto.
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config CRYPTO_DEV_QCE_SKCIPHER
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bool
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depends on CRYPTO_DEV_QCE
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select CRYPTO_AES
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select CRYPTO_LIB_DES
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select CRYPTO_ECB
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@ -625,10 +633,57 @@ config CRYPTO_DEV_QCE
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select CRYPTO_XTS
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select CRYPTO_CTR
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select CRYPTO_SKCIPHER
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config CRYPTO_DEV_QCE_SHA
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bool
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depends on CRYPTO_DEV_QCE
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choice
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prompt "Algorithms enabled for QCE acceleration"
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default CRYPTO_DEV_QCE_ENABLE_ALL
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depends on CRYPTO_DEV_QCE
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help
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This driver supports Qualcomm crypto engine accelerator
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hardware. To compile this driver as a module, choose M here. The
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module will be called qcrypto.
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This option allows to choose whether to build support for all algorihtms
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(default), hashes-only, or skciphers-only.
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The QCE engine does not appear to scale as well as the CPU to handle
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multiple crypto requests. While the ipq40xx chips have 4-core CPUs, the
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QCE handles only 2 requests in parallel.
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Ipsec throughput seems to improve when disabling either family of
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algorithms, sharing the load with the CPU. Enabling skciphers-only
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appears to work best.
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config CRYPTO_DEV_QCE_ENABLE_ALL
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bool "All supported algorithms"
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select CRYPTO_DEV_QCE_SKCIPHER
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select CRYPTO_DEV_QCE_SHA
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help
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Enable all supported algorithms:
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- AES (CBC, CTR, ECB, XTS)
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- 3DES (CBC, ECB)
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- DES (CBC, ECB)
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- SHA1, HMAC-SHA1
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- SHA256, HMAC-SHA256
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config CRYPTO_DEV_QCE_ENABLE_SKCIPHER
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bool "Symmetric-key ciphers only"
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select CRYPTO_DEV_QCE_SKCIPHER
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help
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Enable symmetric-key ciphers only:
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- AES (CBC, CTR, ECB, XTS)
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- 3DES (ECB, CBC)
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- DES (ECB, CBC)
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config CRYPTO_DEV_QCE_ENABLE_SHA
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bool "Hash/HMAC only"
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select CRYPTO_DEV_QCE_SHA
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help
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Enable hashes/HMAC algorithms only:
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- SHA1, HMAC-SHA1
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- SHA256, HMAC-SHA256
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endchoice
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config CRYPTO_DEV_QCOM_RNG
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tristate "Qualcomm Random Number Generator Driver"
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@ -2,6 +2,7 @@
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obj-$(CONFIG_CRYPTO_DEV_QCE) += qcrypto.o
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qcrypto-objs := core.o \
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common.o \
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dma.o \
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sha.o \
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skcipher.o
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dma.o
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qcrypto-$(CONFIG_CRYPTO_DEV_QCE_SHA) += sha.o
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qcrypto-$(CONFIG_CRYPTO_DEV_QCE_SKCIPHER) += skcipher.o
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@ -45,52 +45,56 @@ qce_clear_array(struct qce_device *qce, u32 offset, unsigned int len)
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qce_write(qce, offset + i * sizeof(u32), 0);
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}
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static u32 qce_encr_cfg(unsigned long flags, u32 aes_key_size)
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static u32 qce_config_reg(struct qce_device *qce, int little)
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{
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u32 cfg = 0;
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u32 beats = (qce->burst_size >> 3) - 1;
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u32 pipe_pair = qce->pipe_pair_id;
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u32 config;
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if (IS_AES(flags)) {
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if (aes_key_size == AES_KEYSIZE_128)
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cfg |= ENCR_KEY_SZ_AES128 << ENCR_KEY_SZ_SHIFT;
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else if (aes_key_size == AES_KEYSIZE_256)
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cfg |= ENCR_KEY_SZ_AES256 << ENCR_KEY_SZ_SHIFT;
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}
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config = (beats << REQ_SIZE_SHIFT) & REQ_SIZE_MASK;
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config |= BIT(MASK_DOUT_INTR_SHIFT) | BIT(MASK_DIN_INTR_SHIFT) |
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BIT(MASK_OP_DONE_INTR_SHIFT) | BIT(MASK_ERR_INTR_SHIFT);
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config |= (pipe_pair << PIPE_SET_SELECT_SHIFT) & PIPE_SET_SELECT_MASK;
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config &= ~HIGH_SPD_EN_N_SHIFT;
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if (IS_AES(flags))
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cfg |= ENCR_ALG_AES << ENCR_ALG_SHIFT;
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else if (IS_DES(flags) || IS_3DES(flags))
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cfg |= ENCR_ALG_DES << ENCR_ALG_SHIFT;
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if (little)
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config |= BIT(LITTLE_ENDIAN_MODE_SHIFT);
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if (IS_DES(flags))
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cfg |= ENCR_KEY_SZ_DES << ENCR_KEY_SZ_SHIFT;
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if (IS_3DES(flags))
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cfg |= ENCR_KEY_SZ_3DES << ENCR_KEY_SZ_SHIFT;
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switch (flags & QCE_MODE_MASK) {
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case QCE_MODE_ECB:
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cfg |= ENCR_MODE_ECB << ENCR_MODE_SHIFT;
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break;
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case QCE_MODE_CBC:
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cfg |= ENCR_MODE_CBC << ENCR_MODE_SHIFT;
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break;
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case QCE_MODE_CTR:
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cfg |= ENCR_MODE_CTR << ENCR_MODE_SHIFT;
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break;
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case QCE_MODE_XTS:
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cfg |= ENCR_MODE_XTS << ENCR_MODE_SHIFT;
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break;
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case QCE_MODE_CCM:
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cfg |= ENCR_MODE_CCM << ENCR_MODE_SHIFT;
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cfg |= LAST_CCM_XFR << LAST_CCM_SHIFT;
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break;
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default:
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return ~0;
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}
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return cfg;
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return config;
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}
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void qce_cpu_to_be32p_array(__be32 *dst, const u8 *src, unsigned int len)
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{
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__be32 *d = dst;
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const u8 *s = src;
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unsigned int n;
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n = len / sizeof(u32);
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for (; n > 0; n--) {
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*d = cpu_to_be32p((const __u32 *) s);
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s += sizeof(__u32);
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d++;
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}
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}
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static void qce_setup_config(struct qce_device *qce)
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{
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u32 config;
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/* get big endianness */
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config = qce_config_reg(qce, 0);
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/* clear status */
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qce_write(qce, REG_STATUS, 0);
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qce_write(qce, REG_CONFIG, config);
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}
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static inline void qce_crypto_go(struct qce_device *qce)
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{
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qce_write(qce, REG_GOPROC, BIT(GO_SHIFT) | BIT(RESULTS_DUMP_SHIFT));
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}
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#ifdef CONFIG_CRYPTO_DEV_QCE_SHA
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static u32 qce_auth_cfg(unsigned long flags, u32 key_size)
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{
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u32 cfg = 0;
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@ -137,88 +141,6 @@ static u32 qce_auth_cfg(unsigned long flags, u32 key_size)
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return cfg;
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}
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static u32 qce_config_reg(struct qce_device *qce, int little)
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{
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u32 beats = (qce->burst_size >> 3) - 1;
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u32 pipe_pair = qce->pipe_pair_id;
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u32 config;
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config = (beats << REQ_SIZE_SHIFT) & REQ_SIZE_MASK;
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config |= BIT(MASK_DOUT_INTR_SHIFT) | BIT(MASK_DIN_INTR_SHIFT) |
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BIT(MASK_OP_DONE_INTR_SHIFT) | BIT(MASK_ERR_INTR_SHIFT);
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config |= (pipe_pair << PIPE_SET_SELECT_SHIFT) & PIPE_SET_SELECT_MASK;
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config &= ~HIGH_SPD_EN_N_SHIFT;
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if (little)
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config |= BIT(LITTLE_ENDIAN_MODE_SHIFT);
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return config;
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}
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void qce_cpu_to_be32p_array(__be32 *dst, const u8 *src, unsigned int len)
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{
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__be32 *d = dst;
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const u8 *s = src;
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unsigned int n;
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n = len / sizeof(u32);
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for (; n > 0; n--) {
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*d = cpu_to_be32p((const __u32 *) s);
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s += sizeof(__u32);
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d++;
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}
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}
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static void qce_xts_swapiv(__be32 *dst, const u8 *src, unsigned int ivsize)
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{
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u8 swap[QCE_AES_IV_LENGTH];
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u32 i, j;
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if (ivsize > QCE_AES_IV_LENGTH)
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return;
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memset(swap, 0, QCE_AES_IV_LENGTH);
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for (i = (QCE_AES_IV_LENGTH - ivsize), j = ivsize - 1;
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i < QCE_AES_IV_LENGTH; i++, j--)
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swap[i] = src[j];
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qce_cpu_to_be32p_array(dst, swap, QCE_AES_IV_LENGTH);
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}
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static void qce_xtskey(struct qce_device *qce, const u8 *enckey,
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unsigned int enckeylen, unsigned int cryptlen)
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{
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u32 xtskey[QCE_MAX_CIPHER_KEY_SIZE / sizeof(u32)] = {0};
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unsigned int xtsklen = enckeylen / (2 * sizeof(u32));
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unsigned int xtsdusize;
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qce_cpu_to_be32p_array((__be32 *)xtskey, enckey + enckeylen / 2,
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enckeylen / 2);
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qce_write_array(qce, REG_ENCR_XTS_KEY0, xtskey, xtsklen);
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/* xts du size 512B */
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xtsdusize = min_t(u32, QCE_SECTOR_SIZE, cryptlen);
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qce_write(qce, REG_ENCR_XTS_DU_SIZE, xtsdusize);
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}
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static void qce_setup_config(struct qce_device *qce)
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{
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u32 config;
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/* get big endianness */
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config = qce_config_reg(qce, 0);
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/* clear status */
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qce_write(qce, REG_STATUS, 0);
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qce_write(qce, REG_CONFIG, config);
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}
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static inline void qce_crypto_go(struct qce_device *qce)
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{
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qce_write(qce, REG_GOPROC, BIT(GO_SHIFT) | BIT(RESULTS_DUMP_SHIFT));
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}
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static int qce_setup_regs_ahash(struct crypto_async_request *async_req,
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u32 totallen, u32 offset)
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{
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@ -303,6 +225,87 @@ go_proc:
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return 0;
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}
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#endif
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#ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER
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static u32 qce_encr_cfg(unsigned long flags, u32 aes_key_size)
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{
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u32 cfg = 0;
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if (IS_AES(flags)) {
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if (aes_key_size == AES_KEYSIZE_128)
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cfg |= ENCR_KEY_SZ_AES128 << ENCR_KEY_SZ_SHIFT;
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else if (aes_key_size == AES_KEYSIZE_256)
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cfg |= ENCR_KEY_SZ_AES256 << ENCR_KEY_SZ_SHIFT;
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}
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if (IS_AES(flags))
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cfg |= ENCR_ALG_AES << ENCR_ALG_SHIFT;
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else if (IS_DES(flags) || IS_3DES(flags))
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cfg |= ENCR_ALG_DES << ENCR_ALG_SHIFT;
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if (IS_DES(flags))
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cfg |= ENCR_KEY_SZ_DES << ENCR_KEY_SZ_SHIFT;
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if (IS_3DES(flags))
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cfg |= ENCR_KEY_SZ_3DES << ENCR_KEY_SZ_SHIFT;
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switch (flags & QCE_MODE_MASK) {
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case QCE_MODE_ECB:
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cfg |= ENCR_MODE_ECB << ENCR_MODE_SHIFT;
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break;
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case QCE_MODE_CBC:
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cfg |= ENCR_MODE_CBC << ENCR_MODE_SHIFT;
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break;
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case QCE_MODE_CTR:
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cfg |= ENCR_MODE_CTR << ENCR_MODE_SHIFT;
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break;
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case QCE_MODE_XTS:
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cfg |= ENCR_MODE_XTS << ENCR_MODE_SHIFT;
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break;
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case QCE_MODE_CCM:
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cfg |= ENCR_MODE_CCM << ENCR_MODE_SHIFT;
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cfg |= LAST_CCM_XFR << LAST_CCM_SHIFT;
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break;
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default:
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return ~0;
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}
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return cfg;
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}
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static void qce_xts_swapiv(__be32 *dst, const u8 *src, unsigned int ivsize)
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{
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u8 swap[QCE_AES_IV_LENGTH];
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u32 i, j;
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if (ivsize > QCE_AES_IV_LENGTH)
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return;
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memset(swap, 0, QCE_AES_IV_LENGTH);
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for (i = (QCE_AES_IV_LENGTH - ivsize), j = ivsize - 1;
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i < QCE_AES_IV_LENGTH; i++, j--)
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swap[i] = src[j];
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qce_cpu_to_be32p_array(dst, swap, QCE_AES_IV_LENGTH);
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}
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static void qce_xtskey(struct qce_device *qce, const u8 *enckey,
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unsigned int enckeylen, unsigned int cryptlen)
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{
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u32 xtskey[QCE_MAX_CIPHER_KEY_SIZE / sizeof(u32)] = {0};
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unsigned int xtsklen = enckeylen / (2 * sizeof(u32));
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unsigned int xtsdusize;
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qce_cpu_to_be32p_array((__be32 *)xtskey, enckey + enckeylen / 2,
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enckeylen / 2);
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qce_write_array(qce, REG_ENCR_XTS_KEY0, xtskey, xtsklen);
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/* xts du size 512B */
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xtsdusize = min_t(u32, QCE_SECTOR_SIZE, cryptlen);
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qce_write(qce, REG_ENCR_XTS_DU_SIZE, xtsdusize);
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}
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static int qce_setup_regs_skcipher(struct crypto_async_request *async_req,
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u32 totallen, u32 offset)
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@ -384,15 +387,20 @@ static int qce_setup_regs_skcipher(struct crypto_async_request *async_req,
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return 0;
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}
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#endif
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int qce_start(struct crypto_async_request *async_req, u32 type, u32 totallen,
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u32 offset)
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{
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switch (type) {
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#ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER
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case CRYPTO_ALG_TYPE_SKCIPHER:
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return qce_setup_regs_skcipher(async_req, totallen, offset);
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#endif
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#ifdef CONFIG_CRYPTO_DEV_QCE_SHA
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case CRYPTO_ALG_TYPE_AHASH:
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return qce_setup_regs_ahash(async_req, totallen, offset);
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#endif
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default:
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return -EINVAL;
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}
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@ -22,8 +22,12 @@
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#define QCE_QUEUE_LENGTH 1
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static const struct qce_algo_ops *qce_ops[] = {
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#ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER
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&skcipher_ops,
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#endif
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#ifdef CONFIG_CRYPTO_DEV_QCE_SHA
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&ahash_ops,
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#endif
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};
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static void qce_unregister_algs(struct qce_device *qce)
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