[ARM] pxa: better MFP low power state support for pxa25x/pxa27x
When configured as a specific low power state: MFP_LPM_DRIVE_LOW, MFP_LPM_DRIVE_HIGH, the corresponding GPDR register bit during low power mode shall be re-configured as output (if they are not configured so), thus the PGSRx bits can output. Create an additional low power values GPDR registers, and properly save/restore the GAFR + GPDR registers when doing suspend/resume. Signed-off-by: Eric Miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>hifive-unleashed-5.1
Eric Miao
Russell King
parent
4fa7c24e94
commit
5a3d965190
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@ -65,4 +65,5 @@ static inline void pxa3xx_clear_reset_status(unsigned int mask) {}
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extern struct sysdev_class pxa_irq_sysclass;
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extern struct sysdev_class pxa_gpio_sysclass;
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extern struct sysdev_class pxa2xx_mfp_sysclass;
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extern struct sysdev_class pxa3xx_mfp_sysclass;
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@ -274,12 +274,13 @@ typedef unsigned long mfp_cfg_t;
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#define MFP_DS_MASK (0x7 << 13)
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#define MFP_DS(x) (((x) >> 13) & 0x7)
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#define MFP_LPM_INPUT (0x0 << 16)
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#define MFP_LPM_DEFAULT (0x0 << 16)
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#define MFP_LPM_DRIVE_LOW (0x1 << 16)
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#define MFP_LPM_DRIVE_HIGH (0x2 << 16)
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#define MFP_LPM_PULL_LOW (0x3 << 16)
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#define MFP_LPM_PULL_HIGH (0x4 << 16)
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#define MFP_LPM_FLOAT (0x5 << 16)
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#define MFP_LPM_INPUT (0x6 << 16)
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#define MFP_LPM_STATE_MASK (0x7 << 16)
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#define MFP_LPM_STATE(x) (((x) >> 16) & 0x7)
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@ -297,7 +298,7 @@ typedef unsigned long mfp_cfg_t;
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#define MFP_PULL_MASK (0x3 << 21)
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#define MFP_PULL(x) (((x) >> 21) & 0x3)
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#define MFP_CFG_DEFAULT (MFP_AF0 | MFP_DS03X | MFP_LPM_INPUT |\
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#define MFP_CFG_DEFAULT (MFP_AF0 | MFP_DS03X | MFP_LPM_DEFAULT |\
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MFP_LPM_EDGE_NONE | MFP_PULL_NONE)
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#define MFP_CFG(pin, af) \
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@ -25,7 +25,12 @@
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#include "generic.h"
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#define PGSR(x) __REG2(0x40F00020, ((x) & 0x60) >> 3)
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#define gpio_to_bank(gpio) ((gpio) >> 5)
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#define PGSR(x) __REG2(0x40F00020, (x) << 2)
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#define __GAFR(u, x) __REG2((u) ? 0x40E00058 : 0x40E00054, (x) << 3)
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#define GAFR_L(x) __GAFR(0, x)
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#define GAFR_U(x) __GAFR(1, x)
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#define PWER_WE35 (1 << 24)
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@ -38,49 +43,59 @@ struct gpio_desc {
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};
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static struct gpio_desc gpio_desc[MFP_PIN_GPIO127 + 1];
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static int gpio_nr;
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static int __mfp_config_lpm(unsigned gpio, unsigned long lpm)
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{
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unsigned mask = GPIO_bit(gpio);
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/* low power state */
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switch (lpm) {
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case MFP_LPM_DRIVE_HIGH:
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PGSR(gpio) |= mask;
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break;
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case MFP_LPM_DRIVE_LOW:
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PGSR(gpio) &= ~mask;
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break;
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case MFP_LPM_INPUT:
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break;
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default:
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pr_warning("%s: invalid low power state for GPIO%d\n",
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__func__, gpio);
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return -EINVAL;
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}
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return 0;
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}
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static unsigned long gpdr_lpm[4];
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static int __mfp_config_gpio(unsigned gpio, unsigned long c)
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{
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unsigned long gafr, mask = GPIO_bit(gpio);
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int fn;
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int bank = gpio_to_bank(gpio);
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int uorl = !!(gpio & 0x10); /* GAFRx_U or GAFRx_L ? */
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int shft = (gpio & 0xf) << 1;
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int fn = MFP_AF(c);
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int dir = c & MFP_DIR_OUT;
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fn = MFP_AF(c);
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if (fn > 3)
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return -EINVAL;
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/* alternate function and direction */
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gafr = GAFR(gpio) & ~(0x3 << ((gpio & 0xf) * 2));
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GAFR(gpio) = gafr | (fn << ((gpio & 0xf) * 2));
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/* alternate function and direction at run-time */
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gafr = (uorl == 0) ? GAFR_L(bank) : GAFR_U(bank);
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gafr = (gafr & ~(0x3 << shft)) | (fn << shft);
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if (c & MFP_DIR_OUT)
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if (uorl == 0)
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GAFR_L(bank) = gafr;
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else
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GAFR_U(bank) = gafr;
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if (dir == MFP_DIR_OUT)
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GPDR(gpio) |= mask;
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else
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GPDR(gpio) &= ~mask;
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if (__mfp_config_lpm(gpio, c & MFP_LPM_STATE_MASK))
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return -EINVAL;
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/* alternate function and direction at low power mode */
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switch (c & MFP_LPM_STATE_MASK) {
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case MFP_LPM_DRIVE_HIGH:
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PGSR(bank) |= mask;
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dir = MFP_DIR_OUT;
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break;
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case MFP_LPM_DRIVE_LOW:
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PGSR(bank) &= ~mask;
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dir = MFP_DIR_OUT;
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break;
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case MFP_LPM_DEFAULT:
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break;
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default:
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/* warning and fall through, treat as MFP_LPM_DEFAULT */
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pr_warning("%s: GPIO%d: unsupported low power mode\n",
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__func__, gpio);
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break;
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}
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if (dir == MFP_DIR_OUT)
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gpdr_lpm[bank] |= mask;
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else
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gpdr_lpm[bank] &= ~mask;
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/* give early warning if MFP_LPM_CAN_WAKEUP is set on the
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* configurations of those pins not able to wakeup
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@ -91,7 +106,7 @@ static int __mfp_config_gpio(unsigned gpio, unsigned long c)
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return -EINVAL;
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}
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if ((c & MFP_LPM_CAN_WAKEUP) && (c & MFP_DIR_OUT)) {
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if ((c & MFP_LPM_CAN_WAKEUP) && (dir == MFP_DIR_OUT)) {
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pr_warning("%s: output GPIO%d unable to wakeup\n",
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__func__, gpio);
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return -EINVAL;
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@ -135,7 +150,7 @@ void pxa2xx_mfp_config(unsigned long *mfp_cfgs, int num)
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void pxa2xx_mfp_set_lpm(int mfp, unsigned long lpm)
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{
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unsigned long flags;
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unsigned long flags, c;
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int gpio;
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gpio = __mfp_validate(mfp);
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@ -143,7 +158,11 @@ void pxa2xx_mfp_set_lpm(int mfp, unsigned long lpm)
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return;
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local_irq_save(flags);
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__mfp_config_lpm(gpio, lpm);
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c = gpio_desc[gpio].config;
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c = (c & ~MFP_LPM_STATE_MASK) | lpm;
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__mfp_config_gpio(gpio, c);
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local_irq_restore(flags);
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}
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@ -187,23 +206,22 @@ int gpio_set_wake(unsigned int gpio, unsigned int on)
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}
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#ifdef CONFIG_PXA25x
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static int __init pxa25x_mfp_init(void)
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static void __init pxa25x_mfp_init(void)
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{
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int i;
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if (cpu_is_pxa25x()) {
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for (i = 0; i <= 84; i++)
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gpio_desc[i].valid = 1;
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for (i = 0; i <= 84; i++)
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gpio_desc[i].valid = 1;
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for (i = 0; i <= 15; i++) {
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gpio_desc[i].can_wakeup = 1;
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gpio_desc[i].mask = GPIO_bit(i);
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}
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for (i = 0; i <= 15; i++) {
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gpio_desc[i].can_wakeup = 1;
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gpio_desc[i].mask = GPIO_bit(i);
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}
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return 0;
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gpio_nr = 85;
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}
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postcore_initcall(pxa25x_mfp_init);
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#else
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static inline void pxa25x_mfp_init(void) {}
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#endif /* CONFIG_PXA25x */
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#ifdef CONFIG_PXA27x
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@ -233,45 +251,103 @@ int keypad_set_wake(unsigned int on)
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return 0;
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}
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static int __init pxa27x_mfp_init(void)
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static void __init pxa27x_mfp_init(void)
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{
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int i, gpio;
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if (cpu_is_pxa27x()) {
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for (i = 0; i <= 120; i++) {
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/* skip GPIO2, 5, 6, 7, 8, they are not
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* valid pins allow configuration
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*/
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if (i == 2 || i == 5 || i == 6 ||
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i == 7 || i == 8)
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continue;
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for (i = 0; i <= 120; i++) {
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/* skip GPIO2, 5, 6, 7, 8, they are not
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* valid pins allow configuration
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*/
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if (i == 2 || i == 5 || i == 6 || i == 7 || i == 8)
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continue;
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gpio_desc[i].valid = 1;
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}
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/* Keypad GPIOs */
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for (i = 0; i < ARRAY_SIZE(pxa27x_pkwr_gpio); i++) {
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gpio = pxa27x_pkwr_gpio[i];
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gpio_desc[gpio].can_wakeup = 1;
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gpio_desc[gpio].keypad_gpio = 1;
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gpio_desc[gpio].mask = 1 << i;
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}
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/* Overwrite GPIO13 as a PWER wakeup source */
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for (i = 0; i <= 15; i++) {
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/* skip GPIO2, 5, 6, 7, 8 */
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if (GPIO_bit(i) & 0x1e4)
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continue;
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gpio_desc[i].can_wakeup = 1;
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gpio_desc[i].mask = GPIO_bit(i);
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}
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gpio_desc[35].can_wakeup = 1;
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gpio_desc[35].mask = PWER_WE35;
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gpio_desc[i].valid = 1;
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}
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/* Keypad GPIOs */
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for (i = 0; i < ARRAY_SIZE(pxa27x_pkwr_gpio); i++) {
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gpio = pxa27x_pkwr_gpio[i];
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gpio_desc[gpio].can_wakeup = 1;
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gpio_desc[gpio].keypad_gpio = 1;
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gpio_desc[gpio].mask = 1 << i;
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}
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/* Overwrite GPIO13 as a PWER wakeup source */
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for (i = 0; i <= 15; i++) {
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/* skip GPIO2, 5, 6, 7, 8 */
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if (GPIO_bit(i) & 0x1e4)
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continue;
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gpio_desc[i].can_wakeup = 1;
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gpio_desc[i].mask = GPIO_bit(i);
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}
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gpio_desc[35].can_wakeup = 1;
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gpio_desc[35].mask = PWER_WE35;
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gpio_nr = 121;
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}
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#else
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static inline void pxa27x_mfp_init(void) {}
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#endif /* CONFIG_PXA27x */
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#ifdef CONFIG_PM
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static unsigned long saved_gafr[2][4];
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static unsigned long saved_gpdr[4];
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static int pxa2xx_mfp_suspend(struct sys_device *d, pm_message_t state)
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{
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int i;
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for (i = 0; i <= gpio_to_bank(gpio_nr); i++) {
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saved_gafr[0][i] = GAFR_L(i);
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saved_gafr[1][i] = GAFR_U(i);
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saved_gpdr[i] = GPDR(i * 32);
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GPDR(i * 32) = gpdr_lpm[i];
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}
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return 0;
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}
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postcore_initcall(pxa27x_mfp_init);
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#endif /* CONFIG_PXA27x */
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static int pxa2xx_mfp_resume(struct sys_device *d)
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{
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int i;
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for (i = 0; i <= gpio_to_bank(gpio_nr); i++) {
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GAFR_L(i) = saved_gafr[0][i];
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GAFR_U(i) = saved_gafr[1][i];
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GPDR(i * 32) = saved_gpdr[i];
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}
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PSSR = PSSR_RDH | PSSR_PH;
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return 0;
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}
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#else
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#define pxa2xx_mfp_suspend NULL
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#define pxa2xx_mfp_resume NULL
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#endif
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struct sysdev_class pxa2xx_mfp_sysclass = {
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.name = "mfp",
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.suspend = pxa2xx_mfp_suspend,
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.resume = pxa2xx_mfp_resume,
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};
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static int __init pxa2xx_mfp_init(void)
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{
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int i;
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if (cpu_is_pxa25x())
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pxa25x_mfp_init();
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if (cpu_is_pxa27x())
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pxa27x_mfp_init();
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/* initialize gafr_run[], pgsr_lpm[] from existing values */
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for (i = 0; i <= gpio_to_bank(gpio_nr); i++)
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gpdr_lpm[i] = GPDR(i * 32);
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return sysdev_class_register(&pxa2xx_mfp_sysclass);
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}
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postcore_initcall(pxa2xx_mfp_init);
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@ -203,33 +203,17 @@ static struct clk pxa25x_clks[] = {
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* More ones like CP and general purpose register values are preserved
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* with the stack pointer in sleep.S.
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*/
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enum { SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2,
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SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
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SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U,
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SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U,
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enum {
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SLEEP_SAVE_PSTR,
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SLEEP_SAVE_CKEN,
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SLEEP_SAVE_COUNT
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};
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static void pxa25x_cpu_pm_save(unsigned long *sleep_save)
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{
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SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2);
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SAVE(GAFR0_L); SAVE(GAFR0_U);
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SAVE(GAFR1_L); SAVE(GAFR1_U);
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SAVE(GAFR2_L); SAVE(GAFR2_U);
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SAVE(CKEN);
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SAVE(PSTR);
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/* Clear GPIO transition detect bits */
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GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2;
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}
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static void pxa25x_cpu_pm_restore(unsigned long *sleep_save)
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@ -237,14 +221,6 @@ static void pxa25x_cpu_pm_restore(unsigned long *sleep_save)
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/* ensure not to come back here if it wasn't intended */
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PSPR = 0;
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/* restore registers */
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RESTORE(GAFR0_L); RESTORE(GAFR0_U);
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RESTORE(GAFR1_L); RESTORE(GAFR1_U);
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RESTORE(GAFR2_L); RESTORE(GAFR2_U);
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RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2);
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PSSR = PSSR_RDH | PSSR_PH;
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RESTORE(CKEN);
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RESTORE(PSTR);
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}
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@ -329,6 +305,8 @@ static struct platform_device *pxa25x_devices[] __initdata = {
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static struct sys_device pxa25x_sysdev[] = {
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{
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.cls = &pxa_irq_sysclass,
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}, {
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.cls = &pxa2xx_mfp_sysclass,
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}, {
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.cls = &pxa_gpio_sysclass,
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},
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@ -183,36 +183,18 @@ static struct clk pxa27x_clks[] = {
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* More ones like CP and general purpose register values are preserved
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* with the stack pointer in sleep.S.
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*/
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enum { SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, SLEEP_SAVE_PGSR3,
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SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
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SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U,
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SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U,
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SLEEP_SAVE_GAFR3_L, SLEEP_SAVE_GAFR3_U,
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enum {
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SLEEP_SAVE_PSTR,
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SLEEP_SAVE_CKEN,
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SLEEP_SAVE_MDREFR,
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SLEEP_SAVE_PWER, SLEEP_SAVE_PCFR, SLEEP_SAVE_PRER,
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SLEEP_SAVE_PFER, SLEEP_SAVE_PKWR,
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SLEEP_SAVE_PCFR,
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SLEEP_SAVE_COUNT
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};
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void pxa27x_cpu_pm_save(unsigned long *sleep_save)
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{
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SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2); SAVE(PGSR3);
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SAVE(GAFR0_L); SAVE(GAFR0_U);
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SAVE(GAFR1_L); SAVE(GAFR1_U);
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SAVE(GAFR2_L); SAVE(GAFR2_U);
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SAVE(GAFR3_L); SAVE(GAFR3_U);
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SAVE(MDREFR);
|
||||
SAVE(PWER); SAVE(PCFR); SAVE(PRER);
|
||||
SAVE(PFER); SAVE(PKWR);
|
||||
SAVE(PCFR);
|
||||
|
||||
SAVE(CKEN);
|
||||
SAVE(PSTR);
|
||||
|
|
@ -223,21 +205,12 @@ void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
|
|||
/* ensure not to come back here if it wasn't intended */
|
||||
PSPR = 0;
|
||||
|
||||
/* restore registers */
|
||||
RESTORE(GAFR0_L); RESTORE(GAFR0_U);
|
||||
RESTORE(GAFR1_L); RESTORE(GAFR1_U);
|
||||
RESTORE(GAFR2_L); RESTORE(GAFR2_U);
|
||||
RESTORE(GAFR3_L); RESTORE(GAFR3_U);
|
||||
RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2); RESTORE(PGSR3);
|
||||
|
||||
RESTORE(MDREFR);
|
||||
RESTORE(PWER); RESTORE(PCFR); RESTORE(PRER);
|
||||
RESTORE(PFER); RESTORE(PKWR);
|
||||
RESTORE(PCFR);
|
||||
|
||||
PSSR = PSSR_RDH | PSSR_PH;
|
||||
|
||||
RESTORE(CKEN);
|
||||
|
||||
RESTORE(PSTR);
|
||||
}
|
||||
|
||||
|
|
@ -375,6 +348,8 @@ static struct platform_device *devices[] __initdata = {
|
|||
static struct sys_device pxa27x_sysdev[] = {
|
||||
{
|
||||
.cls = &pxa_irq_sysclass,
|
||||
}, {
|
||||
.cls = &pxa2xx_mfp_sysclass,
|
||||
}, {
|
||||
.cls = &pxa_gpio_sysclass,
|
||||
},
|
||||
|
|
|
|||
Loading…
Reference in New Issue