drm/i915/icl: Configure DSI Dual link mode
This patch configures DSI video mode dual link by programming DSS_CTL registers. v2: Use new bitfield definitions from Anusha's patch Correct register to be programmed and use max depth buffer value (James) v3 by Jani: - checkpatch fixes Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/d8962f4e1beffc2099b8bef8cb5a5191aa1d9efd.1543500286.git.jani.nikula@intel.com
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@ -257,6 +257,45 @@ static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
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}
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}
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static void configure_dual_link_mode(struct intel_encoder *encoder,
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const struct intel_crtc_state *pipe_config)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
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u32 dss_ctl1;
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dss_ctl1 = I915_READ(DSS_CTL1);
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dss_ctl1 |= SPLITTER_ENABLE;
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dss_ctl1 &= ~OVERLAP_PIXELS_MASK;
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dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap);
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if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
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const struct drm_display_mode *adjusted_mode =
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&pipe_config->base.adjusted_mode;
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u32 dss_ctl2;
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u16 hactive = adjusted_mode->crtc_hdisplay;
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u16 dl_buffer_depth;
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dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE;
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dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap;
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if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH)
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DRM_ERROR("DL buffer depth exceed max value\n");
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dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK;
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dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
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dss_ctl2 = I915_READ(DSS_CTL2);
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dss_ctl2 &= ~RIGHT_DL_BUF_TARGET_DEPTH_MASK;
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dss_ctl2 |= RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
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I915_WRITE(DSS_CTL2, dss_ctl2);
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} else {
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/* Interleave */
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dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE;
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}
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I915_WRITE(DSS_CTL1, dss_ctl1);
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}
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static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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@ -591,7 +630,8 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
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I915_WRITE(TRANS_DDI_FUNC_CTL2(dsi_trans), tmp);
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}
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//TODO: configure DSS_CTL1
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/* configure stream splitting */
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configure_dual_link_mode(encoder, pipe_config);
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}
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for_each_dsi_port(port, intel_dsi->ports) {
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