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irqchip/gic-v3-its: Add missing cache flushes 

When the ITS is configured for non-cacheable transactions, make sure
that the allocated, zeroed memory is flushed to the Point of
Coherency, allowing the ITS to observe the zeros instead of random
garbage (or even get its own data overwritten by zeros being evicted
from the cache...).

Fixes: 241a386c7d "irqchip: gicv3-its: Use non-cacheable accesses when no shareability"
Reported-and-tested-by: Stuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Pavel Fedin <p.fedin@samsung.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Link: http://lkml.kernel.org/r/1442142873-20213-3-git-send-email-marc.zyngier@arm.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
hifive-unleashed-5.1
Marc Zyngier 2015-09-13 12:14:32 +01:00 committed by Thomas Gleixner
parent 12e14066f4
commit 5a9a8915c8
1 changed files with 5 additions and 1 deletions
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6
drivers/irqchip/irq-gic-v3-its.c
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@ -898,8 +898,10 @@ retry_baser:
* non-cacheable as well.
*/
shr = tmp & GITS_BASER_SHAREABILITY_MASK;
if (!shr)
if (!shr) {
cache = GITS_BASER_nC;
__flush_dcache_area(base, alloc_size);
}
goto retry_baser;
}
@ -1140,6 +1142,8 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
return NULL;
}
__flush_dcache_area(itt, sz);
dev->its = its;
dev->itt = itt;
dev->nr_ites = nr_ites;