powerpc/8xx: Temporarily disable 16k pages and hugepages
In preparation of making use of hardware assistance in TLB handlers, this patch temporarily disables 16K pages and hugepages. The reason is that when using HW assistance in 4K pages mode, the linux model fit with the HW model for 4K pages and 8M pages. However for 16K pages and 512K mode some additional work is needed to get linux model fit with HW model. For the 8M pages, they will naturaly come back when we switch to HW assistance, without any additional handling. In order to keep the following patch smaller, the removal of the current special handling for 8M pages gets removed here as well. Therefore the 4K pages mode will be implemented first and without support for 512k hugepages. Then the 512k hugepages will be brought back. And the 16K pages will be implemented in the following step. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>hifive-unleashed-5.1
Christophe Leroy
Michael Ellerman
parent
8cfe4f5242
commit
5af543be14
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@ -689,7 +689,7 @@ config PPC_4K_PAGES
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config PPC_16K_PAGES
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bool "16k page size"
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depends on 44x || PPC_8xx
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depends on 44x
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config PPC_64K_PAGES
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bool "64k page size"
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@ -314,7 +314,7 @@ SystemCall:
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InstructionTLBMiss:
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mtspr SPRN_SPRG_SCRATCH0, r10
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mtspr SPRN_SPRG_SCRATCH1, r11
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#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE)
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#ifdef ITLB_MISS_KERNEL
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mtspr SPRN_SPRG_SCRATCH2, r12
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#endif
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@ -325,10 +325,8 @@ InstructionTLBMiss:
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INVALIDATE_ADJACENT_PAGES_CPU15(r11, r10)
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/* Only modules will cause ITLB Misses as we always
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* pin the first 8MB of kernel memory */
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#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE)
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mfcr r12
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#endif
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#ifdef ITLB_MISS_KERNEL
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mfcr r12
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#if defined(SIMPLE_KERNEL_ADDRESS) && defined(CONFIG_PIN_TLB_TEXT)
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andis. r11, r10, 0x8000 /* Address >= 0x80000000 */
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#else
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@ -360,15 +358,9 @@ InstructionTLBMiss:
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/* Extract level 2 index */
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rlwinm r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
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#ifdef CONFIG_HUGETLB_PAGE
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mtcr r11
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bt- 28, 10f /* bit 28 = Large page (8M) */
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bt- 29, 20f /* bit 29 = Large page (8M or 512k) */
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#endif
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rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */
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lwz r10, 0(r10) /* Get the pte */
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4:
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#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE)
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#ifdef ITLB_MISS_KERNEL
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mtcr r12
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#endif
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/* Load the MI_TWC with the attributes for this "segment." */
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@ -393,7 +385,7 @@ InstructionTLBMiss:
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/* Restore registers */
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0: mfspr r10, SPRN_SPRG_SCRATCH0
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mfspr r11, SPRN_SPRG_SCRATCH1
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#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE)
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#ifdef ITLB_MISS_KERNEL
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mfspr r12, SPRN_SPRG_SCRATCH2
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#endif
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rfi
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@ -406,35 +398,12 @@ InstructionTLBMiss:
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stw r10, (itlb_miss_counter - PAGE_OFFSET)@l(0)
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mfspr r10, SPRN_SPRG_SCRATCH0
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mfspr r11, SPRN_SPRG_SCRATCH1
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#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE)
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#ifdef ITLB_MISS_KERNEL
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mfspr r12, SPRN_SPRG_SCRATCH2
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#endif
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rfi
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#endif
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#ifdef CONFIG_HUGETLB_PAGE
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10: /* 8M pages */
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#ifdef CONFIG_PPC_16K_PAGES
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/* Extract level 2 index */
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rlwinm r10, r10, 32 - (PAGE_SHIFT_8M - PAGE_SHIFT), 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1), 29
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/* Add level 2 base */
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rlwimi r10, r11, 0, 0, 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1) - 1
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#else
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/* Level 2 base */
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rlwinm r10, r11, 0, ~HUGEPD_SHIFT_MASK
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#endif
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lwz r10, 0(r10) /* Get the pte */
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b 4b
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20: /* 512k pages */
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/* Extract level 2 index */
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rlwinm r10, r10, 32 - (PAGE_SHIFT_512K - PAGE_SHIFT), 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1), 29
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/* Add level 2 base */
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rlwimi r10, r11, 0, 0, 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1) - 1
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lwz r10, 0(r10) /* Get the pte */
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b 4b
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#endif
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. = 0x1200
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DataStoreTLBMiss:
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mtspr SPRN_SPRG_SCRATCH0, r10
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@ -472,11 +441,6 @@ DataStoreTLBMiss:
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*/
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/* Extract level 2 index */
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rlwinm r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
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#ifdef CONFIG_HUGETLB_PAGE
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mtcr r11
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bt- 28, 10f /* bit 28 = Large page (8M) */
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bt- 29, 20f /* bit 29 = Large page (8M or 512k) */
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#endif
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rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */
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lwz r10, 0(r10) /* Get the pte */
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4:
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@ -534,29 +498,6 @@ DataStoreTLBMiss:
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rfi
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#endif
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#ifdef CONFIG_HUGETLB_PAGE
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10: /* 8M pages */
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/* Extract level 2 index */
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#ifdef CONFIG_PPC_16K_PAGES
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rlwinm r10, r10, 32 - (PAGE_SHIFT_8M - PAGE_SHIFT), 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1), 29
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/* Add level 2 base */
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rlwimi r10, r11, 0, 0, 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1) - 1
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#else
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/* Level 2 base */
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rlwinm r10, r11, 0, ~HUGEPD_SHIFT_MASK
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#endif
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lwz r10, 0(r10) /* Get the pte */
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b 4b
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20: /* 512k pages */
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/* Extract level 2 index */
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rlwinm r10, r10, 32 - (PAGE_SHIFT_512K - PAGE_SHIFT), 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1), 29
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/* Add level 2 base */
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rlwimi r10, r11, 0, 0, 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1) - 1
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lwz r10, 0(r10) /* Get the pte */
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b 4b
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#endif
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/* This is an instruction TLB error on the MPC8xx. This could be due
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* to many reasons, such as executing guarded memory or illegal instruction
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* addresses. There is nothing to do but handle a big time error fault.
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@ -773,12 +714,7 @@ FixupDAR:/* Entry point for dcbx workaround. */
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/* concat physical page address(r11) and page offset(r10) */
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200:
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#ifdef CONFIG_PPC_16K_PAGES
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rlwinm r11, r11, 0, 0, 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1) - 1
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rlwimi r11, r10, 32 - (PAGE_SHIFT_8M - 2), 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1), 29
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#else
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rlwinm r11, r10, 0, ~HUGEPD_SHIFT_MASK
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#endif
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lwz r11, 0(r11) /* Get the pte */
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/* concat physical page address(r11) and page offset(r10) */
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rlwimi r11, r10, 0, 32 - PAGE_SHIFT_8M, 31
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@ -97,12 +97,6 @@ struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT] = {
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.shift = 14,
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},
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#endif
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[MMU_PAGE_512K] = {
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.shift = 19,
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},
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[MMU_PAGE_8M] = {
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.shift = 23,
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},
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};
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#else
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struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT] = {
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