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MIPS: Always use r4k_wait_irqoff for MIPSr6 

Prior to release 6 of the MIPS architecture it has been implementation
dependent whether masked interrupts cause a wait instruction to return,
so the kernel has effectively had to maintain a whitelist of cores upon
which it is safe to use the r4k_wait_irqoff cpu_wait implementation.
With MIPSr6 this is no longer implementation dependent and
r4k_wait_irqoff can always be used.

Remove the existing I6400 case which will no longer ever be hit, and was
incorrect anyway since I6400 & r6 in general doesn't have the WII bit.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Cc: linux-kernel@vger.kernel.org
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Markos Chandras <markos.chandras@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/11210/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
hifive-unleashed-5.1
Paul Burton 2015-09-22 11:24:20 -07:00 committed by Ralf Baechle
parent 78a54c4d8e
commit 5b10a0e84b
1 changed files with 10 additions and 1 deletions
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11
arch/mips/kernel/idle.c
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@ -134,6 +134,16 @@ void __init check_wait(void)
return;
}
/*
* MIPSr6 specifies that masked interrupts should unblock an executing
* wait instruction, and thus that it is safe for us to use
* r4k_wait_irqoff. Yippee!
*/
if (cpu_has_mips_r6) {
cpu_wait = r4k_wait_irqoff;
return;
}
switch (current_cpu_type()) {
case CPU_R3081:
case CPU_R3081E:
@ -196,7 +206,6 @@ void __init check_wait(void)
case CPU_INTERAPTIV:
case CPU_M5150:
case CPU_QEMU_GENERIC:
case CPU_I6400:
cpu_wait = r4k_wait;
if (read_c0_config7() & MIPS_CONF7_WII)
cpu_wait = r4k_wait_irqoff;