drm/amd/pp: use mlck_table.count for array loop index limit
v2: use temporaries to trivially reduces object size. The for-loops process data in the mclk_table but use slck_table.count as the loop index limit. I believe these are cut-n-paste errors from the previous almost identical loops as indicated by static analysis. Fix these. Detected by CoverityScan, CID#1466001 ("Copy-paste error") Fixes:5d97cf39ff
("drm/amd/pp: Add and initialize OD_dpm_table for CI/VI.") Fixes:5e4d4fbea5
("drm/amd/pp: Implement edit_dpm_table on smu7") Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -833,6 +833,7 @@ static int smu7_odn_initial_default_setting(struct pp_hwmgr *hwmgr)
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struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
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struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
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struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
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struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
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struct phm_odn_performance_level *entries;
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if (table_info == NULL)
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if (table_info == NULL)
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return -EINVAL;
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return -EINVAL;
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@ -842,11 +843,11 @@ static int smu7_odn_initial_default_setting(struct pp_hwmgr *hwmgr)
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odn_table->odn_core_clock_dpm_levels.num_of_pl =
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odn_table->odn_core_clock_dpm_levels.num_of_pl =
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data->golden_dpm_table.sclk_table.count;
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data->golden_dpm_table.sclk_table.count;
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entries = odn_table->odn_core_clock_dpm_levels.entries;
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for (i=0; i<data->golden_dpm_table.sclk_table.count; i++) {
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for (i=0; i<data->golden_dpm_table.sclk_table.count; i++) {
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odn_table->odn_core_clock_dpm_levels.entries[i].clock =
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entries[i].clock = data->golden_dpm_table.sclk_table.dpm_levels[i].value;
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data->golden_dpm_table.sclk_table.dpm_levels[i].value;
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entries[i].enabled = true;
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odn_table->odn_core_clock_dpm_levels.entries[i].enabled = true;
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entries[i].vddc = dep_sclk_table->entries[i].vddc;
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odn_table->odn_core_clock_dpm_levels.entries[i].vddc = dep_sclk_table->entries[i].vddc;
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}
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}
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smu7_get_voltage_dependency_table(dep_sclk_table,
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smu7_get_voltage_dependency_table(dep_sclk_table,
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@ -854,11 +855,11 @@ static int smu7_odn_initial_default_setting(struct pp_hwmgr *hwmgr)
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odn_table->odn_memory_clock_dpm_levels.num_of_pl =
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odn_table->odn_memory_clock_dpm_levels.num_of_pl =
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data->golden_dpm_table.mclk_table.count;
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data->golden_dpm_table.mclk_table.count;
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for (i=0; i<data->golden_dpm_table.sclk_table.count; i++) {
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entries = odn_table->odn_memory_clock_dpm_levels.entries;
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odn_table->odn_memory_clock_dpm_levels.entries[i].clock =
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for (i=0; i<data->golden_dpm_table.mclk_table.count; i++) {
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data->golden_dpm_table.mclk_table.dpm_levels[i].value;
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entries[i].clock = data->golden_dpm_table.mclk_table.dpm_levels[i].value;
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odn_table->odn_memory_clock_dpm_levels.entries[i].enabled = true;
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entries[i].enabled = true;
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odn_table->odn_memory_clock_dpm_levels.entries[i].vddc = dep_mclk_table->entries[i].vddc;
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entries[i].vddc = dep_mclk_table->entries[i].vddc;
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}
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}
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smu7_get_voltage_dependency_table(dep_mclk_table,
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smu7_get_voltage_dependency_table(dep_mclk_table,
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@ -4728,7 +4729,7 @@ static void smu7_check_dpm_table_updated(struct pp_hwmgr *hwmgr)
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}
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}
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}
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}
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for (i=0; i<data->dpm_table.sclk_table.count; i++) {
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for (i=0; i<data->dpm_table.mclk_table.count; i++) {
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if (odn_table->odn_memory_clock_dpm_levels.entries[i].clock !=
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if (odn_table->odn_memory_clock_dpm_levels.entries[i].clock !=
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data->dpm_table.mclk_table.dpm_levels[i].value) {
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data->dpm_table.mclk_table.dpm_levels[i].value) {
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data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
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data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
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