arcmsr: add support new adapter ARC12x4 series
Add code to support the new Areca Raid ARC12x4 series adapters. Signed-off-by: Ching Huang <ching2048@areca.com.tw> Reviewed-by: Tomas Henzl <thenzl@redhat.com> Signed-off-by: Christoph Hellwig <hch@lst.de>
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@ -63,12 +63,17 @@ struct device_attribute;
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#define ARCMSR_MAX_QBUFFER 4096
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#define ARCMSR_DEFAULT_SG_ENTRIES 38
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#define ARCMSR_MAX_HBB_POSTQUEUE 264
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#define ARCMSR_MAX_ARC1214_POSTQUEUE 256
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#define ARCMSR_MAX_ARC1214_DONEQUEUE 257
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#define ARCMSR_MAX_XFER_LEN 0x26000 /* 152K */
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#define ARCMSR_CDB_SG_PAGE_LENGTH 256
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#define ARCMST_NUM_MSIX_VECTORS 4
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#ifndef PCI_DEVICE_ID_ARECA_1880
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#define PCI_DEVICE_ID_ARECA_1880 0x1880
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#endif
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#ifndef PCI_DEVICE_ID_ARECA_1214
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#define PCI_DEVICE_ID_ARECA_1214 0x1214
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#endif
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/*
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**********************************************************************************
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**
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@ -339,6 +344,56 @@ struct FIRMWARE_INFO
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#define ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK 0x80000000
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/*
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*******************************************************************************
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** SPEC. for Areca Type D adapter
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*******************************************************************************
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*/
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#define ARCMSR_ARC1214_CHIP_ID 0x00004
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#define ARCMSR_ARC1214_CPU_MEMORY_CONFIGURATION 0x00008
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#define ARCMSR_ARC1214_I2_HOST_INTERRUPT_MASK 0x00034
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#define ARCMSR_ARC1214_SAMPLE_RESET 0x00100
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#define ARCMSR_ARC1214_RESET_REQUEST 0x00108
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#define ARCMSR_ARC1214_MAIN_INTERRUPT_STATUS 0x00200
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#define ARCMSR_ARC1214_PCIE_F0_INTERRUPT_ENABLE 0x0020C
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#define ARCMSR_ARC1214_INBOUND_MESSAGE0 0x00400
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#define ARCMSR_ARC1214_INBOUND_MESSAGE1 0x00404
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#define ARCMSR_ARC1214_OUTBOUND_MESSAGE0 0x00420
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#define ARCMSR_ARC1214_OUTBOUND_MESSAGE1 0x00424
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#define ARCMSR_ARC1214_INBOUND_DOORBELL 0x00460
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#define ARCMSR_ARC1214_OUTBOUND_DOORBELL 0x00480
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#define ARCMSR_ARC1214_OUTBOUND_DOORBELL_ENABLE 0x00484
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#define ARCMSR_ARC1214_INBOUND_LIST_BASE_LOW 0x01000
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#define ARCMSR_ARC1214_INBOUND_LIST_BASE_HIGH 0x01004
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#define ARCMSR_ARC1214_INBOUND_LIST_WRITE_POINTER 0x01018
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#define ARCMSR_ARC1214_OUTBOUND_LIST_BASE_LOW 0x01060
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#define ARCMSR_ARC1214_OUTBOUND_LIST_BASE_HIGH 0x01064
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#define ARCMSR_ARC1214_OUTBOUND_LIST_COPY_POINTER 0x0106C
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#define ARCMSR_ARC1214_OUTBOUND_LIST_READ_POINTER 0x01070
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#define ARCMSR_ARC1214_OUTBOUND_INTERRUPT_CAUSE 0x01088
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#define ARCMSR_ARC1214_OUTBOUND_INTERRUPT_ENABLE 0x0108C
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#define ARCMSR_ARC1214_MESSAGE_WBUFFER 0x02000
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#define ARCMSR_ARC1214_MESSAGE_RBUFFER 0x02100
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#define ARCMSR_ARC1214_MESSAGE_RWBUFFER 0x02200
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/* Host Interrupt Mask */
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#define ARCMSR_ARC1214_ALL_INT_ENABLE 0x00001010
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#define ARCMSR_ARC1214_ALL_INT_DISABLE 0x00000000
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/* Host Interrupt Status */
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#define ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR 0x00001000
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#define ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR 0x00000010
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/* DoorBell*/
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#define ARCMSR_ARC1214_DRV2IOP_DATA_IN_READY 0x00000001
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#define ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ 0x00000002
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/*inbound message 0 ready*/
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#define ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK 0x00000001
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/*outbound DATA WRITE isr door bell clear*/
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#define ARCMSR_ARC1214_IOP2DRV_DATA_READ_OK 0x00000002
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/*outbound message 0 ready*/
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#define ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE 0x02000000
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/*outbound message cmd isr door bell clear*/
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/*ARCMSR_HBAMU_MESSAGE_FIRMWARE_OK*/
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#define ARCMSR_ARC1214_MESSAGE_FIRMWARE_OK 0x80000000
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#define ARCMSR_ARC1214_OUTBOUND_LIST_INTERRUPT_CLEAR 0x00000001
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/*
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*******************************************************************************
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** ARECA SCSI COMMAND DESCRIPTOR BLOCK size 0x1F8 (504)
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*******************************************************************************
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*/
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@ -496,6 +551,56 @@ struct MessageUnit_C{
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uint32_t msgcode_rwbuffer[256]; /*2200 23FF*/
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};
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/*
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*********************************************************************
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** Messaging Unit (MU) of Type D processor
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*********************************************************************
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*/
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struct InBound_SRB {
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uint32_t addressLow; /* pointer to SRB block */
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uint32_t addressHigh;
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uint32_t length; /* in DWORDs */
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uint32_t reserved0;
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};
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struct OutBound_SRB {
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uint32_t addressLow; /* pointer to SRB block */
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uint32_t addressHigh;
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};
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struct MessageUnit_D {
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struct InBound_SRB post_qbuffer[ARCMSR_MAX_ARC1214_POSTQUEUE];
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volatile struct OutBound_SRB
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done_qbuffer[ARCMSR_MAX_ARC1214_DONEQUEUE];
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u16 postq_index;
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volatile u16 doneq_index;
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u32 __iomem *chip_id; /* 0x00004 */
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u32 __iomem *cpu_mem_config; /* 0x00008 */
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u32 __iomem *i2o_host_interrupt_mask; /* 0x00034 */
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u32 __iomem *sample_at_reset; /* 0x00100 */
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u32 __iomem *reset_request; /* 0x00108 */
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u32 __iomem *host_int_status; /* 0x00200 */
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u32 __iomem *pcief0_int_enable; /* 0x0020C */
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u32 __iomem *inbound_msgaddr0; /* 0x00400 */
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u32 __iomem *inbound_msgaddr1; /* 0x00404 */
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u32 __iomem *outbound_msgaddr0; /* 0x00420 */
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u32 __iomem *outbound_msgaddr1; /* 0x00424 */
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u32 __iomem *inbound_doorbell; /* 0x00460 */
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u32 __iomem *outbound_doorbell; /* 0x00480 */
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u32 __iomem *outbound_doorbell_enable; /* 0x00484 */
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u32 __iomem *inboundlist_base_low; /* 0x01000 */
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u32 __iomem *inboundlist_base_high; /* 0x01004 */
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u32 __iomem *inboundlist_write_pointer; /* 0x01018 */
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u32 __iomem *outboundlist_base_low; /* 0x01060 */
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u32 __iomem *outboundlist_base_high; /* 0x01064 */
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u32 __iomem *outboundlist_copy_pointer; /* 0x0106C */
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u32 __iomem *outboundlist_read_pointer; /* 0x01070 0x01072 */
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u32 __iomem *outboundlist_interrupt_cause; /* 0x1088 */
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u32 __iomem *outboundlist_interrupt_enable; /* 0x108C */
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u32 __iomem *message_wbuffer; /* 0x2000 */
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u32 __iomem *message_rbuffer; /* 0x2100 */
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u32 __iomem *msgcode_rwbuffer; /* 0x2200 */
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};
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/*
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*******************************************************************************
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** Adapter Control Block
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*******************************************************************************
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@ -518,12 +623,15 @@ struct AdapterControlBlock
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uint32_t reg_mu_acc_handle0;
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spinlock_t eh_lock;
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spinlock_t ccblist_lock;
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spinlock_t postq_lock;
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spinlock_t doneq_lock;
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spinlock_t rqbuffer_lock;
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spinlock_t wqbuffer_lock;
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union {
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struct MessageUnit_A __iomem *pmuA;
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struct MessageUnit_B *pmuB;
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struct MessageUnit_C __iomem *pmuC;
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struct MessageUnit_D *pmuD;
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};
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/* message unit ATU inbound base address0 */
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void __iomem *mem_base0;
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