sfc: Implement ethtool register dump operation
Signed-off-by: Ben Hutchings <bhutchings@solarflare.com> Acked-by: Jeff Garzik <jgarzik@redhat.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Ben Hutchings
David S. Miller
parent
565b7b2d2e
commit
5b98c1bfcf
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@ -242,6 +242,20 @@ static void efx_ethtool_get_drvinfo(struct net_device *net_dev,
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strlcpy(info->bus_info, pci_name(efx->pci_dev), sizeof(info->bus_info));
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}
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static int efx_ethtool_get_regs_len(struct net_device *net_dev)
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{
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return efx_nic_get_regs_len(netdev_priv(net_dev));
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}
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static void efx_ethtool_get_regs(struct net_device *net_dev,
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struct ethtool_regs *regs, void *buf)
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{
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struct efx_nic *efx = netdev_priv(net_dev);
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regs->version = efx->type->revision;
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efx_nic_get_regs(efx, buf);
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}
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/**
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* efx_fill_test - fill in an individual self-test entry
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* @test_index: Index of the test
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@ -834,6 +848,8 @@ const struct ethtool_ops efx_ethtool_ops = {
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.get_settings = efx_ethtool_get_settings,
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.set_settings = efx_ethtool_set_settings,
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.get_drvinfo = efx_ethtool_get_drvinfo,
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.get_regs_len = efx_ethtool_get_regs_len,
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.get_regs = efx_ethtool_get_regs,
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.nway_reset = efx_ethtool_nway_reset,
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.get_link = efx_ethtool_get_link,
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.get_eeprom_len = efx_ethtool_get_eeprom_len,
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@ -211,6 +211,13 @@ static inline void efx_writed_table(struct efx_nic *efx, efx_dword_t *value,
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efx_writed(efx, value, reg + index * sizeof(efx_oword_t));
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}
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/* Read from a dword register forming part of a table */
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static inline void efx_readd_table(struct efx_nic *efx, efx_dword_t *value,
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unsigned int reg, unsigned int index)
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{
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efx_readd(efx, value, reg + index * sizeof(efx_dword_t));
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}
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/* Page-mapped register block size */
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#define EFX_PAGE_BLOCK_SIZE 0x2000
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@ -1627,3 +1627,269 @@ void efx_nic_init_common(struct efx_nic *efx)
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EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
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efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
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}
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/* Register dump */
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#define REGISTER_REVISION_A 1
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#define REGISTER_REVISION_B 2
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#define REGISTER_REVISION_C 3
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#define REGISTER_REVISION_Z 3 /* latest revision */
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struct efx_nic_reg {
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u32 offset:24;
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u32 min_revision:2, max_revision:2;
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};
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#define REGISTER(name, min_rev, max_rev) { \
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FR_ ## min_rev ## max_rev ## _ ## name, \
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REGISTER_REVISION_ ## min_rev, REGISTER_REVISION_ ## max_rev \
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}
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#define REGISTER_AA(name) REGISTER(name, A, A)
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#define REGISTER_AB(name) REGISTER(name, A, B)
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#define REGISTER_AZ(name) REGISTER(name, A, Z)
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#define REGISTER_BB(name) REGISTER(name, B, B)
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#define REGISTER_BZ(name) REGISTER(name, B, Z)
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#define REGISTER_CZ(name) REGISTER(name, C, Z)
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static const struct efx_nic_reg efx_nic_regs[] = {
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REGISTER_AZ(ADR_REGION),
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REGISTER_AZ(INT_EN_KER),
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REGISTER_BZ(INT_EN_CHAR),
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REGISTER_AZ(INT_ADR_KER),
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REGISTER_BZ(INT_ADR_CHAR),
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/* INT_ACK_KER is WO */
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/* INT_ISR0 is RC */
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REGISTER_AZ(HW_INIT),
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REGISTER_CZ(USR_EV_CFG),
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REGISTER_AB(EE_SPI_HCMD),
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REGISTER_AB(EE_SPI_HADR),
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REGISTER_AB(EE_SPI_HDATA),
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REGISTER_AB(EE_BASE_PAGE),
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REGISTER_AB(EE_VPD_CFG0),
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/* EE_VPD_SW_CNTL and EE_VPD_SW_DATA are not used */
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/* PMBX_DBG_IADDR and PBMX_DBG_IDATA are indirect */
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/* PCIE_CORE_INDIRECT is indirect */
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REGISTER_AB(NIC_STAT),
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REGISTER_AB(GPIO_CTL),
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REGISTER_AB(GLB_CTL),
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/* FATAL_INTR_KER and FATAL_INTR_CHAR are partly RC */
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REGISTER_BZ(DP_CTRL),
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REGISTER_AZ(MEM_STAT),
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REGISTER_AZ(CS_DEBUG),
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REGISTER_AZ(ALTERA_BUILD),
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REGISTER_AZ(CSR_SPARE),
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REGISTER_AB(PCIE_SD_CTL0123),
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REGISTER_AB(PCIE_SD_CTL45),
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REGISTER_AB(PCIE_PCS_CTL_STAT),
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/* DEBUG_DATA_OUT is not used */
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/* DRV_EV is WO */
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REGISTER_AZ(EVQ_CTL),
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REGISTER_AZ(EVQ_CNT1),
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REGISTER_AZ(EVQ_CNT2),
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REGISTER_AZ(BUF_TBL_CFG),
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REGISTER_AZ(SRM_RX_DC_CFG),
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REGISTER_AZ(SRM_TX_DC_CFG),
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REGISTER_AZ(SRM_CFG),
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/* BUF_TBL_UPD is WO */
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REGISTER_AZ(SRM_UPD_EVQ),
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REGISTER_AZ(SRAM_PARITY),
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REGISTER_AZ(RX_CFG),
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REGISTER_BZ(RX_FILTER_CTL),
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/* RX_FLUSH_DESCQ is WO */
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REGISTER_AZ(RX_DC_CFG),
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REGISTER_AZ(RX_DC_PF_WM),
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REGISTER_BZ(RX_RSS_TKEY),
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/* RX_NODESC_DROP is RC */
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REGISTER_AA(RX_SELF_RST),
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/* RX_DEBUG, RX_PUSH_DROP are not used */
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REGISTER_CZ(RX_RSS_IPV6_REG1),
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REGISTER_CZ(RX_RSS_IPV6_REG2),
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REGISTER_CZ(RX_RSS_IPV6_REG3),
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/* TX_FLUSH_DESCQ is WO */
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REGISTER_AZ(TX_DC_CFG),
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REGISTER_AA(TX_CHKSM_CFG),
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REGISTER_AZ(TX_CFG),
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/* TX_PUSH_DROP is not used */
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REGISTER_AZ(TX_RESERVED),
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REGISTER_BZ(TX_PACE),
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/* TX_PACE_DROP_QID is RC */
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REGISTER_BB(TX_VLAN),
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REGISTER_BZ(TX_IPFIL_PORTEN),
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REGISTER_AB(MD_TXD),
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REGISTER_AB(MD_RXD),
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REGISTER_AB(MD_CS),
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REGISTER_AB(MD_PHY_ADR),
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REGISTER_AB(MD_ID),
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/* MD_STAT is RC */
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REGISTER_AB(MAC_STAT_DMA),
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REGISTER_AB(MAC_CTRL),
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REGISTER_BB(GEN_MODE),
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REGISTER_AB(MAC_MC_HASH_REG0),
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REGISTER_AB(MAC_MC_HASH_REG1),
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REGISTER_AB(GM_CFG1),
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REGISTER_AB(GM_CFG2),
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/* GM_IPG and GM_HD are not used */
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REGISTER_AB(GM_MAX_FLEN),
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/* GM_TEST is not used */
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REGISTER_AB(GM_ADR1),
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REGISTER_AB(GM_ADR2),
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REGISTER_AB(GMF_CFG0),
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REGISTER_AB(GMF_CFG1),
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REGISTER_AB(GMF_CFG2),
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REGISTER_AB(GMF_CFG3),
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REGISTER_AB(GMF_CFG4),
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REGISTER_AB(GMF_CFG5),
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REGISTER_BB(TX_SRC_MAC_CTL),
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REGISTER_AB(XM_ADR_LO),
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REGISTER_AB(XM_ADR_HI),
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REGISTER_AB(XM_GLB_CFG),
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REGISTER_AB(XM_TX_CFG),
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REGISTER_AB(XM_RX_CFG),
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REGISTER_AB(XM_MGT_INT_MASK),
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REGISTER_AB(XM_FC),
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REGISTER_AB(XM_PAUSE_TIME),
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REGISTER_AB(XM_TX_PARAM),
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REGISTER_AB(XM_RX_PARAM),
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/* XM_MGT_INT_MSK (note no 'A') is RC */
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REGISTER_AB(XX_PWR_RST),
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REGISTER_AB(XX_SD_CTL),
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REGISTER_AB(XX_TXDRV_CTL),
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/* XX_PRBS_CTL, XX_PRBS_CHK and XX_PRBS_ERR are not used */
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/* XX_CORE_STAT is partly RC */
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};
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struct efx_nic_reg_table {
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u32 offset:24;
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u32 min_revision:2, max_revision:2;
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u32 step:6, rows:21;
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};
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#define REGISTER_TABLE_DIMENSIONS(_, offset, min_rev, max_rev, step, rows) { \
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offset, \
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REGISTER_REVISION_ ## min_rev, REGISTER_REVISION_ ## max_rev, \
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step, rows \
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}
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#define REGISTER_TABLE(name, min_rev, max_rev) \
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REGISTER_TABLE_DIMENSIONS( \
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name, FR_ ## min_rev ## max_rev ## _ ## name, \
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min_rev, max_rev, \
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FR_ ## min_rev ## max_rev ## _ ## name ## _STEP, \
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FR_ ## min_rev ## max_rev ## _ ## name ## _ROWS)
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#define REGISTER_TABLE_AA(name) REGISTER_TABLE(name, A, A)
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#define REGISTER_TABLE_AZ(name) REGISTER_TABLE(name, A, Z)
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#define REGISTER_TABLE_BB(name) REGISTER_TABLE(name, B, B)
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#define REGISTER_TABLE_BZ(name) REGISTER_TABLE(name, B, Z)
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#define REGISTER_TABLE_BB_CZ(name) \
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REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, B, B, \
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FR_BZ_ ## name ## _STEP, \
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FR_BB_ ## name ## _ROWS), \
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REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, C, Z, \
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FR_BZ_ ## name ## _STEP, \
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FR_CZ_ ## name ## _ROWS)
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#define REGISTER_TABLE_CZ(name) REGISTER_TABLE(name, C, Z)
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static const struct efx_nic_reg_table efx_nic_reg_tables[] = {
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/* DRIVER is not used */
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/* EVQ_RPTR, TIMER_COMMAND, USR_EV and {RX,TX}_DESC_UPD are WO */
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REGISTER_TABLE_BB(TX_IPFIL_TBL),
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REGISTER_TABLE_BB(TX_SRC_MAC_TBL),
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REGISTER_TABLE_AA(RX_DESC_PTR_TBL_KER),
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REGISTER_TABLE_BB_CZ(RX_DESC_PTR_TBL),
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REGISTER_TABLE_AA(TX_DESC_PTR_TBL_KER),
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REGISTER_TABLE_BB_CZ(TX_DESC_PTR_TBL),
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REGISTER_TABLE_AA(EVQ_PTR_TBL_KER),
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REGISTER_TABLE_BB_CZ(EVQ_PTR_TBL),
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/* The register buffer is allocated with slab, so we can't
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* reasonably read all of the buffer table (up to 8MB!).
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* However this driver will only use a few entries. Reading
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* 1K entries allows for some expansion of queue count and
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* size before we need to change the version. */
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REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL_KER, FR_AA_BUF_FULL_TBL_KER,
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A, A, 8, 1024),
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REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL, FR_BZ_BUF_FULL_TBL,
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B, Z, 8, 1024),
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/* RX_FILTER_TBL{0,1} is huge and not used by this driver */
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REGISTER_TABLE_CZ(RX_MAC_FILTER_TBL0),
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REGISTER_TABLE_BB_CZ(TIMER_TBL),
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REGISTER_TABLE_BB_CZ(TX_PACE_TBL),
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REGISTER_TABLE_BZ(RX_INDIRECTION_TBL),
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/* TX_FILTER_TBL0 is huge and not used by this driver */
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REGISTER_TABLE_CZ(TX_MAC_FILTER_TBL0),
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REGISTER_TABLE_CZ(MC_TREG_SMEM),
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/* MSIX_PBA_TABLE is not mapped */
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/* SRM_DBG is not mapped (and is redundant with BUF_FLL_TBL) */
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};
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size_t efx_nic_get_regs_len(struct efx_nic *efx)
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{
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const struct efx_nic_reg *reg;
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const struct efx_nic_reg_table *table;
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size_t len = 0;
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for (reg = efx_nic_regs;
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reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs);
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reg++)
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if (efx->type->revision >= reg->min_revision &&
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efx->type->revision <= reg->max_revision)
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len += sizeof(efx_oword_t);
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for (table = efx_nic_reg_tables;
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table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables);
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table++)
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if (efx->type->revision >= table->min_revision &&
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efx->type->revision <= table->max_revision)
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len += table->rows * min_t(size_t, table->step, 16);
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return len;
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}
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void efx_nic_get_regs(struct efx_nic *efx, void *buf)
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{
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const struct efx_nic_reg *reg;
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const struct efx_nic_reg_table *table;
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for (reg = efx_nic_regs;
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reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs);
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reg++) {
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if (efx->type->revision >= reg->min_revision &&
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efx->type->revision <= reg->max_revision) {
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efx_reado(efx, (efx_oword_t *)buf, reg->offset);
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buf += sizeof(efx_oword_t);
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}
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}
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for (table = efx_nic_reg_tables;
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table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables);
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table++) {
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size_t size, i;
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if (!(efx->type->revision >= table->min_revision &&
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efx->type->revision <= table->max_revision))
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continue;
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size = min_t(size_t, table->step, 16);
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for (i = 0; i < table->rows; i++) {
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switch (table->step) {
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case 4: /* 32-bit register or SRAM */
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efx_readd_table(efx, buf, table->offset, i);
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break;
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case 8: /* 64-bit SRAM */
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efx_sram_readq(efx,
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efx->membase + table->offset,
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buf, i);
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break;
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case 16: /* 128-bit register */
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efx_reado_table(efx, buf, table->offset, i);
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break;
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case 32: /* 128-bit register, interleaved */
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efx_reado_table(efx, buf, table->offset, 2 * i);
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break;
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default:
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WARN_ON(1);
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return;
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}
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buf += size;
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}
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}
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}
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@ -222,6 +222,9 @@ extern int efx_nic_test_registers(struct efx_nic *efx,
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const struct efx_nic_register_test *regs,
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size_t n_regs);
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extern size_t efx_nic_get_regs_len(struct efx_nic *efx);
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extern void efx_nic_get_regs(struct efx_nic *efx, void *buf);
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/**************************************************************************
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*
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* Falcon MAC stats
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