ASoC: fsl_esai: Wrap some operations to be functions
Extract the operation to be functions, to improve the readability. In this patch, fsl_esai_hw_init, fsl_esai_register_restore, fsl_esai_trigger_start and fsl_esai_trigger_stop are extracted. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/804d7e75ae7e06a913479912b578b3538ca7cd3f.1562842206.git.shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>alistair/sunxi64-5.4-dsi
Shengjiu Wang
Mark Brown
parent
4dc057a786
commit
5be6155b50
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@ -35,6 +35,7 @@
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* @fifo_depth: depth of tx/rx FIFO
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* @slot_width: width of each DAI slot
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* @slots: number of slots
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* @channels: channel num for tx or rx
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* @hck_rate: clock rate of desired HCKx clock
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* @sck_rate: clock rate of desired SCKx clock
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* @hck_dir: the direction of HCKx pads
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@ -57,6 +58,7 @@ struct fsl_esai {
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u32 slots;
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u32 tx_mask;
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u32 rx_mask;
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u32 channels[2];
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u32 hck_rate[2];
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u32 sck_rate[2];
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bool hck_dir[2];
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@ -543,64 +545,132 @@ static int fsl_esai_hw_params(struct snd_pcm_substream *substream,
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return 0;
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}
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static int fsl_esai_hw_init(struct fsl_esai *esai_priv)
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{
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struct platform_device *pdev = esai_priv->pdev;
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int ret;
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/* Reset ESAI unit */
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ret = regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR,
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ESAI_ECR_ESAIEN_MASK | ESAI_ECR_ERST_MASK,
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ESAI_ECR_ESAIEN | ESAI_ECR_ERST);
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if (ret) {
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dev_err(&pdev->dev, "failed to reset ESAI: %d\n", ret);
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return ret;
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}
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/*
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* We need to enable ESAI so as to access some of its registers.
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* Otherwise, we would fail to dump regmap from user space.
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*/
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ret = regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR,
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ESAI_ECR_ESAIEN_MASK | ESAI_ECR_ERST_MASK,
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ESAI_ECR_ESAIEN);
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if (ret) {
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dev_err(&pdev->dev, "failed to enable ESAI: %d\n", ret);
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return ret;
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}
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regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC,
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ESAI_PRRC_PDC_MASK, 0);
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regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC,
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ESAI_PCRC_PC_MASK, 0);
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return 0;
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}
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static int fsl_esai_register_restore(struct fsl_esai *esai_priv)
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{
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int ret;
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/* FIFO reset for safety */
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regmap_update_bits(esai_priv->regmap, REG_ESAI_TFCR,
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ESAI_xFCR_xFR, ESAI_xFCR_xFR);
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regmap_update_bits(esai_priv->regmap, REG_ESAI_RFCR,
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ESAI_xFCR_xFR, ESAI_xFCR_xFR);
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regcache_mark_dirty(esai_priv->regmap);
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ret = regcache_sync(esai_priv->regmap);
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if (ret)
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return ret;
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/* FIFO reset done */
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regmap_update_bits(esai_priv->regmap, REG_ESAI_TFCR, ESAI_xFCR_xFR, 0);
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regmap_update_bits(esai_priv->regmap, REG_ESAI_RFCR, ESAI_xFCR_xFR, 0);
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return 0;
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}
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static void fsl_esai_trigger_start(struct fsl_esai *esai_priv, bool tx)
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{
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u8 i, channels = esai_priv->channels[tx];
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u32 pins = DIV_ROUND_UP(channels, esai_priv->slots);
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u32 mask;
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regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
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ESAI_xFCR_xFEN_MASK, ESAI_xFCR_xFEN);
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/* Write initial words reqiured by ESAI as normal procedure */
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for (i = 0; tx && i < channels; i++)
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regmap_write(esai_priv->regmap, REG_ESAI_ETDR, 0x0);
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/*
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* When set the TE/RE in the end of enablement flow, there
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* will be channel swap issue for multi data line case.
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* In order to workaround this issue, we switch the bit
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* enablement sequence to below sequence
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* 1) clear the xSMB & xSMA: which is done in probe and
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* stop state.
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* 2) set TE/RE
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* 3) set xSMB
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* 4) set xSMA: xSMA is the last one in this flow, which
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* will trigger esai to start.
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*/
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regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
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tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK,
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tx ? ESAI_xCR_TE(pins) : ESAI_xCR_RE(pins));
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mask = tx ? esai_priv->tx_mask : esai_priv->rx_mask;
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regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx),
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ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(mask));
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regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx),
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ESAI_xSMA_xS_MASK, ESAI_xSMA_xS(mask));
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}
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static void fsl_esai_trigger_stop(struct fsl_esai *esai_priv, bool tx)
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{
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regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
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tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK, 0);
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regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx),
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ESAI_xSMA_xS_MASK, 0);
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regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx),
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ESAI_xSMB_xS_MASK, 0);
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/* Disable and reset FIFO */
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regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
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ESAI_xFCR_xFR | ESAI_xFCR_xFEN, ESAI_xFCR_xFR);
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regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
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ESAI_xFCR_xFR, 0);
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}
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static int fsl_esai_trigger(struct snd_pcm_substream *substream, int cmd,
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struct snd_soc_dai *dai)
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{
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struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
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bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
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u8 i, channels = substream->runtime->channels;
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u32 pins = DIV_ROUND_UP(channels, esai_priv->slots);
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u32 mask;
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esai_priv->channels[tx] = substream->runtime->channels;
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
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ESAI_xFCR_xFEN_MASK, ESAI_xFCR_xFEN);
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/* Write initial words reqiured by ESAI as normal procedure */
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for (i = 0; tx && i < channels; i++)
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regmap_write(esai_priv->regmap, REG_ESAI_ETDR, 0x0);
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/*
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* When set the TE/RE in the end of enablement flow, there
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* will be channel swap issue for multi data line case.
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* In order to workaround this issue, we switch the bit
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* enablement sequence to below sequence
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* 1) clear the xSMB & xSMA: which is done in probe and
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* stop state.
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* 2) set TE/RE
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* 3) set xSMB
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* 4) set xSMA: xSMA is the last one in this flow, which
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* will trigger esai to start.
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*/
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regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
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tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK,
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tx ? ESAI_xCR_TE(pins) : ESAI_xCR_RE(pins));
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mask = tx ? esai_priv->tx_mask : esai_priv->rx_mask;
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regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx),
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ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(mask));
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regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx),
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ESAI_xSMA_xS_MASK, ESAI_xSMA_xS(mask));
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fsl_esai_trigger_start(esai_priv, tx);
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break;
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case SNDRV_PCM_TRIGGER_SUSPEND:
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
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tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK, 0);
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regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx),
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ESAI_xSMA_xS_MASK, 0);
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regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx),
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ESAI_xSMB_xS_MASK, 0);
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/* Disable and reset FIFO */
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regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
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ESAI_xFCR_xFR | ESAI_xFCR_xFEN, ESAI_xFCR_xFR);
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regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
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ESAI_xFCR_xFR, 0);
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fsl_esai_trigger_stop(esai_priv, tx);
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break;
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default:
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return -EINVAL;
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@ -866,22 +936,9 @@ static int fsl_esai_probe(struct platform_device *pdev)
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dev_set_drvdata(&pdev->dev, esai_priv);
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/* Reset ESAI unit */
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ret = regmap_write(esai_priv->regmap, REG_ESAI_ECR, ESAI_ECR_ERST);
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if (ret) {
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dev_err(&pdev->dev, "failed to reset ESAI: %d\n", ret);
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ret = fsl_esai_hw_init(esai_priv);
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if (ret)
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return ret;
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}
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/*
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* We need to enable ESAI so as to access some of its registers.
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* Otherwise, we would fail to dump regmap from user space.
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*/
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ret = regmap_write(esai_priv->regmap, REG_ESAI_ECR, ESAI_ECR_ESAIEN);
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if (ret) {
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dev_err(&pdev->dev, "failed to enable ESAI: %d\n", ret);
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return ret;
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}
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esai_priv->tx_mask = 0xFFFFFFFF;
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esai_priv->rx_mask = 0xFFFFFFFF;
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@ -955,20 +1012,10 @@ static int fsl_esai_runtime_resume(struct device *dev)
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regcache_cache_only(esai->regmap, false);
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/* FIFO reset for safety */
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regmap_update_bits(esai->regmap, REG_ESAI_TFCR,
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ESAI_xFCR_xFR, ESAI_xFCR_xFR);
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regmap_update_bits(esai->regmap, REG_ESAI_RFCR,
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ESAI_xFCR_xFR, ESAI_xFCR_xFR);
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ret = regcache_sync(esai->regmap);
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ret = fsl_esai_register_restore(esai);
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if (ret)
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goto err_regcache_sync;
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/* FIFO reset done */
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regmap_update_bits(esai->regmap, REG_ESAI_TFCR, ESAI_xFCR_xFR, 0);
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regmap_update_bits(esai->regmap, REG_ESAI_RFCR, ESAI_xFCR_xFR, 0);
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return 0;
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err_regcache_sync:
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@ -991,7 +1038,6 @@ static int fsl_esai_runtime_suspend(struct device *dev)
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struct fsl_esai *esai = dev_get_drvdata(dev);
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regcache_cache_only(esai->regmap, true);
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regcache_mark_dirty(esai->regmap);
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if (!IS_ERR(esai->fsysclk))
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clk_disable_unprepare(esai->fsysclk);
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