au1xmmc: codingstyle tidying.
Clean up the codebase, no functional changes. - merge the au1xmmc.h header contents into the driver file, - indentation, spelling and style fixes. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
This commit is contained in:
Manuel Lauss
Pierre Ossman
parent
20f522ff55
commit
5c0a889df5
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@ -49,20 +49,104 @@
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#include <asm/mach-au1x00/au1xxx_dbdma.h>
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#include <asm/mach-au1x00/au1100_mmc.h>
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#include <au1xxx.h>
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#include "au1xmmc.h"
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#define DRIVER_NAME "au1xxx-mmc"
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/* Set this to enable special debugging macros */
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/* #define DEBUG */
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#ifdef DEBUG
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#define DBG(fmt, idx, args...) printk("au1xx(%d): DEBUG: " fmt, idx, ##args)
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#define DBG(fmt, idx, args...) \
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printk(KERN_DEBUG "au1xmmc(%d): DEBUG: " fmt, idx, ##args)
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#else
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#define DBG(fmt, idx, args...)
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#define DBG(fmt, idx, args...) do {} while (0)
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#endif
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/* Hardware definitions */
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#define AU1XMMC_DESCRIPTOR_COUNT 1
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#define AU1XMMC_DESCRIPTOR_SIZE 2048
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#define AU1XMMC_OCR (MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | \
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MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 | \
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MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36)
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/* This gives us a hard value for the stop command that we can write directly
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* to the command register.
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*/
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#define STOP_CMD \
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(SD_CMD_RT_1B | SD_CMD_CT_7 | (0xC << SD_CMD_CI_SHIFT) | SD_CMD_GO)
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/* This is the set of interrupts that we configure by default. */
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#define AU1XMMC_INTERRUPTS \
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(SD_CONFIG_SC | SD_CONFIG_DT | SD_CONFIG_RAT | \
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SD_CONFIG_CR | SD_CONFIG_I)
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/* The poll event (looking for insert/remove events runs twice a second. */
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#define AU1XMMC_DETECT_TIMEOUT (HZ/2)
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struct au1xmmc_host {
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struct mmc_host *mmc;
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struct mmc_request *mrq;
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u32 flags;
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u32 iobase;
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u32 clock;
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u32 bus_width;
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u32 power_mode;
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int status;
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struct {
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int len;
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int dir;
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} dma;
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struct {
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int index;
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int offset;
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int len;
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} pio;
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u32 tx_chan;
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u32 rx_chan;
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int irq;
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struct timer_list timer;
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struct tasklet_struct finish_task;
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struct tasklet_struct data_task;
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struct au1xmmc_platform_data *platdata;
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struct platform_device *pdev;
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struct resource *ioarea;
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};
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/* Status flags used by the host structure */
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#define HOST_F_XMIT 0x0001
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#define HOST_F_RECV 0x0002
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#define HOST_F_DMA 0x0010
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#define HOST_F_ACTIVE 0x0100
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#define HOST_F_STOP 0x1000
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#define HOST_S_IDLE 0x0001
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#define HOST_S_CMD 0x0002
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#define HOST_S_DATA 0x0003
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#define HOST_S_STOP 0x0004
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/* Easy access macros */
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#define HOST_STATUS(h) ((h)->iobase + SD_STATUS)
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#define HOST_CONFIG(h) ((h)->iobase + SD_CONFIG)
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#define HOST_ENABLE(h) ((h)->iobase + SD_ENABLE)
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#define HOST_TXPORT(h) ((h)->iobase + SD_TXPORT)
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#define HOST_RXPORT(h) ((h)->iobase + SD_RXPORT)
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#define HOST_CMDARG(h) ((h)->iobase + SD_CMDARG)
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#define HOST_BLKSIZE(h) ((h)->iobase + SD_BLKSIZE)
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#define HOST_CMD(h) ((h)->iobase + SD_CMD)
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#define HOST_CONFIG2(h) ((h)->iobase + SD_CONFIG2)
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#define HOST_TIMEOUT(h) ((h)->iobase + SD_TIMEOUT)
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#define HOST_DEBUG(h) ((h)->iobase + SD_DEBUG)
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#define DMA_CHANNEL(h) \
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(((h)->flags & HOST_F_XMIT) ? (h)->tx_chan : (h)->rx_chan)
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static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask)
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{
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u32 val = au_readl(HOST_CONFIG(host));
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@ -141,7 +225,6 @@ static int au1xmmc_card_readonly(struct mmc_host *mmc)
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static void au1xmmc_finish_request(struct au1xmmc_host *host)
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{
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struct mmc_request *mrq = host->mrq;
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host->mrq = NULL;
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@ -215,18 +298,14 @@ static int au1xmmc_send_command(struct au1xmmc_host *host, int wait,
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au_sync();
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/* Wait for the command to go on the line */
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while(1) {
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if (!(au_readl(HOST_CMD(host)) & SD_CMD_GO))
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break;
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}
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while (au_readl(HOST_CMD(host)) & SD_CMD_GO)
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/* nop */;
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/* Wait for the command to come back */
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if (wait) {
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u32 status = au_readl(HOST_STATUS(host));
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while(!(status & SD_STATUS_CR))
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while (!(status & SD_STATUS_CR))
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status = au_readl(HOST_STATUS(host));
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/* Clear the CR status */
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@ -240,12 +319,11 @@ static int au1xmmc_send_command(struct au1xmmc_host *host, int wait,
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static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status)
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{
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struct mmc_request *mrq = host->mrq;
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struct mmc_data *data;
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u32 crc;
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WARN_ON(host->status != HOST_S_DATA && host->status != HOST_S_STOP);
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WARN_ON((host->status != HOST_S_DATA) && (host->status != HOST_S_STOP));
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if (host->mrq == NULL)
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return;
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@ -256,15 +334,13 @@ static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status)
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status = au_readl(HOST_STATUS(host));
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/* The transaction is really over when the SD_STATUS_DB bit is clear */
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while((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB))
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while ((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB))
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status = au_readl(HOST_STATUS(host));
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data->error = 0;
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dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir);
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/* Process any errors */
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crc = (status & (SD_STATUS_WC | SD_STATUS_RC));
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if (host->flags & HOST_F_XMIT)
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crc |= ((status & 0x07) == 0x02) ? 0 : 1;
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@ -282,15 +358,13 @@ static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status)
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#ifdef CONFIG_SOC_AU1200 /* DBDMA */
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u32 chan = DMA_CHANNEL(host);
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chan_tab_t *c = *((chan_tab_t **) chan);
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chan_tab_t *c = *((chan_tab_t **)chan);
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au1x_dma_chan_t *cp = c->chan_ptr;
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data->bytes_xfered = cp->ddma_bytecnt;
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#endif
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}
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else
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} else
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data->bytes_xfered =
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(data->blocks * data->blksz) -
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host->pio.len;
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(data->blocks * data->blksz) - host->pio.len;
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}
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au1xmmc_finish_request(host);
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@ -298,7 +372,7 @@ static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status)
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static void au1xmmc_tasklet_data(unsigned long param)
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{
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struct au1xmmc_host *host = (struct au1xmmc_host *) param;
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struct au1xmmc_host *host = (struct au1xmmc_host *)param;
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u32 status = au_readl(HOST_STATUS(host));
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au1xmmc_data_complete(host, status);
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@ -308,11 +382,10 @@ static void au1xmmc_tasklet_data(unsigned long param)
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static void au1xmmc_send_pio(struct au1xmmc_host *host)
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{
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struct mmc_data *data = 0;
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int sg_len, max, count = 0;
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unsigned char *sg_ptr;
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u32 status = 0;
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struct mmc_data *data;
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int sg_len, max, count;
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unsigned char *sg_ptr, val;
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u32 status;
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struct scatterlist *sg;
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data = host->mrq->data;
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@ -327,14 +400,12 @@ static void au1xmmc_send_pio(struct au1xmmc_host *host)
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/* This is the space left inside the buffer */
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sg_len = data->sg[host->pio.index].length - host->pio.offset;
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/* Check to if we need less then the size of the sg_buffer */
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/* Check if we need less than the size of the sg_buffer */
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max = (sg_len > host->pio.len) ? host->pio.len : sg_len;
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if (max > AU1XMMC_MAX_TRANSFER) max = AU1XMMC_MAX_TRANSFER;
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for(count = 0; count < max; count++ ) {
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unsigned char val;
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if (max > AU1XMMC_MAX_TRANSFER)
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max = AU1XMMC_MAX_TRANSFER;
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for (count = 0; count < max; count++) {
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status = au_readl(HOST_STATUS(host));
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if (!(status & SD_STATUS_TH))
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@ -342,7 +413,7 @@ static void au1xmmc_send_pio(struct au1xmmc_host *host)
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val = *sg_ptr++;
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au_writel((unsigned long) val, HOST_TXPORT(host));
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au_writel((unsigned long)val, HOST_TXPORT(host));
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au_sync();
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}
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@ -366,11 +437,10 @@ static void au1xmmc_send_pio(struct au1xmmc_host *host)
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static void au1xmmc_receive_pio(struct au1xmmc_host *host)
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{
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struct mmc_data *data = 0;
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int sg_len = 0, max = 0, count = 0;
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unsigned char *sg_ptr = 0;
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u32 status = 0;
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struct mmc_data *data;
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int max, count, sg_len = 0;
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unsigned char *sg_ptr = NULL;
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u32 status, val;
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struct scatterlist *sg;
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data = host->mrq->data;
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@ -387,15 +457,15 @@ static void au1xmmc_receive_pio(struct au1xmmc_host *host)
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/* This is the space left inside the buffer */
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sg_len = sg_dma_len(&data->sg[host->pio.index]) - host->pio.offset;
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/* Check to if we need less then the size of the sg_buffer */
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if (sg_len < max) max = sg_len;
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/* Check if we need less than the size of the sg_buffer */
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if (sg_len < max)
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max = sg_len;
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}
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if (max > AU1XMMC_MAX_TRANSFER)
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max = AU1XMMC_MAX_TRANSFER;
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for(count = 0; count < max; count++ ) {
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u32 val;
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for (count = 0; count < max; count++) {
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status = au_readl(HOST_STATUS(host));
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if (!(status & SD_STATUS_NE))
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@ -421,7 +491,7 @@ static void au1xmmc_receive_pio(struct au1xmmc_host *host)
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val = au_readl(HOST_RXPORT(host));
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if (sg_ptr)
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*sg_ptr++ = (unsigned char) (val & 0xFF);
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*sg_ptr++ = (unsigned char)(val & 0xFF);
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}
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host->pio.len -= count;
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@ -433,7 +503,7 @@ static void au1xmmc_receive_pio(struct au1xmmc_host *host)
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}
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if (host->pio.len == 0) {
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//IRQ_OFF(host, SD_CONFIG_RA | SD_CONFIG_RF);
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/* IRQ_OFF(host, SD_CONFIG_RA | SD_CONFIG_RF); */
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IRQ_OFF(host, SD_CONFIG_NE);
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if (host->flags & HOST_F_STOP)
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@ -443,17 +513,15 @@ static void au1xmmc_receive_pio(struct au1xmmc_host *host)
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}
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}
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/* static void au1xmmc_cmd_complete
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This is called when a command has been completed - grab the response
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and check for errors. Then start the data transfer if it is indicated.
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*/
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/* This is called when a command has been completed - grab the response
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* and check for errors. Then start the data transfer if it is indicated.
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*/
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static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status)
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{
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struct mmc_request *mrq = host->mrq;
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struct mmc_command *cmd;
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int trans;
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u32 r[4];
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int i, trans;
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if (!host->mrq)
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return;
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@ -463,9 +531,6 @@ static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status)
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if (cmd->flags & MMC_RSP_PRESENT) {
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if (cmd->flags & MMC_RSP_136) {
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u32 r[4];
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int i;
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r[0] = au_readl(host->iobase + SD_RESP3);
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r[1] = au_readl(host->iobase + SD_RESP2);
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r[2] = au_readl(host->iobase + SD_RESP1);
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@ -473,10 +538,9 @@ static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status)
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/* The CRC is omitted from the response, so really
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* we only got 120 bytes, but the engine expects
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* 128 bits, so we have to shift things up
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* 128 bits, so we have to shift things up.
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*/
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for(i = 0; i < 4; i++) {
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for (i = 0; i < 4; i++) {
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cmd->resp[i] = (r[i] & 0x00FFFFFF) << 8;
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if (i != 3)
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cmd->resp[i] |= (r[i + 1] & 0xFF000000) >> 24;
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@ -487,22 +551,20 @@ static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status)
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* our response omits the CRC, our data ends up
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* being shifted 8 bits to the right. In this case,
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* that means that the OSR data starts at bit 31,
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* so we can just read RESP0 and return that
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* so we can just read RESP0 and return that.
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*/
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cmd->resp[0] = au_readl(host->iobase + SD_RESP0);
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}
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}
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/* Figure out errors */
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if (status & (SD_STATUS_SC | SD_STATUS_WC | SD_STATUS_RC))
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cmd->error = -EILSEQ;
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trans = host->flags & (HOST_F_XMIT | HOST_F_RECV);
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if (!trans || cmd->error) {
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IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA|SD_CONFIG_RF);
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IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF);
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tasklet_schedule(&host->finish_task);
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return;
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}
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@ -529,18 +591,15 @@ static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status)
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static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate)
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{
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unsigned int pbus = get_au1x00_speed();
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unsigned int divisor;
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u32 config;
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/* From databook:
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divisor = ((((cpuclock / sbus_divisor) / 2) / mmcclock) / 2) - 1
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*/
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* divisor = ((((cpuclock / sbus_divisor) / 2) / mmcclock) / 2) - 1
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*/
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pbus /= ((au_readl(SYS_POWERCTRL) & 0x3) + 2);
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pbus /= 2;
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divisor = ((pbus / rate) / 2) - 1;
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config = au_readl(HOST_CONFIG(host));
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@ -552,8 +611,8 @@ static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate)
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au_sync();
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}
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static int
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au1xmmc_prepare_data(struct au1xmmc_host *host, struct mmc_data *data)
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static int au1xmmc_prepare_data(struct au1xmmc_host *host,
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struct mmc_data *data)
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{
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int datalen = data->blocks * data->blksz;
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@ -582,7 +641,7 @@ au1xmmc_prepare_data(struct au1xmmc_host *host, struct mmc_data *data)
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au1xxx_dbdma_stop(channel);
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for(i = 0; i < host->dma.len; i++) {
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for (i = 0; i < host->dma.len; i++) {
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u32 ret = 0, flags = DDMA_FLAGS_NOIE;
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struct scatterlist *sg = &data->sg[i];
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int sg_len = sg->length;
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@ -592,14 +651,12 @@ au1xmmc_prepare_data(struct au1xmmc_host *host, struct mmc_data *data)
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if (i == host->dma.len - 1)
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flags = DDMA_FLAGS_IE;
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if (host->flags & HOST_F_XMIT){
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ret = au1xxx_dbdma_put_source_flags(channel,
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(void *) sg_virt(sg), len, flags);
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}
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else {
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ret = au1xxx_dbdma_put_dest_flags(channel,
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(void *) sg_virt(sg),
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len, flags);
|
||||
if (host->flags & HOST_F_XMIT) {
|
||||
ret = au1xxx_dbdma_put_source_flags(channel,
|
||||
(void *)sg_virt(sg), len, flags);
|
||||
} else {
|
||||
ret = au1xxx_dbdma_put_dest_flags(channel,
|
||||
(void *)sg_virt(sg), len, flags);
|
||||
}
|
||||
|
||||
if (!ret)
|
||||
|
|
@ -608,8 +665,7 @@ au1xmmc_prepare_data(struct au1xmmc_host *host, struct mmc_data *data)
|
|||
datalen -= len;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
else {
|
||||
} else {
|
||||
host->pio.index = 0;
|
||||
host->pio.offset = 0;
|
||||
host->pio.len = datalen;
|
||||
|
|
@ -618,7 +674,7 @@ au1xmmc_prepare_data(struct au1xmmc_host *host, struct mmc_data *data)
|
|||
IRQ_ON(host, SD_CONFIG_TH);
|
||||
else
|
||||
IRQ_ON(host, SD_CONFIG_NE);
|
||||
//IRQ_ON(host, SD_CONFIG_RA|SD_CONFIG_RF);
|
||||
/* IRQ_ON(host, SD_CONFIG_RA | SD_CONFIG_RF); */
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -629,15 +685,10 @@ dataerr:
|
|||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
/* static void au1xmmc_request
|
||||
This actually starts a command or data transaction
|
||||
*/
|
||||
|
||||
/* This actually starts a command or data transaction */
|
||||
static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq)
|
||||
{
|
||||
|
||||
struct au1xmmc_host *host = mmc_priv(mmc);
|
||||
unsigned int flags = 0;
|
||||
int ret = 0;
|
||||
|
||||
WARN_ON(irqs_disabled());
|
||||
|
|
@ -648,7 +699,6 @@ static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq)
|
|||
|
||||
if (mrq->data) {
|
||||
FLUSH_FIFO(host);
|
||||
flags = mrq->data->flags;
|
||||
ret = au1xmmc_prepare_data(host, mrq->data);
|
||||
}
|
||||
|
||||
|
|
@ -663,7 +713,6 @@ static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq)
|
|||
|
||||
static void au1xmmc_reset_controller(struct au1xmmc_host *host)
|
||||
{
|
||||
|
||||
/* Apply the clock */
|
||||
au_writel(SD_ENABLE_CE, HOST_ENABLE(host));
|
||||
au_sync_delay(1);
|
||||
|
|
@ -693,7 +742,7 @@ static void au1xmmc_reset_controller(struct au1xmmc_host *host)
|
|||
}
|
||||
|
||||
|
||||
static void au1xmmc_set_ios(struct mmc_host* mmc, struct mmc_ios* ios)
|
||||
static void au1xmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
|
||||
{
|
||||
struct au1xmmc_host *host = mmc_priv(mmc);
|
||||
u32 config2;
|
||||
|
|
|
|||
|
|
@ -1,97 +0,0 @@
|
|||
#ifndef _AU1XMMC_H_
|
||||
#define _AU1XMMC_H_
|
||||
|
||||
/* Hardware definitions */
|
||||
|
||||
#define AU1XMMC_DESCRIPTOR_COUNT 1
|
||||
#define AU1XMMC_DESCRIPTOR_SIZE 2048
|
||||
|
||||
#define AU1XMMC_OCR ( MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | \
|
||||
MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 | \
|
||||
MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36)
|
||||
|
||||
/* Easy access macros */
|
||||
|
||||
#define HOST_STATUS(h) ((h)->iobase + SD_STATUS)
|
||||
#define HOST_CONFIG(h) ((h)->iobase + SD_CONFIG)
|
||||
#define HOST_ENABLE(h) ((h)->iobase + SD_ENABLE)
|
||||
#define HOST_TXPORT(h) ((h)->iobase + SD_TXPORT)
|
||||
#define HOST_RXPORT(h) ((h)->iobase + SD_RXPORT)
|
||||
#define HOST_CMDARG(h) ((h)->iobase + SD_CMDARG)
|
||||
#define HOST_BLKSIZE(h) ((h)->iobase + SD_BLKSIZE)
|
||||
#define HOST_CMD(h) ((h)->iobase + SD_CMD)
|
||||
#define HOST_CONFIG2(h) ((h)->iobase + SD_CONFIG2)
|
||||
#define HOST_TIMEOUT(h) ((h)->iobase + SD_TIMEOUT)
|
||||
#define HOST_DEBUG(h) ((h)->iobase + SD_DEBUG)
|
||||
|
||||
#define DMA_CHANNEL(h) \
|
||||
( ((h)->flags & HOST_F_XMIT) ? (h)->tx_chan : (h)->rx_chan)
|
||||
|
||||
/* This gives us a hard value for the stop command that we can write directly
|
||||
* to the command register
|
||||
*/
|
||||
|
||||
#define STOP_CMD (SD_CMD_RT_1B|SD_CMD_CT_7|(0xC << SD_CMD_CI_SHIFT)|SD_CMD_GO)
|
||||
|
||||
/* This is the set of interrupts that we configure by default */
|
||||
|
||||
#if 0
|
||||
#define AU1XMMC_INTERRUPTS (SD_CONFIG_SC | SD_CONFIG_DT | SD_CONFIG_DD | \
|
||||
SD_CONFIG_RAT | SD_CONFIG_CR | SD_CONFIG_I)
|
||||
#endif
|
||||
|
||||
#define AU1XMMC_INTERRUPTS (SD_CONFIG_SC | SD_CONFIG_DT | \
|
||||
SD_CONFIG_RAT | SD_CONFIG_CR | SD_CONFIG_I)
|
||||
/* The poll event (looking for insert/remove events runs twice a second */
|
||||
#define AU1XMMC_DETECT_TIMEOUT (HZ/2)
|
||||
|
||||
struct au1xmmc_host {
|
||||
struct mmc_host *mmc;
|
||||
struct mmc_request *mrq;
|
||||
|
||||
u32 flags;
|
||||
u32 iobase;
|
||||
u32 clock;
|
||||
u32 bus_width;
|
||||
u32 power_mode;
|
||||
|
||||
int status;
|
||||
|
||||
struct {
|
||||
int len;
|
||||
int dir;
|
||||
} dma;
|
||||
|
||||
struct {
|
||||
int index;
|
||||
int offset;
|
||||
int len;
|
||||
} pio;
|
||||
|
||||
u32 tx_chan;
|
||||
u32 rx_chan;
|
||||
|
||||
int irq;
|
||||
|
||||
struct timer_list timer;
|
||||
struct tasklet_struct finish_task;
|
||||
struct tasklet_struct data_task;
|
||||
struct au1xmmc_platform_data *platdata;
|
||||
struct platform_device *pdev;
|
||||
struct resource *ioarea;
|
||||
};
|
||||
|
||||
/* Status flags used by the host structure */
|
||||
|
||||
#define HOST_F_XMIT 0x0001
|
||||
#define HOST_F_RECV 0x0002
|
||||
#define HOST_F_DMA 0x0010
|
||||
#define HOST_F_ACTIVE 0x0100
|
||||
#define HOST_F_STOP 0x1000
|
||||
|
||||
#define HOST_S_IDLE 0x0001
|
||||
#define HOST_S_CMD 0x0002
|
||||
#define HOST_S_DATA 0x0003
|
||||
#define HOST_S_STOP 0x0004
|
||||
|
||||
#endif
|
||||
Loading…
Reference in a new issue