ARM: tegra20: cpuidle: add powered-down state for secondary CPU
The powered-down state of Tegra20 requires power gating both CPU cores. When the secondary CPU requests to enter powered-down state, it saves its own contexts and then enters WFI. The Tegra20 had a limition to power down both CPU cores. The secondary CPU must waits for CPU0 in powered-down state too. If the secondary CPU be woken up before CPU0 entering powered-down state, then it needs to restore its CPU states and waits for next chance. Be aware of that, you may see the legacy power state "LP2" in the code which is exactly the same meaning of "CPU power down". Based on the work by: Colin Cross <ccross@android.com> Gary King <gking@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>hifive-unleashed-5.1
Joseph Lo
Stephen Warren
parent
d4b92fb253
commit
5c1350bdfc
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@ -22,21 +22,99 @@
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/cpuidle.h>
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#include <linux/cpu_pm.h>
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#include <linux/clockchips.h>
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#include <asm/cpuidle.h>
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#include <asm/proc-fns.h>
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#include <asm/suspend.h>
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#include <asm/smp_plat.h>
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#include "pm.h"
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#include "sleep.h"
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#ifdef CONFIG_PM_SLEEP
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static int tegra20_idle_lp2(struct cpuidle_device *dev,
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struct cpuidle_driver *drv,
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int index);
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#endif
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static struct cpuidle_state tegra_idle_states[] = {
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[0] = ARM_CPUIDLE_WFI_STATE_PWR(600),
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#ifdef CONFIG_PM_SLEEP
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[1] = {
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.enter = tegra20_idle_lp2,
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.exit_latency = 5000,
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.target_residency = 10000,
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.power_usage = 0,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.name = "powered-down",
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.desc = "CPU power gated",
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},
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#endif
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};
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static struct cpuidle_driver tegra_idle_driver = {
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.name = "tegra_idle",
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.owner = THIS_MODULE,
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.en_core_tk_irqen = 1,
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.state_count = 1,
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.states = {
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[0] = ARM_CPUIDLE_WFI_STATE_PWR(600),
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},
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};
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static DEFINE_PER_CPU(struct cpuidle_device, tegra_idle_device);
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#ifdef CONFIG_PM_SLEEP
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#ifdef CONFIG_SMP
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static bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev,
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struct cpuidle_driver *drv,
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int index)
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{
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clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
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cpu_suspend(0, tegra20_sleep_cpu_secondary_finish);
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tegra20_cpu_clear_resettable();
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clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
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return true;
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}
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#else
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static inline bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev,
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struct cpuidle_driver *drv,
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int index)
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{
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return true;
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}
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#endif
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static int tegra20_idle_lp2(struct cpuidle_device *dev,
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struct cpuidle_driver *drv,
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int index)
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{
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u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu;
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bool entered_lp2 = false;
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local_fiq_disable();
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tegra_set_cpu_in_lp2(cpu);
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cpu_pm_enter();
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if (cpu == 0)
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cpu_do_idle();
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else
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entered_lp2 = tegra20_idle_enter_lp2_cpu_1(dev, drv, index);
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cpu_pm_exit();
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tegra_clear_cpu_in_lp2(cpu);
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local_fiq_enable();
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smp_rmb();
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return entered_lp2 ? index : 0;
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}
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#endif
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int __init tegra20_cpuidle_init(void)
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{
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int ret;
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@ -44,6 +122,10 @@ int __init tegra20_cpuidle_init(void)
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struct cpuidle_device *dev;
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struct cpuidle_driver *drv = &tegra_idle_driver;
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drv->state_count = ARRAY_SIZE(tegra_idle_states);
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memcpy(drv->states, tegra_idle_states,
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drv->state_count * sizeof(drv->states[0]));
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ret = cpuidle_register_driver(&tegra_idle_driver);
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if (ret) {
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pr_err("CPUidle driver registration failed\n");
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@ -36,6 +36,7 @@
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#include "iomap.h"
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#include "reset.h"
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#include "flowctrl.h"
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#include "fuse.h"
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#include "sleep.h"
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#define TEGRA_POWER_CPU_PWRREQ_OE (1 << 16) /* CPU pwr req enable */
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@ -173,6 +174,8 @@ bool tegra_set_cpu_in_lp2(int phy_cpu_id)
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if ((phy_cpu_id == 0) && cpumask_equal(cpu_lp2_mask, cpu_online_mask))
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last_cpu = true;
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else if (tegra_chip_id == TEGRA20 && phy_cpu_id == 1)
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tegra20_cpu_set_resettable_soon();
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spin_unlock(&tegra_lp2_lock);
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return last_cpu;
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@ -21,6 +21,8 @@
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/proc-fns.h>
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#include <asm/cp15.h>
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#include "sleep.h"
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#include "flowctrl.h"
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@ -75,3 +77,148 @@ ENTRY(tegra20_cpu_shutdown)
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mov pc, lr
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ENDPROC(tegra20_cpu_shutdown)
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#endif
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#ifdef CONFIG_PM_SLEEP
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/*
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* tegra_pen_lock
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*
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* spinlock implementation with no atomic test-and-set and no coherence
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* using Peterson's algorithm on strongly-ordered registers
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* used to synchronize a cpu waking up from wfi with entering lp2 on idle
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*
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* The reference link of Peterson's algorithm:
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* http://en.wikipedia.org/wiki/Peterson's_algorithm
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*
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* SCRATCH37 = r1 = !turn (inverted from Peterson's algorithm)
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* on cpu 0:
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* r2 = flag[0] (in SCRATCH38)
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* r3 = flag[1] (in SCRATCH39)
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* on cpu1:
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* r2 = flag[1] (in SCRATCH39)
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* r3 = flag[0] (in SCRATCH38)
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*
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* must be called with MMU on
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* corrupts r0-r3, r12
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*/
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ENTRY(tegra_pen_lock)
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mov32 r3, TEGRA_PMC_VIRT
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cpu_id r0
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add r1, r3, #PMC_SCRATCH37
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cmp r0, #0
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addeq r2, r3, #PMC_SCRATCH38
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addeq r3, r3, #PMC_SCRATCH39
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addne r2, r3, #PMC_SCRATCH39
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addne r3, r3, #PMC_SCRATCH38
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mov r12, #1
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str r12, [r2] @ flag[cpu] = 1
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dsb
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str r12, [r1] @ !turn = cpu
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1: dsb
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ldr r12, [r3]
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cmp r12, #1 @ flag[!cpu] == 1?
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ldreq r12, [r1]
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cmpeq r12, r0 @ !turn == cpu?
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beq 1b @ while !turn == cpu && flag[!cpu] == 1
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mov pc, lr @ locked
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ENDPROC(tegra_pen_lock)
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ENTRY(tegra_pen_unlock)
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dsb
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mov32 r3, TEGRA_PMC_VIRT
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cpu_id r0
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cmp r0, #0
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addeq r2, r3, #PMC_SCRATCH38
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addne r2, r3, #PMC_SCRATCH39
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mov r12, #0
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str r12, [r2]
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mov pc, lr
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ENDPROC(tegra_pen_unlock)
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/*
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* tegra20_cpu_clear_resettable(void)
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*
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* Called to clear the "resettable soon" flag in PMC_SCRATCH41 when
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* it is expected that the secondary CPU will be idle soon.
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*/
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ENTRY(tegra20_cpu_clear_resettable)
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mov32 r1, TEGRA_PMC_VIRT + PMC_SCRATCH41
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mov r12, #CPU_NOT_RESETTABLE
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str r12, [r1]
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mov pc, lr
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ENDPROC(tegra20_cpu_clear_resettable)
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/*
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* tegra20_cpu_set_resettable_soon(void)
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*
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* Called to set the "resettable soon" flag in PMC_SCRATCH41 when
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* it is expected that the secondary CPU will be idle soon.
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*/
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ENTRY(tegra20_cpu_set_resettable_soon)
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mov32 r1, TEGRA_PMC_VIRT + PMC_SCRATCH41
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mov r12, #CPU_RESETTABLE_SOON
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str r12, [r1]
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mov pc, lr
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ENDPROC(tegra20_cpu_set_resettable_soon)
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/*
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* tegra20_sleep_cpu_secondary_finish(unsigned long v2p)
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*
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* Enters WFI on secondary CPU by exiting coherency.
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*/
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ENTRY(tegra20_sleep_cpu_secondary_finish)
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stmfd sp!, {r4-r11, lr}
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mrc p15, 0, r11, c1, c0, 1 @ save actlr before exiting coherency
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/* Flush and disable the L1 data cache */
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bl tegra_disable_clean_inv_dcache
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mov32 r0, TEGRA_PMC_VIRT + PMC_SCRATCH41
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mov r3, #CPU_RESETTABLE
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str r3, [r0]
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bl cpu_do_idle
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/*
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* cpu may be reset while in wfi, which will return through
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* tegra_resume to cpu_resume
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* or interrupt may wake wfi, which will return here
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* cpu state is unchanged - MMU is on, cache is on, coherency
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* is off, and the data cache is off
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*
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* r11 contains the original actlr
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*/
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bl tegra_pen_lock
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mov32 r3, TEGRA_PMC_VIRT
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add r0, r3, #PMC_SCRATCH41
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mov r3, #CPU_NOT_RESETTABLE
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str r3, [r0]
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bl tegra_pen_unlock
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/* Re-enable the data cache */
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mrc p15, 0, r10, c1, c0, 0
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orr r10, r10, #CR_C
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mcr p15, 0, r10, c1, c0, 0
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isb
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mcr p15, 0, r11, c1, c0, 1 @ reenable coherency
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/* Invalidate the TLBs & BTAC */
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mov r1, #0
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mcr p15, 0, r1, c8, c3, 0 @ invalidate shared TLBs
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mcr p15, 0, r1, c7, c1, 6 @ invalidate shared BTAC
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dsb
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isb
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/* the cpu was running with coherency disabled,
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* caches may be out of date */
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bl v7_flush_kern_cache_louis
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ldmfd sp!, {r4 - r11, pc}
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ENDPROC(tegra20_sleep_cpu_secondary_finish)
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#endif
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@ -25,6 +25,19 @@
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+ IO_PPSB_VIRT)
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#define TEGRA_CLK_RESET_VIRT (TEGRA_CLK_RESET_BASE - IO_PPSB_PHYS \
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+ IO_PPSB_VIRT)
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#define TEGRA_PMC_VIRT (TEGRA_PMC_BASE - IO_APB_PHYS + IO_APB_VIRT)
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/* PMC_SCRATCH37-39 and 41 are used for tegra_pen_lock and idle */
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#define PMC_SCRATCH37 0x130
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#define PMC_SCRATCH38 0x134
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#define PMC_SCRATCH39 0x138
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#define PMC_SCRATCH41 0x140
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#ifdef CONFIG_ARCH_TEGRA_2x_SOC
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#define CPU_RESETTABLE 2
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#define CPU_RESETTABLE_SOON 1
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#define CPU_NOT_RESETTABLE 0
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#endif
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#ifdef __ASSEMBLY__
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/* returns the offset of the flow controller halt register for a cpu */
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@ -104,6 +117,8 @@ exit_l2_resume:
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.endm
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#endif /* CONFIG_CACHE_L2X0 */
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#else
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void tegra_pen_lock(void);
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void tegra_pen_unlock(void);
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void tegra_resume(void);
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int tegra_sleep_cpu_finish(unsigned long);
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void tegra_disable_clean_inv_dcache(void);
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@ -116,6 +131,14 @@ static inline void tegra20_hotplug_init(void) {}
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static inline void tegra30_hotplug_init(void) {}
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#endif
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void tegra20_cpu_clear_resettable(void);
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#ifdef CONFIG_ARCH_TEGRA_2x_SOC
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void tegra20_cpu_set_resettable_soon(void);
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#else
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static inline void tegra20_cpu_set_resettable_soon(void) {}
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#endif
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int tegra20_sleep_cpu_secondary_finish(unsigned long);
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int tegra30_sleep_cpu_secondary_finish(unsigned long);
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void tegra30_tear_down_cpu(void);
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