Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
* 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: random: Fix handing of arch_get_random_long in get_random_bytes() x86: Call stop_machine_text_poke() on all CPUs x86, ioapic: Only print ioapic debug information for IRQs belonging to an ioapic chip x86/mrst: Avoid reporting wrong nmi status x86/mrst: Add support for Penwell clock calibration x86/apic: Allow use of lapic timer early calibration result x86/apic: Do not clear nr_irqs_gsi if no legacy irqs x86/platform: Add a wallclock_init func to x86_platforms ops x86/mce: Make mce_chrdev_ops 'static const'
This commit is contained in:
commit
5c6b4e84cb
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@ -49,6 +49,7 @@ extern unsigned int apic_verbosity;
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extern int local_apic_timer_c2_ok;
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extern int disable_apic;
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extern unsigned int lapic_timer_frequency;
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#ifdef CONFIG_SMP
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extern void __inquire_remote_apic(int apicid);
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@ -17,7 +17,7 @@
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#define NMI_REASON_CLEAR_IOCHK 0x08
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#define NMI_REASON_CLEAR_MASK 0x0f
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static inline unsigned char get_nmi_reason(void)
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static inline unsigned char default_get_nmi_reason(void)
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{
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return inb(NMI_REASON_PORT);
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}
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@ -201,7 +201,10 @@ int mce_notify_irq(void);
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void mce_notify_process(void);
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DECLARE_PER_CPU(struct mce, injectm);
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extern struct file_operations mce_chrdev_ops;
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extern void register_mce_write_callback(ssize_t (*)(struct file *filp,
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const char __user *ubuf,
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size_t usize, loff_t *off));
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/*
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* Exception handler
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@ -44,6 +44,13 @@ enum mrst_timer_options {
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extern enum mrst_timer_options mrst_timer_options;
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/*
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* Penwell uses spread spectrum clock, so the freq number is not exactly
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* the same as reported by MSR based on SDM.
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*/
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#define PENWELL_FSB_FREQ_83SKU 83200
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#define PENWELL_FSB_FREQ_100SKU 99840
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#define SFI_MTMR_MAX_NUM 8
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#define SFI_MRTC_MAX 8
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@ -152,6 +152,7 @@ struct x86_cpuinit_ops {
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/**
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* struct x86_platform_ops - platform specific runtime functions
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* @calibrate_tsc: calibrate TSC
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* @wallclock_init: init the wallclock device
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* @get_wallclock: get time from HW clock like RTC etc.
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* @set_wallclock: set time back to HW clock
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* @is_untracked_pat_range exclude from PAT logic
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@ -160,11 +161,13 @@ struct x86_cpuinit_ops {
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*/
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struct x86_platform_ops {
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unsigned long (*calibrate_tsc)(void);
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void (*wallclock_init)(void);
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unsigned long (*get_wallclock)(void);
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int (*set_wallclock)(unsigned long nowtime);
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void (*iommu_shutdown)(void);
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bool (*is_untracked_pat_range)(u64 start, u64 end);
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void (*nmi_init)(void);
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unsigned char (*get_nmi_reason)(void);
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int (*i8042_detect)(void);
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};
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@ -738,5 +738,5 @@ void __kprobes text_poke_smp_batch(struct text_poke_param *params, int n)
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atomic_set(&stop_machine_first, 1);
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wrote_text = 0;
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__stop_machine(stop_machine_text_poke, (void *)&tpp, NULL);
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__stop_machine(stop_machine_text_poke, (void *)&tpp, cpu_online_mask);
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}
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@ -186,7 +186,7 @@ static struct resource lapic_resource = {
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.flags = IORESOURCE_MEM | IORESOURCE_BUSY,
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};
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static unsigned int calibration_result;
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unsigned int lapic_timer_frequency = 0;
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static void apic_pm_activate(void);
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@ -454,7 +454,7 @@ static void lapic_timer_setup(enum clock_event_mode mode,
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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case CLOCK_EVT_MODE_ONESHOT:
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__setup_APIC_LVTT(calibration_result,
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__setup_APIC_LVTT(lapic_timer_frequency,
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mode != CLOCK_EVT_MODE_PERIODIC, 1);
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break;
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case CLOCK_EVT_MODE_UNUSED:
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@ -638,6 +638,25 @@ static int __init calibrate_APIC_clock(void)
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long delta, deltatsc;
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int pm_referenced = 0;
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/**
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* check if lapic timer has already been calibrated by platform
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* specific routine, such as tsc calibration code. if so, we just fill
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* in the clockevent structure and return.
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*/
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if (lapic_timer_frequency) {
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apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n",
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lapic_timer_frequency);
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lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR,
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TICK_NSEC, lapic_clockevent.shift);
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lapic_clockevent.max_delta_ns =
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clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
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lapic_clockevent.min_delta_ns =
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clockevent_delta2ns(0xF, &lapic_clockevent);
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lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
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return 0;
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}
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local_irq_disable();
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/* Replace the global interrupt handler */
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@ -679,12 +698,12 @@ static int __init calibrate_APIC_clock(void)
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lapic_clockevent.min_delta_ns =
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clockevent_delta2ns(0xF, &lapic_clockevent);
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calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
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lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
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apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
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apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult);
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apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
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calibration_result);
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lapic_timer_frequency);
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if (cpu_has_tsc) {
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apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
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@ -695,13 +714,13 @@ static int __init calibrate_APIC_clock(void)
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apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
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"%u.%04u MHz.\n",
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calibration_result / (1000000 / HZ),
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calibration_result % (1000000 / HZ));
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lapic_timer_frequency / (1000000 / HZ),
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lapic_timer_frequency % (1000000 / HZ));
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/*
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* Do a sanity check on the APIC calibration result
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*/
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if (calibration_result < (1000000 / HZ)) {
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if (lapic_timer_frequency < (1000000 / HZ)) {
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local_irq_enable();
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pr_warning("APIC frequency too slow, disabling apic timer\n");
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return -1;
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@ -193,10 +193,8 @@ int __init arch_early_irq_init(void)
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struct irq_cfg *cfg;
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int count, node, i;
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if (!legacy_pic->nr_legacy_irqs) {
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nr_irqs_gsi = 0;
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if (!legacy_pic->nr_legacy_irqs)
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io_apic_irqs = ~0UL;
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}
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for (i = 0; i < nr_ioapics; i++) {
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ioapics[i].saved_registers =
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@ -1696,6 +1694,7 @@ __apicdebuginit(void) print_IO_APICs(void)
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int ioapic_idx;
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struct irq_cfg *cfg;
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unsigned int irq;
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struct irq_chip *chip;
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printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
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for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
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@ -1716,6 +1715,10 @@ __apicdebuginit(void) print_IO_APICs(void)
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for_each_active_irq(irq) {
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struct irq_pin_list *entry;
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chip = irq_get_chip(irq);
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if (chip != &ioapic_chip)
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continue;
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cfg = irq_get_chip_data(irq);
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if (!cfg)
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continue;
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@ -208,7 +208,7 @@ static int inject_init(void)
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if (!alloc_cpumask_var(&mce_inject_cpumask, GFP_KERNEL))
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return -ENOMEM;
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printk(KERN_INFO "Machine check injector initialized\n");
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mce_chrdev_ops.write = mce_write;
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register_mce_write_callback(mce_write);
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register_nmi_handler(NMI_LOCAL, mce_raise_notify, 0,
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"mce_notify");
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return 0;
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@ -1634,16 +1634,35 @@ static long mce_chrdev_ioctl(struct file *f, unsigned int cmd,
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}
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}
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/* Modified in mce-inject.c, so not static or const */
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struct file_operations mce_chrdev_ops = {
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static ssize_t (*mce_write)(struct file *filp, const char __user *ubuf,
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size_t usize, loff_t *off);
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void register_mce_write_callback(ssize_t (*fn)(struct file *filp,
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const char __user *ubuf,
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size_t usize, loff_t *off))
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{
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mce_write = fn;
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}
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EXPORT_SYMBOL_GPL(register_mce_write_callback);
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ssize_t mce_chrdev_write(struct file *filp, const char __user *ubuf,
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size_t usize, loff_t *off)
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{
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if (mce_write)
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return mce_write(filp, ubuf, usize, off);
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else
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return -EINVAL;
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}
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static const struct file_operations mce_chrdev_ops = {
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.open = mce_chrdev_open,
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.release = mce_chrdev_release,
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.read = mce_chrdev_read,
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.write = mce_chrdev_write,
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.poll = mce_chrdev_poll,
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.unlocked_ioctl = mce_chrdev_ioctl,
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.llseek = no_llseek,
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};
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EXPORT_SYMBOL_GPL(mce_chrdev_ops);
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static struct miscdevice mce_chrdev_device = {
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MISC_MCELOG_MINOR,
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@ -29,6 +29,7 @@
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#include <asm/traps.h>
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#include <asm/mach_traps.h>
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#include <asm/nmi.h>
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#include <asm/x86_init.h>
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#define NMI_MAX_NAMELEN 16
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struct nmiaction {
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/* Non-CPU-specific NMI: NMI sources can be processed on any CPU */
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raw_spin_lock(&nmi_reason_lock);
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reason = get_nmi_reason();
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reason = x86_platform.get_nmi_reason();
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if (reason & NMI_REASON_MASK) {
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if (reason & NMI_REASON_SERR)
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@ -1045,6 +1045,8 @@ void __init setup_arch(char **cmdline_p)
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x86_init.timers.wallclock_init();
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x86_platform.wallclock_init();
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mcheck_init();
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arch_init_ideal_nops();
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@ -21,12 +21,14 @@
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#include <asm/pat.h>
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#include <asm/tsc.h>
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#include <asm/iommu.h>
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#include <asm/mach_traps.h>
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void __cpuinit x86_init_noop(void) { }
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void __init x86_init_uint_noop(unsigned int unused) { }
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void __init x86_init_pgd_noop(pgd_t *unused) { }
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int __init iommu_init_noop(void) { return 0; }
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void iommu_shutdown_noop(void) { }
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void wallclock_init_noop(void) { }
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/*
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* The platform setup functions are preset with the default functions
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@ -97,11 +99,13 @@ static int default_i8042_detect(void) { return 1; };
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struct x86_platform_ops x86_platform = {
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.calibrate_tsc = native_calibrate_tsc,
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.wallclock_init = wallclock_init_noop,
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.get_wallclock = mach_get_cmos_time,
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.set_wallclock = mach_set_rtc_mmss,
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.iommu_shutdown = iommu_shutdown_noop,
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.is_untracked_pat_range = is_ISA_range,
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.nmi_init = default_nmi_init,
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.get_nmi_reason = default_get_nmi_reason,
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.i8042_detect = default_i8042_detect
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};
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@ -187,11 +187,34 @@ int __init sfi_parse_mrtc(struct sfi_table_header *table)
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static unsigned long __init mrst_calibrate_tsc(void)
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{
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unsigned long flags, fast_calibrate;
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if (__mrst_cpu_chip == MRST_CPU_CHIP_PENWELL) {
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u32 lo, hi, ratio, fsb;
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local_irq_save(flags);
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fast_calibrate = apbt_quick_calibrate();
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local_irq_restore(flags);
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rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
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pr_debug("IA32 perf status is 0x%x, 0x%0x\n", lo, hi);
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ratio = (hi >> 8) & 0x1f;
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pr_debug("ratio is %d\n", ratio);
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if (!ratio) {
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pr_err("read a zero ratio, should be incorrect!\n");
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pr_err("force tsc ratio to 16 ...\n");
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ratio = 16;
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}
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rdmsr(MSR_FSB_FREQ, lo, hi);
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if ((lo & 0x7) == 0x7)
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fsb = PENWELL_FSB_FREQ_83SKU;
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else
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fsb = PENWELL_FSB_FREQ_100SKU;
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fast_calibrate = ratio * fsb;
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pr_debug("read penwell tsc %lu khz\n", fast_calibrate);
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lapic_timer_frequency = fsb * 1000 / HZ;
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/* mark tsc clocksource as reliable */
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set_cpu_cap(&boot_cpu_data, X86_FEATURE_TSC_RELIABLE);
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} else {
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local_irq_save(flags);
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fast_calibrate = apbt_quick_calibrate();
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local_irq_restore(flags);
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}
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if (fast_calibrate)
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return fast_calibrate;
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@ -253,6 +276,17 @@ static void mrst_reboot(void)
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intel_scu_ipc_simple_command(0xf1, 0);
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}
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/*
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* Moorestown does not have external NMI source nor port 0x61 to report
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* NMI status. The possible NMI sources are from pmu as a result of NMI
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* watchdog or lock debug. Reading io port 0x61 results in 0xff which
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* misled NMI handler.
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*/
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static unsigned char mrst_get_nmi_reason(void)
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{
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return 0;
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}
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/*
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* Moorestown specific x86_init function overrides and early setup
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* calls.
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@ -274,6 +308,8 @@ void __init x86_mrst_early_setup(void)
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x86_platform.calibrate_tsc = mrst_calibrate_tsc;
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x86_platform.i8042_detect = mrst_i8042_detect;
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x86_init.timers.wallclock_init = mrst_rtc_init;
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x86_platform.get_nmi_reason = mrst_get_nmi_reason;
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x86_init.pci.init = pci_mrst_init;
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x86_init.pci.fixup_irqs = x86_init_noop;
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