imx-drm limit fixes
Fix IPU IC downscaler to its hardware limitation of 4:1 and the IPU DI pixel clock divider integer part to 8-bit. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJVGnyFAAoJEFDCiBxwnmDrP9IQAI+hF9AwH645S7VS2aWJdepn It+LSh2lQ0Mn8Q2pQYDuoJAoM2u98H04270lhL5JfSc1uqdiud6J+hzSG/0D8fqu 6ZDMV+yen3edo3B3HXtmAbglv6DGEht5HjEcjKIJ14vV0l+q6AdLPwKVbZkw3hl2 LMeexTDx/rMnWizhiXrAGaYmOTYawXOWM/kj1NbQYCBQfVScsJcmrd11NC6xE5ak Mvpv4wtwQ5/g/XwDeBZLRF6+WL9dvRdj0gId6JMisCG7mMOXZxHAKArarWqY7FUE sRtMkvnBmgrZhmkXcBXWN3DgdSC1kSWa6CZqHWDdVDnmcU0cozKsnrAoZdGLfhS9 +ryml/poUA9IEqZTtb/XuzY+gYEyXX5PoLoqdcWXgiEuFgWgdM1CilrmJl+IxyIj A5/NaA9SUHVqGAF1+5b4nTjFYCl6UuZnLlx+ov3MfK1C4w9c711GUUt24PBv9KFy eYVOswg+cqWkXfeYiLFAv2BoB8pkhDCLwhySRhCjHYJq9NfTgViwCLCYJ59RTQPs auz6d9wN19D4rE1eagV4LeTPDZVuoTYcE9RxHGhl32fO1ISq0u0L9xRq5X63CF6k 1LajiyGdD9aJbuAgaywGqmRuGiCasOdgqp6KV68cLRuQ86Dd6R9a8vQ5tw/cWERD td2rf0B0zduI34/S98oS =1E75 -----END PGP SIGNATURE----- Merge tag 'imx-drm-fixes-2015-03-31' of git://git.pengutronix.de/git/pza/linux into drm-next imx-drm limit fixes Fix IPU IC downscaler to its hardware limitation of 4:1 and the IPU DI pixel clock divider integer part to 8-bit. * tag 'imx-drm-fixes-2015-03-31' of git://git.pengutronix.de/git/pza/linux: gpu: ipu-v3: turns out the IPU can only downsize 4:1 gpu: ipu-v3: limit pixel clock divider to 8-bits drm/radeon: programm the VCE fw BAR as well drm/radeon: always dump the ring content if it's available radeon: Do not directly dereference pointers to BIOS area. drm/radeon/dpm: fix 120hz handling harder
This commit is contained in:
commit
5c7f0c2795
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@ -2131,6 +2131,7 @@
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#define VCE_UENC_REG_CLOCK_GATING 0x207c0
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#define VCE_SYS_INT_EN 0x21300
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# define VCE_SYS_INT_TRAP_INTERRUPT_EN (1 << 3)
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#define VCE_LMI_VCPU_CACHE_40BIT_BAR 0x2145c
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#define VCE_LMI_CTRL2 0x21474
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#define VCE_LMI_CTRL 0x21498
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#define VCE_LMI_VM_CTRL 0x214a0
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@ -1567,6 +1567,7 @@ struct radeon_dpm {
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int new_active_crtc_count;
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u32 current_active_crtcs;
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int current_active_crtc_count;
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bool single_display;
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struct radeon_dpm_dynamic_state dyn_state;
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struct radeon_dpm_fan fan;
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u32 tdp_limit;
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@ -76,7 +76,7 @@ static bool igp_read_bios_from_vram(struct radeon_device *rdev)
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static bool radeon_read_bios(struct radeon_device *rdev)
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{
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uint8_t __iomem *bios;
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uint8_t __iomem *bios, val1, val2;
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size_t size;
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rdev->bios = NULL;
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@ -86,15 +86,19 @@ static bool radeon_read_bios(struct radeon_device *rdev)
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return false;
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}
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if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
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val1 = readb(&bios[0]);
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val2 = readb(&bios[1]);
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if (size == 0 || val1 != 0x55 || val2 != 0xaa) {
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pci_unmap_rom(rdev->pdev, bios);
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return false;
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}
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rdev->bios = kmemdup(bios, size, GFP_KERNEL);
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rdev->bios = kzalloc(size, GFP_KERNEL);
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if (rdev->bios == NULL) {
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pci_unmap_rom(rdev->pdev, bios);
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return false;
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}
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memcpy_fromio(rdev->bios, bios, size);
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pci_unmap_rom(rdev->pdev, bios);
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return true;
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}
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@ -837,12 +837,8 @@ static void radeon_dpm_thermal_work_handler(struct work_struct *work)
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radeon_pm_compute_clocks(rdev);
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}
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static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
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enum radeon_pm_state_type dpm_state)
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static bool radeon_dpm_single_display(struct radeon_device *rdev)
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{
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int i;
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struct radeon_ps *ps;
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u32 ui_class;
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bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ?
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true : false;
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@ -858,6 +854,17 @@ static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
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if (single_display && (r600_dpm_get_vrefresh(rdev) >= 120))
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single_display = false;
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return single_display;
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}
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static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
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enum radeon_pm_state_type dpm_state)
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{
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int i;
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struct radeon_ps *ps;
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u32 ui_class;
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bool single_display = radeon_dpm_single_display(rdev);
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/* certain older asics have a separare 3D performance state,
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* so try that first if the user selected performance
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*/
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@ -983,6 +990,7 @@ static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
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struct radeon_ps *ps;
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enum radeon_pm_state_type dpm_state;
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int ret;
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bool single_display = radeon_dpm_single_display(rdev);
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/* if dpm init failed */
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if (!rdev->pm.dpm_enabled)
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@ -1007,6 +1015,9 @@ static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
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/* vce just modifies an existing state so force a change */
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if (ps->vce_active != rdev->pm.dpm.vce_active)
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goto force;
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/* user has made a display change (such as timing) */
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if (rdev->pm.dpm.single_display != single_display)
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goto force;
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if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) {
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/* for pre-BTC and APUs if the num crtcs changed but state is the same,
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* all we need to do is update the display configuration.
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@ -1069,6 +1080,7 @@ force:
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rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
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rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
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rdev->pm.dpm.single_display = single_display;
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/* wait for the rings to drain */
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for (i = 0; i < RADEON_NUM_RINGS; i++) {
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@ -495,7 +495,7 @@ static int radeon_debugfs_ring_info(struct seq_file *m, void *data)
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seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
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seq_printf(m, "%u dwords in ring\n", count);
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if (!ring->ready)
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if (!ring->ring)
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return 0;
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/* print 8 dw before current rptr as often it's the last executed
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@ -156,6 +156,9 @@ int vce_v2_0_resume(struct radeon_device *rdev)
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WREG32(VCE_LMI_SWAP_CNTL1, 0);
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WREG32(VCE_LMI_VM_CTRL, 0);
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WREG32(VCE_LMI_VCPU_CACHE_40BIT_BAR, addr >> 8);
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addr &= 0xff;
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size = RADEON_GPU_PAGE_ALIGN(rdev->vce_fw->size);
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WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);
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WREG32(VCE_VCPU_CACHE_SIZE0, size);
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@ -441,8 +441,7 @@ static void ipu_di_config_clock(struct ipu_di *di,
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in_rate = clk_get_rate(clk);
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div = DIV_ROUND_CLOSEST(in_rate, sig->mode.pixelclock);
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if (div == 0)
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div = 1;
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div = clamp(div, 1U, 255U);
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clkgen0 = div << 4;
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}
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clkrate = clk_get_rate(di->clk_ipu);
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div = DIV_ROUND_CLOSEST(clkrate, sig->mode.pixelclock);
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if (div == 0)
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div = 1;
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div = clamp(div, 1U, 255U);
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rate = clkrate / div;
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error = rate / (sig->mode.pixelclock / 1000);
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in_rate = clk_get_rate(clk);
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div = DIV_ROUND_CLOSEST(in_rate, sig->mode.pixelclock);
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if (div == 0)
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div = 1;
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div = clamp(div, 1U, 255U);
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clkgen0 = div << 4;
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}
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@ -297,8 +297,8 @@ static int calc_resize_coeffs(struct ipu_ic *ic,
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return -EINVAL;
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}
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/* Cannot downsize more than 8:1 */
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if ((out_size << 3) < in_size) {
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/* Cannot downsize more than 4:1 */
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if ((out_size << 2) < in_size) {
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dev_err(ipu->dev, "Unsupported downsize\n");
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return -EINVAL;
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}
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