ASoC: Improve EP93xx I2S clocks management.
Improve EP93xx I2S clocks management. Some freqs values are set not exact as they requested for MCLK and original code was not able to find divisors for SCLK and LRCLK. This code just picks up nearest value from 3 possible variants. This patch makes 44100 and 192000 rates working and fixes capture function (by selecting SCLK/LRCLK=64 where possible). All other rates should work as before. Signed-off-by: Alexander Sverdlin <subaparts@yandex.ru> Acked-by: Liam Girdwood <lrg@ti.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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@ -242,7 +242,7 @@ static int ep93xx_i2s_hw_params(struct snd_pcm_substream *substream,
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{
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struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
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unsigned word_len, div, sdiv, lrdiv;
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int found = 0, err;
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int err;
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S16_LE:
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@ -275,15 +275,14 @@ static int ep93xx_i2s_hw_params(struct snd_pcm_substream *substream,
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* the codec uses.
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*/
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div = clk_get_rate(info->mclk) / params_rate(params);
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for (sdiv = 2; sdiv <= 4; sdiv += 2)
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for (lrdiv = 64; lrdiv <= 128; lrdiv <<= 1)
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if (sdiv * lrdiv == div) {
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found = 1;
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goto out;
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}
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out:
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if (!found)
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return -EINVAL;
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sdiv = 4;
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if (div > (256 + 512) / 2) {
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lrdiv = 128;
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} else {
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lrdiv = 64;
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if (div < (128 + 256) / 2)
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sdiv = 2;
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}
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err = clk_set_rate(info->sclk, clk_get_rate(info->mclk) / sdiv);
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if (err)
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