spi: rcar: add Renesas QSPI support on RSPI
The R8A7790 has QSPI module which is very similar to RSPI. This patch adds into RSPI module together to supports QSPI module. Signed-off-by: Hiep Cao Minh <cm-hiep@jinso.co.jp> Signed-off-by: Mark Brown <broonie@linaro.org>hifive-unleashed-5.1
Hiep Cao Minh
Mark Brown
parent
272b98c645
commit
5ce0ba8865
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@ -369,7 +369,7 @@ config SPI_PXA2XX_PCI
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config SPI_RSPI
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tristate "Renesas RSPI controller"
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depends on SUPERH && SH_DMAE_BASE
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depends on (SUPERH || ARCH_SHMOBILE) && SH_DMAE_BASE
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help
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SPI driver for Renesas RSPI blocks.
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@ -59,6 +59,14 @@
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#define RSPI_SPCMD6 0x1c
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#define RSPI_SPCMD7 0x1e
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/*qspi only */
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#define QSPI_SPBFCR 0x18
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#define QSPI_SPBDCR 0x1a
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#define QSPI_SPBMUL0 0x1c
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#define QSPI_SPBMUL1 0x20
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#define QSPI_SPBMUL2 0x24
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#define QSPI_SPBMUL3 0x28
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/* SPCR */
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#define SPCR_SPRIE 0x80
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#define SPCR_SPE 0x40
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@ -126,6 +134,8 @@
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#define SPCMD_LSBF 0x1000
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#define SPCMD_SPB_MASK 0x0f00
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#define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK)
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#define SPCMD_SPB_8BIT 0x0000 /* qspi only */
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#define SPCMD_SPB_16BIT 0x0100
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#define SPCMD_SPB_20BIT 0x0000
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#define SPCMD_SPB_24BIT 0x0100
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#define SPCMD_SPB_32BIT 0x0200
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@ -135,6 +145,10 @@
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#define SPCMD_CPOL 0x0002
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#define SPCMD_CPHA 0x0001
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/* SPBFCR */
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#define SPBFCR_TXRST 0x80 /* qspi only */
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#define SPBFCR_RXRST 0x40 /* qspi only */
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struct rspi_data {
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void __iomem *addr;
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u32 max_speed_hz;
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@ -145,6 +159,7 @@ struct rspi_data {
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spinlock_t lock;
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struct clk *clk;
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unsigned char spsr;
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const struct spi_ops *ops;
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/* for dmaengine */
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struct dma_chan *chan_tx;
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@ -165,6 +180,11 @@ static void rspi_write16(struct rspi_data *rspi, u16 data, u16 offset)
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iowrite16(data, rspi->addr + offset);
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}
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static void rspi_write32(struct rspi_data *rspi, u32 data, u16 offset)
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{
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iowrite32(data, rspi->addr + offset);
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}
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static u8 rspi_read8(struct rspi_data *rspi, u16 offset)
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{
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return ioread8(rspi->addr + offset);
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@ -175,17 +195,98 @@ static u16 rspi_read16(struct rspi_data *rspi, u16 offset)
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return ioread16(rspi->addr + offset);
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}
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static unsigned char rspi_calc_spbr(struct rspi_data *rspi)
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/* optional functions */
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struct spi_ops {
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int (*set_config_register)(struct rspi_data *rspi, int access_size);
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};
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/*
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* functions for RSPI
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*/
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static int rspi_set_config_register(struct rspi_data *rspi, int access_size)
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{
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int tmp;
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unsigned char spbr;
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int spbr;
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tmp = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz) - 1;
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spbr = clamp(tmp, 0, 255);
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/* Sets output mode(CMOS) and MOSI signal(from previous transfer) */
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rspi_write8(rspi, 0x00, RSPI_SPPCR);
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return spbr;
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/* Sets transfer bit rate */
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spbr = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz) - 1;
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rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
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/* Sets number of frames to be used: 1 frame */
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rspi_write8(rspi, 0x00, RSPI_SPDCR);
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/* Sets RSPCK, SSL, next-access delay value */
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rspi_write8(rspi, 0x00, RSPI_SPCKD);
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rspi_write8(rspi, 0x00, RSPI_SSLND);
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rspi_write8(rspi, 0x00, RSPI_SPND);
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/* Sets parity, interrupt mask */
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rspi_write8(rspi, 0x00, RSPI_SPCR2);
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/* Sets SPCMD */
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rspi_write16(rspi, SPCMD_SPB_8_TO_16(access_size) | SPCMD_SSLKP,
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RSPI_SPCMD0);
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/* Sets RSPI mode */
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rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
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return 0;
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}
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/*
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* functions for QSPI
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*/
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static int qspi_set_config_register(struct rspi_data *rspi, int access_size)
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{
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u16 spcmd;
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int spbr;
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/* Sets output mode(CMOS) and MOSI signal(from previous transfer) */
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rspi_write8(rspi, 0x00, RSPI_SPPCR);
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/* Sets transfer bit rate */
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spbr = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz);
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rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
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/* Sets number of frames to be used: 1 frame */
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rspi_write8(rspi, 0x00, RSPI_SPDCR);
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/* Sets RSPCK, SSL, next-access delay value */
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rspi_write8(rspi, 0x00, RSPI_SPCKD);
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rspi_write8(rspi, 0x00, RSPI_SSLND);
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rspi_write8(rspi, 0x00, RSPI_SPND);
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/* Data Length Setting */
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if (access_size == 8)
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spcmd = SPCMD_SPB_8BIT;
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else if (access_size == 16)
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spcmd = SPCMD_SPB_16BIT;
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else if (access_size == 32)
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spcmd = SPCMD_SPB_32BIT;
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spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | SPCMD_SSLKP | SPCMD_SPNDEN;
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/* Resets transfer data length */
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rspi_write32(rspi, 0, QSPI_SPBMUL0);
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/* Resets transmit and receive buffer */
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rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
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/* Sets buffer to allow normal operation */
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rspi_write8(rspi, 0x00, QSPI_SPBFCR);
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/* Sets SPCMD */
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rspi_write16(rspi, spcmd, RSPI_SPCMD0);
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/* Enables SPI function in a master mode */
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rspi_write8(rspi, SPCR_SPE | SPCR_MSTR, RSPI_SPCR);
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return 0;
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}
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#define set_config_register(spi, n) spi->ops->set_config_register(spi, n)
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static void rspi_enable_irq(struct rspi_data *rspi, u8 enable)
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{
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rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR);
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@ -220,35 +321,6 @@ static void rspi_negate_ssl(struct rspi_data *rspi)
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rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR);
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}
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static int rspi_set_config_register(struct rspi_data *rspi, int access_size)
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{
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/* Sets output mode(CMOS) and MOSI signal(from previous transfer) */
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rspi_write8(rspi, 0x00, RSPI_SPPCR);
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/* Sets transfer bit rate */
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rspi_write8(rspi, rspi_calc_spbr(rspi), RSPI_SPBR);
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/* Sets number of frames to be used: 1 frame */
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rspi_write8(rspi, 0x00, RSPI_SPDCR);
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/* Sets RSPCK, SSL, next-access delay value */
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rspi_write8(rspi, 0x00, RSPI_SPCKD);
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rspi_write8(rspi, 0x00, RSPI_SSLND);
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rspi_write8(rspi, 0x00, RSPI_SPND);
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/* Sets parity, interrupt mask */
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rspi_write8(rspi, 0x00, RSPI_SPCR2);
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/* Sets SPCMD */
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rspi_write16(rspi, SPCMD_SPB_8_TO_16(access_size) | SPCMD_SSLKP,
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RSPI_SPCMD0);
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/* Sets RSPI mode */
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rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
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return 0;
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}
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static int rspi_send_pio(struct rspi_data *rspi, struct spi_message *mesg,
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struct spi_transfer *t)
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{
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@ -616,7 +688,7 @@ static int rspi_setup(struct spi_device *spi)
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spi->bits_per_word = 8;
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rspi->max_speed_hz = spi->max_speed_hz;
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rspi_set_config_register(rspi, 8);
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set_config_register(rspi, 8);
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return 0;
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}
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@ -745,7 +817,16 @@ static int rspi_probe(struct platform_device *pdev)
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struct rspi_data *rspi;
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int ret, irq;
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char clk_name[16];
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struct rspi_plat_data *rspi_pd = pdev->dev.platform_data;
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const struct spi_ops *ops;
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const struct platform_device_id *id_entry = pdev->id_entry;
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ops = (struct spi_ops *)id_entry->driver_data;
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/* ops parameter check */
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if (!ops->set_config_register) {
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dev_err(&pdev->dev, "there is no set_config_register\n");
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return -ENODEV;
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}
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/* get base addr */
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (unlikely(res == NULL)) {
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@ -767,7 +848,7 @@ static int rspi_probe(struct platform_device *pdev)
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rspi = spi_master_get_devdata(master);
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platform_set_drvdata(pdev, rspi);
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rspi->ops = ops;
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rspi->master = master;
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rspi->addr = ioremap(res->start, resource_size(res));
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if (rspi->addr == NULL) {
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@ -776,7 +857,7 @@ static int rspi_probe(struct platform_device *pdev)
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goto error1;
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}
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snprintf(clk_name, sizeof(clk_name), "rspi%d", pdev->id);
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snprintf(clk_name, sizeof(clk_name), "%s%d", id_entry->name, pdev->id);
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rspi->clk = clk_get(&pdev->dev, clk_name);
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if (IS_ERR(rspi->clk)) {
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dev_err(&pdev->dev, "cannot get clock\n");
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@ -790,7 +871,10 @@ static int rspi_probe(struct platform_device *pdev)
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INIT_WORK(&rspi->ws, rspi_work);
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init_waitqueue_head(&rspi->wait);
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master->num_chipselect = 2;
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master->num_chipselect = rspi_pd->num_chipselect;
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if (!master->num_chipselect)
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master->num_chipselect = 2; /* default */
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master->bus_num = pdev->id;
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master->setup = rspi_setup;
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master->transfer = rspi_transfer;
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@ -832,11 +916,28 @@ error1:
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return ret;
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}
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static struct spi_ops rspi_ops = {
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.set_config_register = rspi_set_config_register,
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};
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static struct spi_ops qspi_ops = {
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.set_config_register = qspi_set_config_register,
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};
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static struct platform_device_id spi_driver_ids[] = {
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{ "rspi", (kernel_ulong_t)&rspi_ops },
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{ "qspi", (kernel_ulong_t)&qspi_ops },
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{},
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};
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MODULE_DEVICE_TABLE(platform, spi_driver_ids);
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static struct platform_driver rspi_driver = {
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.probe = rspi_probe,
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.remove = rspi_remove,
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.id_table = spi_driver_ids,
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.driver = {
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.name = "rspi",
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.name = "renesas_spi",
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.owner = THIS_MODULE,
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},
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};
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@ -26,6 +26,8 @@ struct rspi_plat_data {
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unsigned int dma_rx_id;
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unsigned dma_width_16bit:1; /* DMAC read/write width = 16-bit */
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u16 num_chipselect;
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};
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#endif
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