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drm/exynos: add global macro for the default primary plane 

Define DEFAULT_WIN as zero to help set the primary plane on all CRTCs.
Some CRTCs were defining a variable to store the default window, but that
is not necessary as the default (primary) window is always the window zero.

Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
hifive-unleashed-5.1
Gustavo Padovan 2015-10-12 22:07:48 +09:00 committed by Inki Dae
parent c691349ca4
commit 5d3d099574
6 changed files with 13 additions and 18 deletions
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6
drivers/gpu/drm/exynos/exynos5433_drm_decon.c
View File

@ -33,7 +33,6 @@ struct decon_context {
struct exynos_drm_plane planes[WINDOWS_NR];
void __iomem *addr;
struct clk *clks[6];
unsigned int default_win;
unsigned long irq_flags;
int pipe;
bool suspended;
@ -501,7 +500,7 @@ static int decon_bind(struct device *dev, struct device *master, void *data)
ctx->pipe = priv->pipe++;
for (zpos = 0; zpos < WINDOWS_NR; zpos++) {
type = (zpos == ctx->default_win) ? DRM_PLANE_TYPE_PRIMARY :
type = (zpos == DEFAULT_WIN) ? DRM_PLANE_TYPE_PRIMARY :
DRM_PLANE_TYPE_OVERLAY;
ret = exynos_plane_init(drm_dev, &ctx->planes[zpos],
1 << ctx->pipe, type, decon_formats,
@ -510,7 +509,7 @@ static int decon_bind(struct device *dev, struct device *master, void *data)
return ret;
}
exynos_plane = &ctx->planes[ctx->default_win];
exynos_plane = &ctx->planes[DEFAULT_WIN];
ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD,
&decon_crtc_ops, ctx);
@ -607,7 +606,6 @@ static int exynos5433_decon_probe(struct platform_device *pdev)
if (!ctx)
return -ENOMEM;
ctx->default_win = 0;
ctx->suspended = true;
ctx->dev = dev;
if (of_get_child_by_name(dev->of_node, "i80-if-timings"))

5
drivers/gpu/drm/exynos/exynos7_drm_decon.c
View File

@ -51,7 +51,6 @@ struct decon_context {
struct clk *eclk;
struct clk *vclk;
void __iomem *regs;
unsigned int default_win;
unsigned long irq_flags;
bool i80_if;
bool suspended;
@ -690,7 +689,7 @@ static int decon_bind(struct device *dev, struct device *master, void *data)
}
for (zpos = 0; zpos < WINDOWS_NR; zpos++) {
type = (zpos == ctx->default_win) ? DRM_PLANE_TYPE_PRIMARY :
type = (zpos == DEFAULT_WIN) ? DRM_PLANE_TYPE_PRIMARY :
DRM_PLANE_TYPE_OVERLAY;
ret = exynos_plane_init(drm_dev, &ctx->planes[zpos],
1 << ctx->pipe, type, decon_formats,
@ -699,7 +698,7 @@ static int decon_bind(struct device *dev, struct device *master, void *data)
return ret;
}
exynos_plane = &ctx->planes[ctx->default_win];
exynos_plane = &ctx->planes[DEFAULT_WIN];
ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD,
&decon_crtc_ops, ctx);

2
drivers/gpu/drm/exynos/exynos_drm_drv.h
View File

@ -22,6 +22,8 @@
#define MAX_PLANE 5
#define MAX_FB_BUFFER 4
#define DEFAULT_WIN 0
#define to_exynos_crtc(x) container_of(x, struct exynos_drm_crtc, base)
#define to_exynos_plane(x) container_of(x, struct exynos_drm_plane, base)

5
drivers/gpu/drm/exynos/exynos_drm_fimd.c
View File

@ -153,7 +153,6 @@ struct fimd_context {
struct clk *lcd_clk;
void __iomem *regs;
struct regmap *sysreg;
unsigned int default_win;
unsigned long irq_flags;
u32 vidcon0;
u32 vidcon1;
@ -949,7 +948,7 @@ static int fimd_bind(struct device *dev, struct device *master, void *data)
ctx->pipe = priv->pipe++;
for (zpos = 0; zpos < WINDOWS_NR; zpos++) {
type = (zpos == ctx->default_win) ? DRM_PLANE_TYPE_PRIMARY :
type = (zpos == DEFAULT_WIN) ? DRM_PLANE_TYPE_PRIMARY :
DRM_PLANE_TYPE_OVERLAY;
ret = exynos_plane_init(drm_dev, &ctx->planes[zpos],
1 << ctx->pipe, type, fimd_formats,
@ -958,7 +957,7 @@ static int fimd_bind(struct device *dev, struct device *master, void *data)
return ret;
}
exynos_plane = &ctx->planes[ctx->default_win];
exynos_plane = &ctx->planes[DEFAULT_WIN];
ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD,
&fimd_crtc_ops, ctx);

6
drivers/gpu/drm/exynos/exynos_drm_vidi.c
View File

@ -42,7 +42,6 @@ struct vidi_context {
struct exynos_drm_plane planes[WINDOWS_NR];
struct edid *raw_edid;
unsigned int clkdiv;
unsigned int default_win;
unsigned long irq_flags;
unsigned int connected;
bool vblank_on;
@ -446,7 +445,7 @@ static int vidi_bind(struct device *dev, struct device *master, void *data)
vidi_ctx_initialize(ctx, drm_dev);
for (zpos = 0; zpos < WINDOWS_NR; zpos++) {
type = (zpos == ctx->default_win) ? DRM_PLANE_TYPE_PRIMARY :
type = (zpos == DEFAULT_WIN) ? DRM_PLANE_TYPE_PRIMARY :
DRM_PLANE_TYPE_OVERLAY;
ret = exynos_plane_init(drm_dev, &ctx->planes[zpos],
1 << ctx->pipe, type, formats,
@ -455,7 +454,7 @@ static int vidi_bind(struct device *dev, struct device *master, void *data)
return ret;
}
exynos_plane = &ctx->planes[ctx->default_win];
exynos_plane = &ctx->planes[DEFAULT_WIN];
ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
ctx->pipe, EXYNOS_DISPLAY_TYPE_VIDI,
&vidi_crtc_ops, ctx);
@ -507,7 +506,6 @@ static int vidi_probe(struct platform_device *pdev)
if (!ctx)
return -ENOMEM;
ctx->default_win = 0;
ctx->pdev = pdev;
INIT_WORK(&ctx->work, vidi_fake_vblank_handler);

7
drivers/gpu/drm/exynos/exynos_mixer.c
View File

@ -42,7 +42,6 @@
#include "exynos_mixer.h"
#define MIXER_WIN_NR 3
#define MIXER_DEFAULT_WIN 0
#define VP_DEFAULT_WIN 2
/* The pixelformats that are natively supported by the mixer. */
@ -600,7 +599,7 @@ static void mixer_graph_buffer(struct mixer_context *ctx,
/* setup display size */
if (ctx->mxr_ver == MXR_VER_128_0_0_184 &&
win == MIXER_DEFAULT_WIN) {
win == DEFAULT_WIN) {
val = MXR_MXR_RES_HEIGHT(mode->vdisplay);
val |= MXR_MXR_RES_WIDTH(mode->hdisplay);
mixer_reg_write(res, MXR_RESOLUTION, val);
@ -1197,7 +1196,7 @@ static int mixer_bind(struct device *dev, struct device *manager, void *data)
const uint32_t *formats;
unsigned int fcount;
type = (zpos == MIXER_DEFAULT_WIN) ? DRM_PLANE_TYPE_PRIMARY :
type = (zpos == DEFAULT_WIN) ? DRM_PLANE_TYPE_PRIMARY :
DRM_PLANE_TYPE_OVERLAY;
if (zpos < VP_DEFAULT_WIN) {
formats = mixer_formats;
@ -1214,7 +1213,7 @@ static int mixer_bind(struct device *dev, struct device *manager, void *data)
return ret;
}
exynos_plane = &ctx->planes[MIXER_DEFAULT_WIN];
exynos_plane = &ctx->planes[DEFAULT_WIN];
ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
ctx->pipe, EXYNOS_DISPLAY_TYPE_HDMI,
&mixer_crtc_ops, ctx);