drm/amdgpu/vce: simplify vce instance setup
Set the me instance in early init and use that rather than calculating the instance based on the ring pointer. Reviewed-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -56,7 +56,7 @@ static uint64_t vce_v2_0_ring_get_rptr(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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if (ring == &adev->vce.ring[0])
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if (ring->me == 0)
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return RREG32(mmVCE_RB_RPTR);
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else
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return RREG32(mmVCE_RB_RPTR2);
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@ -73,7 +73,7 @@ static uint64_t vce_v2_0_ring_get_wptr(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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if (ring == &adev->vce.ring[0])
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if (ring->me == 0)
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return RREG32(mmVCE_RB_WPTR);
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else
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return RREG32(mmVCE_RB_WPTR2);
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@ -90,7 +90,7 @@ static void vce_v2_0_ring_set_wptr(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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if (ring == &adev->vce.ring[0])
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if (ring->me == 0)
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WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
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else
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WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
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@ -627,8 +627,10 @@ static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev)
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{
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int i;
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for (i = 0; i < adev->vce.num_rings; i++)
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for (i = 0; i < adev->vce.num_rings; i++) {
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adev->vce.ring[i].funcs = &vce_v2_0_ring_funcs;
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adev->vce.ring[i].me = i;
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}
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}
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static const struct amdgpu_irq_src_funcs vce_v2_0_irq_funcs = {
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@ -86,9 +86,9 @@ static uint64_t vce_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
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else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0)
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WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));
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if (ring == &adev->vce.ring[0])
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if (ring->me == 0)
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v = RREG32(mmVCE_RB_RPTR);
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else if (ring == &adev->vce.ring[1])
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else if (ring->me == 1)
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v = RREG32(mmVCE_RB_RPTR2);
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else
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v = RREG32(mmVCE_RB_RPTR3);
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@ -118,9 +118,9 @@ static uint64_t vce_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
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else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0)
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WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));
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if (ring == &adev->vce.ring[0])
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if (ring->me == 0)
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v = RREG32(mmVCE_RB_WPTR);
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else if (ring == &adev->vce.ring[1])
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else if (ring->me == 1)
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v = RREG32(mmVCE_RB_WPTR2);
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else
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v = RREG32(mmVCE_RB_WPTR3);
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@ -149,9 +149,9 @@ static void vce_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
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else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0)
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WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));
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if (ring == &adev->vce.ring[0])
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if (ring->me == 0)
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WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
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else if (ring == &adev->vce.ring[1])
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else if (ring->me == 1)
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WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
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else
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WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr));
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@ -942,12 +942,16 @@ static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev)
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int i;
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if (adev->asic_type >= CHIP_STONEY) {
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for (i = 0; i < adev->vce.num_rings; i++)
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for (i = 0; i < adev->vce.num_rings; i++) {
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adev->vce.ring[i].funcs = &vce_v3_0_ring_vm_funcs;
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adev->vce.ring[i].me = i;
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}
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DRM_INFO("VCE enabled in VM mode\n");
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} else {
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for (i = 0; i < adev->vce.num_rings; i++)
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for (i = 0; i < adev->vce.num_rings; i++) {
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adev->vce.ring[i].funcs = &vce_v3_0_ring_phys_funcs;
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adev->vce.ring[i].me = i;
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}
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DRM_INFO("VCE enabled in physical mode\n");
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}
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}
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@ -60,9 +60,9 @@ static uint64_t vce_v4_0_ring_get_rptr(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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if (ring == &adev->vce.ring[0])
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if (ring->me == 0)
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return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR));
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else if (ring == &adev->vce.ring[1])
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else if (ring->me == 1)
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return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR2));
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else
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return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR3));
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@ -82,9 +82,9 @@ static uint64_t vce_v4_0_ring_get_wptr(struct amdgpu_ring *ring)
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if (ring->use_doorbell)
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return adev->wb.wb[ring->wptr_offs];
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if (ring == &adev->vce.ring[0])
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if (ring->me == 0)
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return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR));
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else if (ring == &adev->vce.ring[1])
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else if (ring->me == 1)
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return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2));
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else
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return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR3));
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@ -108,10 +108,10 @@ static void vce_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
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return;
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}
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if (ring == &adev->vce.ring[0])
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if (ring->me == 0)
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WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR),
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lower_32_bits(ring->wptr));
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else if (ring == &adev->vce.ring[1])
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else if (ring->me == 1)
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WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2),
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lower_32_bits(ring->wptr));
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else
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@ -1088,8 +1088,10 @@ static void vce_v4_0_set_ring_funcs(struct amdgpu_device *adev)
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{
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int i;
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for (i = 0; i < adev->vce.num_rings; i++)
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for (i = 0; i < adev->vce.num_rings; i++) {
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adev->vce.ring[i].funcs = &vce_v4_0_ring_vm_funcs;
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adev->vce.ring[i].me = i;
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}
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DRM_INFO("VCE enabled in VM mode\n");
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}
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