drm/i915: dvo needs a P2 divisor of 4
Section 1.5.4, "DPLL A Control Register" from Bspec about bit 23 "FPA0/A1 P2 Clock Divide": 0 = Divide by 2 1 = Divide by 4. This bit must be set in DVO non-gang mode So copy the current limits (which should be good for i8xx) and create a new set for dvo encoders. Reviewed-by: Chris Wilson <chris@chris-wilson.oc.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -89,7 +89,7 @@ intel_fdi_link_freq(struct drm_device *dev)
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return 27;
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}
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static const intel_limit_t intel_limits_i8xx_dvo = {
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static const intel_limit_t intel_limits_i8xx_dac = {
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.dot = { .min = 25000, .max = 350000 },
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.vco = { .min = 930000, .max = 1400000 },
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.n = { .min = 3, .max = 16 },
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@ -102,6 +102,19 @@ static const intel_limit_t intel_limits_i8xx_dvo = {
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.p2_slow = 4, .p2_fast = 2 },
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};
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static const intel_limit_t intel_limits_i8xx_dvo = {
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.dot = { .min = 25000, .max = 350000 },
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.vco = { .min = 930000, .max = 1400000 },
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.n = { .min = 3, .max = 16 },
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.m = { .min = 96, .max = 140 },
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.m1 = { .min = 18, .max = 26 },
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.m2 = { .min = 6, .max = 16 },
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.p = { .min = 4, .max = 128 },
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.p1 = { .min = 2, .max = 33 },
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.p2 = { .dot_limit = 165000,
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.p2_slow = 4, .p2_fast = 4 },
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};
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static const intel_limit_t intel_limits_i8xx_lvds = {
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.dot = { .min = 25000, .max = 350000 },
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.vco = { .min = 930000, .max = 1400000 },
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@ -410,8 +423,10 @@ static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
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} else {
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if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
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limit = &intel_limits_i8xx_lvds;
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else
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else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
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limit = &intel_limits_i8xx_dvo;
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else
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limit = &intel_limits_i8xx_dac;
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}
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return limit;
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}
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