From e9920bc28a4f9d677f1cf49223142a405c4d615f Mon Sep 17 00:00:00 2001 From: Lukasz Luba Date: Wed, 21 Aug 2019 12:42:56 +0200 Subject: [PATCH 01/10] dt-bindings: ddr: Rename lpddr2 directory Change directory name to be ready for new types of memories. Signed-off-by: Lukasz Luba Reviewed-by: Rob Herring Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/{lpddr2 => ddr}/lpddr2-timings.txt | 0 Documentation/devicetree/bindings/{lpddr2 => ddr}/lpddr2.txt | 2 +- 2 files changed, 1 insertion(+), 1 deletion(-) rename Documentation/devicetree/bindings/{lpddr2 => ddr}/lpddr2-timings.txt (100%) rename Documentation/devicetree/bindings/{lpddr2 => ddr}/lpddr2.txt (96%) diff --git a/Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt b/Documentation/devicetree/bindings/ddr/lpddr2-timings.txt similarity index 100% rename from Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt rename to Documentation/devicetree/bindings/ddr/lpddr2-timings.txt diff --git a/Documentation/devicetree/bindings/lpddr2/lpddr2.txt b/Documentation/devicetree/bindings/ddr/lpddr2.txt similarity index 96% rename from Documentation/devicetree/bindings/lpddr2/lpddr2.txt rename to Documentation/devicetree/bindings/ddr/lpddr2.txt index 58354a075e13..ddd40121e6f6 100644 --- a/Documentation/devicetree/bindings/lpddr2/lpddr2.txt +++ b/Documentation/devicetree/bindings/ddr/lpddr2.txt @@ -36,7 +36,7 @@ Child nodes: "lpddr2-timings" provides AC timing parameters of the device for a given speed-bin. The user may provide the timings for as many speed-bins as is required. Please see Documentation/devicetree/ - bindings/lpddr2/lpddr2-timings.txt for more information on "lpddr2-timings" + bindings/ddr/lpddr2-timings.txt for more information on "lpddr2-timings" Example: From 1d816d3454427481b08a6bbc16287b1aba395672 Mon Sep 17 00:00:00 2001 From: Lukasz Luba Date: Wed, 21 Aug 2019 12:42:57 +0200 Subject: [PATCH 02/10] dt-bindings: ddr: Add bindings for LPDDR3 memories Specifies the AC timing parameters of the LPDDR3 memory device. Signed-off-by: Lukasz Luba Reviewed-by: Rob Herring Signed-off-by: Krzysztof Kozlowski --- .../bindings/ddr/lpddr3-timings.txt | 58 +++++++++++ .../devicetree/bindings/ddr/lpddr3.txt | 97 +++++++++++++++++++ 2 files changed, 155 insertions(+) create mode 100644 Documentation/devicetree/bindings/ddr/lpddr3-timings.txt create mode 100644 Documentation/devicetree/bindings/ddr/lpddr3.txt diff --git a/Documentation/devicetree/bindings/ddr/lpddr3-timings.txt b/Documentation/devicetree/bindings/ddr/lpddr3-timings.txt new file mode 100644 index 000000000000..84705e50a3fd --- /dev/null +++ b/Documentation/devicetree/bindings/ddr/lpddr3-timings.txt @@ -0,0 +1,58 @@ +* AC timing parameters of LPDDR3 memories for a given speed-bin. + +The structures are based on LPDDR2 and extended where needed. + +Required properties: +- compatible : Should be "jedec,lpddr3-timings" +- min-freq : minimum DDR clock frequency for the speed-bin. Type is +- reg : maximum DDR clock frequency for the speed-bin. Type is + +Optional properties: + +The following properties represent AC timing parameters from the memory +data-sheet of the device for a given speed-bin. All these properties are +of type and the default unit is ps (pico seconds). +- tRFC +- tRRD +- tRPab +- tRPpb +- tRCD +- tRC +- tRAS +- tWTR +- tWR +- tRTP +- tW2W-C2C +- tR2R-C2C +- tFAW +- tXSR +- tXP +- tCKE +- tCKESR +- tMRD + +Example: + +timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 { + compatible = "jedec,lpddr3-timings"; + reg = <800000000>; /* workaround: it shows max-freq */ + min-freq = <100000000>; + tRFC = <65000>; + tRRD = <6000>; + tRPab = <12000>; + tRPpb = <12000>; + tRCD = <10000>; + tRC = <33750>; + tRAS = <23000>; + tWTR = <3750>; + tWR = <7500>; + tRTP = <3750>; + tW2W-C2C = <0>; + tR2R-C2C = <0>; + tFAW = <25000>; + tXSR = <70000>; + tXP = <3750>; + tCKE = <3750>; + tCKESR = <3750>; + tMRD = <7000>; +}; diff --git a/Documentation/devicetree/bindings/ddr/lpddr3.txt b/Documentation/devicetree/bindings/ddr/lpddr3.txt new file mode 100644 index 000000000000..3b2485b84b3f --- /dev/null +++ b/Documentation/devicetree/bindings/ddr/lpddr3.txt @@ -0,0 +1,97 @@ +* LPDDR3 SDRAM memories compliant to JEDEC JESD209-3C + +Required properties: +- compatible : Should be - "jedec,lpddr3" +- density : representing density in Mb (Mega bits) +- io-width : representing bus width. Possible values are 8, 16, 32, 64 +- #address-cells: Must be set to 1 +- #size-cells: Must be set to 0 + +Optional properties: + +The following optional properties represent the minimum value of some AC +timing parameters of the DDR device in terms of number of clock cycles. +These values shall be obtained from the device data-sheet. +- tRFC-min-tck +- tRRD-min-tck +- tRPab-min-tck +- tRPpb-min-tck +- tRCD-min-tck +- tRC-min-tck +- tRAS-min-tck +- tWTR-min-tck +- tWR-min-tck +- tRTP-min-tck +- tW2W-C2C-min-tck +- tR2R-C2C-min-tck +- tWL-min-tck +- tDQSCK-min-tck +- tRL-min-tck +- tFAW-min-tck +- tXSR-min-tck +- tXP-min-tck +- tCKE-min-tck +- tCKESR-min-tck +- tMRD-min-tck + +Child nodes: +- The lpddr3 node may have one or more child nodes of type "lpddr3-timings". + "lpddr3-timings" provides AC timing parameters of the device for + a given speed-bin. Please see Documentation/devicetree/ + bindings/ddr/lpddr3-timings.txt for more information on "lpddr3-timings" + +Example: + +samsung_K3QF2F20DB: lpddr3 { + compatible = "Samsung,K3QF2F20DB", "jedec,lpddr3"; + density = <16384>; + io-width = <32>; + #address-cells = <1>; + #size-cells = <0>; + + tRFC-min-tck = <17>; + tRRD-min-tck = <2>; + tRPab-min-tck = <2>; + tRPpb-min-tck = <2>; + tRCD-min-tck = <3>; + tRC-min-tck = <6>; + tRAS-min-tck = <5>; + tWTR-min-tck = <2>; + tWR-min-tck = <7>; + tRTP-min-tck = <2>; + tW2W-C2C-min-tck = <0>; + tR2R-C2C-min-tck = <0>; + tWL-min-tck = <8>; + tDQSCK-min-tck = <5>; + tRL-min-tck = <14>; + tFAW-min-tck = <5>; + tXSR-min-tck = <12>; + tXP-min-tck = <2>; + tCKE-min-tck = <2>; + tCKESR-min-tck = <2>; + tMRD-min-tck = <5>; + + timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 { + compatible = "jedec,lpddr3-timings"; + reg = <800000000>; /* workaround: it shows max-freq */ + min-freq = <100000000>; + tRFC = <65000>; + tRRD = <6000>; + tRPab = <12000>; + tRPpb = <12000>; + tRCD = <10000>; + tRC = <33750>; + tRAS = <23000>; + tWTR = <3750>; + tWR = <7500>; + tRTP = <3750>; + tW2W-C2C = <0>; + tR2R-C2C = <0>; + tFAW = <25000>; + tXSR = <70000>; + tXP = <3750>; + tCKE = <3750>; + tCKESR = <3750>; + tMRD = <7000>; + }; +} From c6d46248cd15f519e83398aef433884238f93c36 Mon Sep 17 00:00:00 2001 From: Lukasz Luba Date: Wed, 21 Aug 2019 12:42:59 +0200 Subject: [PATCH 03/10] dt-bindings: memory-controllers: Add Exynos5422 DMC device description Add device tree bindings for a new Exynos5422 Dynamic Memory Controller device. Signed-off-by: Lukasz Luba Reviewed-by: Rob Herring Signed-off-by: Krzysztof Kozlowski --- .../memory-controllers/exynos5422-dmc.txt | 73 +++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt diff --git a/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt new file mode 100644 index 000000000000..02aeb3b5a820 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt @@ -0,0 +1,73 @@ +* Exynos5422 frequency and voltage scaling for Dynamic Memory Controller device + +The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the DRAM +memory chips are connected. The driver is to monitor the controller in runtime +and switch frequency and voltage. To monitor the usage of the controller in +runtime, the driver uses the PPMU (Platform Performance Monitoring Unit), which +is able to measure the current load of the memory. +When 'userspace' governor is used for the driver, an application is able to +switch the DMC and memory frequency. + +Required properties for DMC device for Exynos5422: +- compatible: Should be "samsung,exynos5422-dmc". +- clocks : list of clock specifiers, must contain an entry for each + required entry in clock-names for CLK_FOUT_SPLL, CLK_MOUT_SCLK_SPLL, + CLK_FF_DOUT_SPLL2, CLK_FOUT_BPLL, CLK_MOUT_BPLL, CLK_SCLK_BPLL, + CLK_MOUT_MX_MSPLL_CCORE, CLK_MOUT_MX_MSPLL_CCORE_PHY, CLK_MOUT_MCLK_CDREX, +- clock-names : should include "fout_spll", "mout_sclk_spll", "ff_dout_spll2", + "fout_bpll", "mout_bpll", "sclk_bpll", "mout_mx_mspll_ccore", + "mout_mclk_cdrex" entries +- devfreq-events : phandles for PPMU devices connected to this DMC. +- vdd-supply : phandle for voltage regulator which is connected. +- reg : registers of two CDREX controllers. +- operating-points-v2 : phandle for OPPs described in v2 definition. +- device-handle : phandle of the connected DRAM memory device. For more + information please refer to documentation file: + Documentation/devicetree/bindings/ddr/lpddr3.txt +- devfreq-events : phandles of the PPMU events used by the controller. +- samsung,syscon-clk : phandle of the clock register set used by the controller, + these registers are used for enabling a 'pause' feature and are not + exposed by clock framework but they must be used in a safe way. + The register offsets are in the driver code and specyfic for this SoC + type. + +Example: + + ppmu_dmc0_0: ppmu@10d00000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d00000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX0_0>; + clock-names = "ppmu"; + events { + ppmu_event_dmc0_0: ppmu-event3-dmc0_0 { + event-name = "ppmu-event3-dmc0_0"; + }; + }; + }; + + dmc: memory-controller@10c20000 { + compatible = "samsung,exynos5422-dmc"; + reg = <0x10c20000 0x100>, <0x10c30000 0x100>, + clocks = <&clock CLK_FOUT_SPLL>, + <&clock CLK_MOUT_SCLK_SPLL>, + <&clock CLK_FF_DOUT_SPLL2>, + <&clock CLK_FOUT_BPLL>, + <&clock CLK_MOUT_BPLL>, + <&clock CLK_SCLK_BPLL>, + <&clock CLK_MOUT_MX_MSPLL_CCORE>, + <&clock CLK_MOUT_MCLK_CDREX>, + clock-names = "fout_spll", + "mout_sclk_spll", + "ff_dout_spll2", + "fout_bpll", + "mout_bpll", + "sclk_bpll", + "mout_mx_mspll_ccore", + "mout_mclk_cdrex", + operating-points-v2 = <&dmc_opp_table>; + devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>, + <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>; + device-handle = <&samsung_K3QF2F20DB>; + vdd-supply = <&buck1_reg>; + samsung,syscon-clk = <&clock>; + }; From 53d2ebcc73cde1268285bc2b99b4a5c915afe73a Mon Sep 17 00:00:00 2001 From: Lukasz Luba Date: Wed, 21 Aug 2019 12:43:01 +0200 Subject: [PATCH 04/10] ARM: dts: exynos: Add syscon compatible to clock controller on Exynos542x In order to get the clock by phandle and use it with regmap it needs to be compatible with syscon. The DMC driver uses two registers from clock register set and needs the regmap of them. Signed-off-by: Lukasz Luba Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5420.dtsi | 2 +- arch/arm/boot/dts/exynos5800.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 7d51e0f4ab79..a43970b3fc83 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -175,7 +175,7 @@ }; clock: clock-controller@10010000 { - compatible = "samsung,exynos5420-clock"; + compatible = "samsung,exynos5420-clock", "syscon"; reg = <0x10010000 0x30000>; #clock-cells = <1>; }; diff --git a/arch/arm/boot/dts/exynos5800.dtsi b/arch/arm/boot/dts/exynos5800.dtsi index de639eecc5c9..16177d815ee4 100644 --- a/arch/arm/boot/dts/exynos5800.dtsi +++ b/arch/arm/boot/dts/exynos5800.dtsi @@ -17,7 +17,7 @@ }; &clock { - compatible = "samsung,exynos5800-clock"; + compatible = "samsung,exynos5800-clock", "syscon"; }; &cluster_a15_opp_table { From 5cb4d9a02a607943182b8382c97db81d9cebc02e Mon Sep 17 00:00:00 2001 From: Lukasz Luba Date: Wed, 21 Aug 2019 12:43:02 +0200 Subject: [PATCH 05/10] ARM: dts: exynos: Add DMC device to Exynos5422 and Odroid XU3-family boards Add description of Dynamic Memory Controller and PPMU counters to Exynos5422 and Odroid XU3/XU4/HC1 boards. They are used by exynos5422-dmc driver. There is a definition of the memory chip, which is then used during calculation of timings for each OPP. The algorithm in the driver needs these two sets to bound the timings. Signed-off-by: Lukasz Luba Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5420.dtsi | 71 +++++++++++ arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 117 ++++++++++++++++++ 2 files changed, 188 insertions(+) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index a43970b3fc83..92c5e0d8a824 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -237,6 +237,29 @@ status = "disabled"; }; + dmc: memory-controller@10c20000 { + compatible = "samsung,exynos5422-dmc"; + reg = <0x10c20000 0x100>, <0x10c30000 0x100>; + clocks = <&clock CLK_FOUT_SPLL>, + <&clock CLK_MOUT_SCLK_SPLL>, + <&clock CLK_FF_DOUT_SPLL2>, + <&clock CLK_FOUT_BPLL>, + <&clock CLK_MOUT_BPLL>, + <&clock CLK_SCLK_BPLL>, + <&clock CLK_MOUT_MX_MSPLL_CCORE>, + <&clock CLK_MOUT_MCLK_CDREX>; + clock-names = "fout_spll", + "mout_sclk_spll", + "ff_dout_spll2", + "fout_bpll", + "mout_bpll", + "sclk_bpll", + "mout_mx_mspll_ccore", + "mout_mclk_cdrex"; + samsung,syscon-clk = <&clock>; + status = "disabled"; + }; + nocp_mem0_0: nocp@10ca1000 { compatible = "samsung,exynos5420-nocp"; reg = <0x10CA1000 0x200>; @@ -273,6 +296,54 @@ status = "disabled"; }; + ppmu_dmc0_0: ppmu@10d00000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d00000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX0_0>; + clock-names = "ppmu"; + events { + ppmu_event3_dmc0_0: ppmu-event3-dmc0_0 { + event-name = "ppmu-event3-dmc0_0"; + }; + }; + }; + + ppmu_dmc0_1: ppmu@10d10000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d10000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX0_1>; + clock-names = "ppmu"; + events { + ppmu_event3_dmc0_1: ppmu-event3-dmc0_1 { + event-name = "ppmu-event3-dmc0_1"; + }; + }; + }; + + ppmu_dmc1_0: ppmu@10d60000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d60000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX1_0>; + clock-names = "ppmu"; + events { + ppmu_event3_dmc1_0: ppmu-event3-dmc1_0 { + event-name = "ppmu-event3-dmc1_0"; + }; + }; + }; + + ppmu_dmc1_1: ppmu@10d70000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d70000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX1_1>; + clock-names = "ppmu"; + events { + ppmu_event3_dmc1_1: ppmu-event3-dmc1_1 { + event-name = "ppmu-event3-dmc1_1"; + }; + }; + }; + gsc_pd: power-domain@10044000 { compatible = "samsung,exynos4210-pd"; reg = <0x10044000 0x20>; diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index 829147e320e0..059fa32d1a8f 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -34,6 +34,98 @@ clock-frequency = <24000000>; }; }; + + dmc_opp_table: opp_table2 { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <165000000>; + opp-microvolt = <875000>; + }; + opp01 { + opp-hz = /bits/ 64 <206000000>; + opp-microvolt = <875000>; + }; + opp02 { + opp-hz = /bits/ 64 <275000000>; + opp-microvolt = <875000>; + }; + opp03 { + opp-hz = /bits/ 64 <413000000>; + opp-microvolt = <887500>; + }; + opp04 { + opp-hz = /bits/ 64 <543000000>; + opp-microvolt = <937500>; + }; + opp05 { + opp-hz = /bits/ 64 <633000000>; + opp-microvolt = <1012500>; + }; + opp06 { + opp-hz = /bits/ 64 <728000000>; + opp-microvolt = <1037500>; + }; + opp07 { + opp-hz = /bits/ 64 <825000000>; + opp-microvolt = <1050000>; + }; + }; + + samsung_K3QF2F20DB: lpddr3 { + compatible = "samsung,K3QF2F20DB", "jedec,lpddr3"; + density = <16384>; + io-width = <32>; + #address-cells = <1>; + #size-cells = <0>; + + tRFC-min-tck = <17>; + tRRD-min-tck = <2>; + tRPab-min-tck = <2>; + tRPpb-min-tck = <2>; + tRCD-min-tck = <3>; + tRC-min-tck = <6>; + tRAS-min-tck = <5>; + tWTR-min-tck = <2>; + tWR-min-tck = <7>; + tRTP-min-tck = <2>; + tW2W-C2C-min-tck = <0>; + tR2R-C2C-min-tck = <0>; + tWL-min-tck = <8>; + tDQSCK-min-tck = <5>; + tRL-min-tck = <14>; + tFAW-min-tck = <5>; + tXSR-min-tck = <12>; + tXP-min-tck = <2>; + tCKE-min-tck = <2>; + tCKESR-min-tck = <2>; + tMRD-min-tck = <5>; + + timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 { + compatible = "jedec,lpddr3-timings"; + /* workaround: 'reg' shows max-freq */ + reg = <800000000>; + min-freq = <100000000>; + tRFC = <65000>; + tRRD = <6000>; + tRPab = <12000>; + tRPpb = <12000>; + tRCD = <10000>; + tRC = <33750>; + tRAS = <23000>; + tWTR = <3750>; + tWR = <7500>; + tRTP = <3750>; + tW2W-C2C = <0>; + tR2R-C2C = <0>; + tFAW = <25000>; + tXSR = <70000>; + tXP = <3750>; + tCKE = <3750>; + tCKESR = <3750>; + tMRD = <7000>; + }; + }; }; &adc { @@ -132,6 +224,15 @@ cpu-supply = <&buck2_reg>; }; +&dmc { + devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>, + <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>; + device-handle = <&samsung_K3QF2F20DB>; + operating-points-v2 = <&dmc_opp_table>; + vdd-supply = <&buck1_reg>; + status = "okay"; +}; + &hsi2c_4 { status = "okay"; @@ -634,6 +735,22 @@ }; }; +&ppmu_dmc0_0 { + status = "okay"; +}; + +&ppmu_dmc0_1 { + status = "okay"; +}; + +&ppmu_dmc1_0 { + status = "okay"; +}; + +&ppmu_dmc1_1 { + status = "okay"; +}; + &tmu_cpu0 { vtmu-supply = <&ldo7_reg>; }; From 296523d933060cad754626c751dc20f64dba7d01 Mon Sep 17 00:00:00 2001 From: Lukasz Luba Date: Thu, 19 Sep 2019 11:26:41 +0200 Subject: [PATCH 06/10] dt-bindings: ddr: Add bindings for Samsung LPDDR3 memories Add compatible for Samsung k3qf2f20db LPDDR3 memory bindings, based on at25.txt compatible section. Introduce minor fixes in the old documentation. Suggested-by: Krzysztof Kozlowski Signed-off-by: Lukasz Luba Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/ddr/lpddr3.txt | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/ddr/lpddr3.txt b/Documentation/devicetree/bindings/ddr/lpddr3.txt index 3b2485b84b3f..a0eda35a86ee 100644 --- a/Documentation/devicetree/bindings/ddr/lpddr3.txt +++ b/Documentation/devicetree/bindings/ddr/lpddr3.txt @@ -1,7 +1,10 @@ * LPDDR3 SDRAM memories compliant to JEDEC JESD209-3C Required properties: -- compatible : Should be - "jedec,lpddr3" +- compatible : Should be ",", and generic value "jedec,lpddr3". + Example "," values: + "samsung,K3QF2F20DB" + - density : representing density in Mb (Mega bits) - io-width : representing bus width. Possible values are 8, 16, 32, 64 - #address-cells: Must be set to 1 @@ -43,7 +46,7 @@ Child nodes: Example: samsung_K3QF2F20DB: lpddr3 { - compatible = "Samsung,K3QF2F20DB", "jedec,lpddr3"; + compatible = "samsung,K3QF2F20DB", "jedec,lpddr3"; density = <16384>; io-width = <32>; #address-cells = <1>; @@ -73,7 +76,8 @@ samsung_K3QF2F20DB: lpddr3 { timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 { compatible = "jedec,lpddr3-timings"; - reg = <800000000>; /* workaround: it shows max-freq */ + /* workaround: 'reg' shows max-freq */ + reg = <800000000>; min-freq = <100000000>; tRFC = <65000>; tRRD = <6000>; From 40192209b96b65ff3588e063c5b984e946baaaae Mon Sep 17 00:00:00 2001 From: Lukasz Luba Date: Wed, 2 Oct 2019 08:04:52 +0200 Subject: [PATCH 07/10] dt-bindings: memory-controllers: exynos5422-dmc: Add interrupt mode Add description for optional interrupt lines. It provides a new operation mode, which uses internal performance counters interrupt when overflow. This is more reliable than using default polling mode implemented in devfreq. Signed-off-by: Lukasz Luba Signed-off-by: Krzysztof Kozlowski --- .../bindings/memory-controllers/exynos5422-dmc.txt | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt index 02aeb3b5a820..e2434cac4858 100644 --- a/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt @@ -31,6 +31,14 @@ Required properties for DMC device for Exynos5422: The register offsets are in the driver code and specyfic for this SoC type. +Optional properties for DMC device for Exynos5422: +- interrupt-parent : The parent interrupt controller. +- interrupts : Contains the IRQ line numbers for the DMC internal performance + event counters in DREX0 and DREX1 channels. Align with specification of the + interrupt line(s) in the interrupt-parent controller. +- interrupt-names : IRQ names "drex_0" and "drex_1", the order should be the + same as in the 'interrupts' list above. + Example: ppmu_dmc0_0: ppmu@10d00000 { @@ -70,4 +78,7 @@ Example: device-handle = <&samsung_K3QF2F20DB>; vdd-supply = <&buck1_reg>; samsung,syscon-clk = <&clock>; + interrupt-parent = <&combiner>; + interrupts = <16 0>, <16 1>; + interrupt-names = "drex_0", "drex_1"; }; From 63cf62ddb983c97d19815bb3a480e05ccd9c52b6 Mon Sep 17 00:00:00 2001 From: Lukasz Luba Date: Wed, 2 Oct 2019 08:04:52 +0200 Subject: [PATCH 08/10] ARM: dts: exynos: Extend mapped region for DMC on Exynos5422 DMC Adaptive Voltage and Frequency Scaling driver in interrupt mode needs to access registers at address offset near 0x10000. These registers are private DMC performance counters, which might be used as interrupt trigger when overflow. Potential usage is to skip polling in devfreq framework and switch to interrupt managed bandwidth control. Signed-off-by: Lukasz Luba Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5420.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 92c5e0d8a824..3293807b99ad 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -239,7 +239,7 @@ dmc: memory-controller@10c20000 { compatible = "samsung,exynos5422-dmc"; - reg = <0x10c20000 0x100>, <0x10c30000 0x100>; + reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>; clocks = <&clock CLK_FOUT_SPLL>, <&clock CLK_MOUT_SCLK_SPLL>, <&clock CLK_FF_DOUT_SPLL2>, From 8611ed7ad5866dea0c75e08e7a2b34722db35426 Mon Sep 17 00:00:00 2001 From: Lukasz Luba Date: Wed, 2 Oct 2019 08:04:53 +0200 Subject: [PATCH 09/10] ARM: dts: exynos: Add interrupts to DMC controller in Exynos5422 Add interrupts to Dynamic Memory Controller in Exynos5422 and Odroid XU3-family boards. It will be used instead of devfreq polling mode governor. The interrupt is connected to performance counters private for DMC, which might track utilisation of the memory channels. Signed-off-by: Lukasz Luba Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5420.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 3293807b99ad..c829bbdc5711 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -240,6 +240,9 @@ dmc: memory-controller@10c20000 { compatible = "samsung,exynos5422-dmc"; reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>; + interrupt-parent = <&combiner>; + interrupts = <16 0>, <16 1>; + interrupt-names = "drex_0", "drex_1"; clocks = <&clock CLK_FOUT_SPLL>, <&clock CLK_MOUT_SCLK_SPLL>, <&clock CLK_FF_DOUT_SPLL2>, From 41f277be1d028e64fb8d5e91a7ce74df600bde54 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 2 Oct 2019 19:44:01 +0200 Subject: [PATCH 10/10] dt-bindings: memory-controllers: exynos5422-dmc: Correct example syntax and memory region After adding the interrupt properties to Exynos5422 DMC bindings example, the mapped memory region must be big enough to access performance counters registers. Fix also syntax errors (semicolons) and adjust indentation. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Lukasz Luba --- .../bindings/memory-controllers/exynos5422-dmc.txt | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt index e2434cac4858..02e4a1f862f1 100644 --- a/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt @@ -55,7 +55,7 @@ Example: dmc: memory-controller@10c20000 { compatible = "samsung,exynos5422-dmc"; - reg = <0x10c20000 0x100>, <0x10c30000 0x100>, + reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>; clocks = <&clock CLK_FOUT_SPLL>, <&clock CLK_MOUT_SCLK_SPLL>, <&clock CLK_FF_DOUT_SPLL2>, @@ -63,7 +63,7 @@ Example: <&clock CLK_MOUT_BPLL>, <&clock CLK_SCLK_BPLL>, <&clock CLK_MOUT_MX_MSPLL_CCORE>, - <&clock CLK_MOUT_MCLK_CDREX>, + <&clock CLK_MOUT_MCLK_CDREX>; clock-names = "fout_spll", "mout_sclk_spll", "ff_dout_spll2", @@ -71,10 +71,10 @@ Example: "mout_bpll", "sclk_bpll", "mout_mx_mspll_ccore", - "mout_mclk_cdrex", + "mout_mclk_cdrex"; operating-points-v2 = <&dmc_opp_table>; devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>, - <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>; + <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>; device-handle = <&samsung_K3QF2F20DB>; vdd-supply = <&buck1_reg>; samsung,syscon-clk = <&clock>;