gpio: lpc18xx: add GPIO pin interrupt controller support
The change adds support of LPC18xx/LPC43xx GPIO pin interrupt controller block within SoC GPIO controller. The new interrupt controller driver allows to configure and capture edge or level interrupts on 8 arbitrary selectedinput GPIO pins, and lift the signals to be reported as NVIC rising edge interrupts. Configuration of a particular GPIO pin to serve as interrupt and its mapping to an interrupt on NVIC is done by SCU pin controller, for more details see description of 'nxp,gpio-pin-interrupt' device tree property of a GPIO pin [1]. From LPC18xx and LPC43xx User Manuals the GPIO controller consists of the following blocks: * GPIO pin interrupt block at 0x40087000, this change adds its support, * GPIO GROUP0 interrupt block at 0x40088000, * GPIO GROUP1 interrupt block at 0x40089000, * GPIO port block at 0x400F4000, it is supported by the original driver. While all 4 sub-controller blocks have their own I/O addresses, moreover all 3 interrupt blocks are APB0 peripherals and high-speed GPIO block is an AHB slave, according to the hardware manual the GPIO controller is seen as a single block, and 4 sub-controllers have the shared reset signal RGU #28 and clock to register interface CLK_CPU_GPIO on CCU1. Likely support of two GPIO group interrupt blocks won't be added in short term, because the mechanism to mask several interrupt sources is not well defined. [1] Documentation/devicetree/bindings/pinctrl/nxp,lpc1850-scu.txt Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>hifive-unleashed-5.1
Vladimir Zapolskiy
Linus Walleij
parent
985d8d5c76
commit
5ddabfe8d3
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@ -288,6 +288,7 @@ config GPIO_LPC18XX
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tristate "NXP LPC18XX/43XX GPIO support"
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default y if ARCH_LPC18XX
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depends on OF_GPIO && (ARCH_LPC18XX || COMPILE_TEST)
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select IRQ_DOMAIN_HIERARCHY
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help
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Select this option to enable GPIO driver for
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NXP LPC18XX/43XX devices.
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@ -2,6 +2,7 @@
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/*
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* GPIO driver for NXP LPC18xx/43xx.
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*
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* Copyright (C) 2018 Vladimir Zapolskiy <vz@mleia.com>
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* Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
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*
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*/
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@ -9,9 +10,13 @@
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#include <linux/clk.h>
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#include <linux/gpio/driver.h>
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#include <linux/io.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_gpio.h>
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#include <linux/of_irq.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/platform_device.h>
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@ -21,13 +26,247 @@
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#define LPC18XX_MAX_PORTS 8
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#define LPC18XX_PINS_PER_PORT 32
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/* LPC18xx GPIO pin interrupt controller register offsets */
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#define LPC18XX_GPIO_PIN_IC_ISEL 0x00
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#define LPC18XX_GPIO_PIN_IC_IENR 0x04
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#define LPC18XX_GPIO_PIN_IC_SIENR 0x08
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#define LPC18XX_GPIO_PIN_IC_CIENR 0x0c
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#define LPC18XX_GPIO_PIN_IC_IENF 0x10
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#define LPC18XX_GPIO_PIN_IC_SIENF 0x14
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#define LPC18XX_GPIO_PIN_IC_CIENF 0x18
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#define LPC18XX_GPIO_PIN_IC_RISE 0x1c
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#define LPC18XX_GPIO_PIN_IC_FALL 0x20
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#define LPC18XX_GPIO_PIN_IC_IST 0x24
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#define NR_LPC18XX_GPIO_PIN_IC_IRQS 8
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struct lpc18xx_gpio_pin_ic {
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void __iomem *base;
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struct irq_domain *domain;
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struct raw_spinlock lock;
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};
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struct lpc18xx_gpio_chip {
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struct gpio_chip gpio;
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void __iomem *base;
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struct clk *clk;
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struct lpc18xx_gpio_pin_ic *pin_ic;
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spinlock_t lock;
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};
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static inline void lpc18xx_gpio_pin_ic_isel(struct lpc18xx_gpio_pin_ic *ic,
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u32 pin, bool set)
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{
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u32 val = readl_relaxed(ic->base + LPC18XX_GPIO_PIN_IC_ISEL);
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if (set)
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val &= ~BIT(pin);
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else
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val |= BIT(pin);
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writel_relaxed(val, ic->base + LPC18XX_GPIO_PIN_IC_ISEL);
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}
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static inline void lpc18xx_gpio_pin_ic_set(struct lpc18xx_gpio_pin_ic *ic,
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u32 pin, u32 reg)
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{
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writel_relaxed(BIT(pin), ic->base + reg);
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}
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static void lpc18xx_gpio_pin_ic_mask(struct irq_data *d)
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{
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struct lpc18xx_gpio_pin_ic *ic = d->chip_data;
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u32 type = irqd_get_trigger_type(d);
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raw_spin_lock(&ic->lock);
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if (type & IRQ_TYPE_LEVEL_MASK || type & IRQ_TYPE_EDGE_RISING)
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lpc18xx_gpio_pin_ic_set(ic, d->hwirq,
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LPC18XX_GPIO_PIN_IC_CIENR);
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if (type & IRQ_TYPE_EDGE_FALLING)
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lpc18xx_gpio_pin_ic_set(ic, d->hwirq,
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LPC18XX_GPIO_PIN_IC_CIENF);
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raw_spin_unlock(&ic->lock);
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irq_chip_mask_parent(d);
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}
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static void lpc18xx_gpio_pin_ic_unmask(struct irq_data *d)
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{
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struct lpc18xx_gpio_pin_ic *ic = d->chip_data;
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u32 type = irqd_get_trigger_type(d);
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raw_spin_lock(&ic->lock);
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if (type & IRQ_TYPE_LEVEL_MASK || type & IRQ_TYPE_EDGE_RISING)
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lpc18xx_gpio_pin_ic_set(ic, d->hwirq,
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LPC18XX_GPIO_PIN_IC_SIENR);
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if (type & IRQ_TYPE_EDGE_FALLING)
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lpc18xx_gpio_pin_ic_set(ic, d->hwirq,
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LPC18XX_GPIO_PIN_IC_SIENF);
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raw_spin_unlock(&ic->lock);
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irq_chip_unmask_parent(d);
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}
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static void lpc18xx_gpio_pin_ic_eoi(struct irq_data *d)
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{
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struct lpc18xx_gpio_pin_ic *ic = d->chip_data;
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u32 type = irqd_get_trigger_type(d);
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raw_spin_lock(&ic->lock);
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if (type & IRQ_TYPE_EDGE_BOTH)
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lpc18xx_gpio_pin_ic_set(ic, d->hwirq,
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LPC18XX_GPIO_PIN_IC_IST);
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raw_spin_unlock(&ic->lock);
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irq_chip_eoi_parent(d);
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}
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static int lpc18xx_gpio_pin_ic_set_type(struct irq_data *d, unsigned int type)
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{
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struct lpc18xx_gpio_pin_ic *ic = d->chip_data;
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raw_spin_lock(&ic->lock);
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if (type & IRQ_TYPE_LEVEL_HIGH) {
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lpc18xx_gpio_pin_ic_isel(ic, d->hwirq, true);
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lpc18xx_gpio_pin_ic_set(ic, d->hwirq,
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LPC18XX_GPIO_PIN_IC_SIENF);
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} else if (type & IRQ_TYPE_LEVEL_LOW) {
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lpc18xx_gpio_pin_ic_isel(ic, d->hwirq, true);
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lpc18xx_gpio_pin_ic_set(ic, d->hwirq,
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LPC18XX_GPIO_PIN_IC_CIENF);
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} else {
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lpc18xx_gpio_pin_ic_isel(ic, d->hwirq, false);
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}
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raw_spin_unlock(&ic->lock);
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return 0;
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}
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static struct irq_chip lpc18xx_gpio_pin_ic = {
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.name = "LPC18xx GPIO pin",
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.irq_mask = lpc18xx_gpio_pin_ic_mask,
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.irq_unmask = lpc18xx_gpio_pin_ic_unmask,
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.irq_eoi = lpc18xx_gpio_pin_ic_eoi,
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.irq_set_type = lpc18xx_gpio_pin_ic_set_type,
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.irq_retrigger = irq_chip_retrigger_hierarchy,
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.flags = IRQCHIP_SET_TYPE_MASKED,
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};
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static int lpc18xx_gpio_pin_ic_domain_alloc(struct irq_domain *domain,
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unsigned int virq,
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unsigned int nr_irqs, void *data)
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{
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struct irq_fwspec parent_fwspec, *fwspec = data;
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struct lpc18xx_gpio_pin_ic *ic = domain->host_data;
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irq_hw_number_t hwirq;
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int ret;
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if (nr_irqs != 1)
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return -EINVAL;
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hwirq = fwspec->param[0];
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if (hwirq >= NR_LPC18XX_GPIO_PIN_IC_IRQS)
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return -EINVAL;
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/*
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* All LPC18xx/LPC43xx GPIO pin hardware interrupts are translated
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* into edge interrupts 32...39 on parent Cortex-M3/M4 NVIC
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*/
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parent_fwspec.fwnode = domain->parent->fwnode;
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parent_fwspec.param_count = 1;
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parent_fwspec.param[0] = hwirq + 32;
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ret = irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec);
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if (ret < 0) {
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pr_err("failed to allocate parent irq %u: %d\n",
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parent_fwspec.param[0], ret);
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return ret;
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}
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return irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
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&lpc18xx_gpio_pin_ic, ic);
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}
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static const struct irq_domain_ops lpc18xx_gpio_pin_ic_domain_ops = {
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.alloc = lpc18xx_gpio_pin_ic_domain_alloc,
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.xlate = irq_domain_xlate_twocell,
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.free = irq_domain_free_irqs_common,
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};
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static int lpc18xx_gpio_pin_ic_probe(struct lpc18xx_gpio_chip *gc)
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{
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struct device *dev = gc->gpio.parent;
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struct irq_domain *parent_domain;
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struct device_node *parent_node;
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struct lpc18xx_gpio_pin_ic *ic;
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struct resource res;
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int ret, index;
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parent_node = of_irq_find_parent(dev->of_node);
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if (!parent_node)
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return -ENXIO;
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parent_domain = irq_find_host(parent_node);
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of_node_put(parent_node);
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if (!parent_domain)
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return -ENXIO;
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ic = devm_kzalloc(dev, sizeof(*ic), GFP_KERNEL);
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if (!ic)
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return -ENOMEM;
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index = of_property_match_string(dev->of_node, "reg-names",
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"gpio-pin-ic");
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if (index < 0) {
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ret = -ENODEV;
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goto free_ic;
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}
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ret = of_address_to_resource(dev->of_node, index, &res);
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if (ret < 0)
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goto free_ic;
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ic->base = devm_ioremap_resource(dev, &res);
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if (IS_ERR(ic->base)) {
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ret = PTR_ERR(ic->base);
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goto free_ic;
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}
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raw_spin_lock_init(&ic->lock);
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ic->domain = irq_domain_add_hierarchy(parent_domain, 0,
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NR_LPC18XX_GPIO_PIN_IC_IRQS,
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dev->of_node,
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&lpc18xx_gpio_pin_ic_domain_ops,
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ic);
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if (!ic->domain) {
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pr_err("unable to add irq domain\n");
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ret = -ENODEV;
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goto free_iomap;
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}
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gc->pin_ic = ic;
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return 0;
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free_iomap:
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devm_iounmap(dev, ic->base);
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free_ic:
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devm_kfree(dev, ic);
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return ret;
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}
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static void lpc18xx_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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{
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struct lpc18xx_gpio_chip *gc = gpiochip_get_data(chip);
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@ -91,8 +330,7 @@ static int lpc18xx_gpio_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct lpc18xx_gpio_chip *gc;
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struct resource *res;
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int ret;
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int index, ret;
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gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL);
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if (!gc)
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@ -101,8 +339,22 @@ static int lpc18xx_gpio_probe(struct platform_device *pdev)
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gc->gpio = lpc18xx_chip;
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platform_set_drvdata(pdev, gc);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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gc->base = devm_ioremap_resource(dev, res);
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index = of_property_match_string(dev->of_node, "reg-names", "gpio");
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if (index < 0) {
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/* To support backward compatibility take the first resource */
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struct resource *res;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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gc->base = devm_ioremap_resource(dev, res);
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} else {
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struct resource res;
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ret = of_address_to_resource(dev->of_node, index, &res);
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if (ret < 0)
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return ret;
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gc->base = devm_ioremap_resource(dev, &res);
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}
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if (IS_ERR(gc->base))
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return PTR_ERR(gc->base);
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@ -129,6 +381,9 @@ static int lpc18xx_gpio_probe(struct platform_device *pdev)
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return ret;
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}
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/* On error GPIO pin interrupt controller just won't be registered */
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lpc18xx_gpio_pin_ic_probe(gc);
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return 0;
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}
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@ -136,6 +391,9 @@ static int lpc18xx_gpio_remove(struct platform_device *pdev)
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{
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struct lpc18xx_gpio_chip *gc = platform_get_drvdata(pdev);
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if (gc->pin_ic)
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irq_domain_remove(gc->pin_ic->domain);
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clk_disable_unprepare(gc->clk);
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return 0;
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@ -158,5 +416,6 @@ static struct platform_driver lpc18xx_gpio_driver = {
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module_platform_driver(lpc18xx_gpio_driver);
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MODULE_AUTHOR("Joachim Eastwood <manabian@gmail.com>");
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MODULE_AUTHOR("Vladimir Zapolskiy <vz@mleia.com>");
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MODULE_DESCRIPTION("GPIO driver for LPC18xx/43xx");
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MODULE_LICENSE("GPL v2");
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