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ARM: soc: late platform updates 

This branch contains updates to OMAP and Marvell platforms (kirkwood,
 dove, mvebu) that came in after we had done the big multiplatform merges,
 so they were kept separate from the rest, and not separated into the
 traditional topics of cleanup/driver/platform features.
 
 For OMAP, the updates are:
 - Runtime PM conversions for the GPMC and RNG IP blocks
 - Preparation patches for the OMAP common clock framework conversion
 - clkdev alias additions required by other drivers
 - Performance Monitoring Unit (PMU) support for OMAP2, 3, and non-4430 OMAP4
 - OMAP hwmod code and data improvements
 - Preparation patches for the IOMMU runtime PM conversion
 - Preparation patches for OMAP4 full-chip retention support
 
 For Kirkwood/Dove/mvebu:
 
 - New driver for "address decoder controller" for mvebu, which
   is a piece of hardware that configures addressable devices and
   peripherals. First user is the boot rom aperture on armada XP since
   it is needed for SMP support.
 - New device tree bindings for peripherals such as gpio-fan, iconnect
   nand, mv_cesa and the above address decoder controller.
 - Some defconfig updates, mostly to enable new DT boards and a few drivers.
 - New drivers using the pincontrol subsystem for dove, kirkwood and mvebu
 - New clean gpio driver for mvebu
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Merge tag 'soc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull late ARM soc platform updates from Olof Johansson:
 "This branch contains updates to OMAP and Marvell platforms (kirkwood,
  dove, mvebu) that came in after we had done the big multiplatform
  merges, so they were kept separate from the rest, and not separated
  into the traditional topics of cleanup/driver/platform features.

  For OMAP, the updates are:
   - Runtime PM conversions for the GPMC and RNG IP blocks
   - Preparation patches for the OMAP common clock framework conversion
   - clkdev alias additions required by other drivers
   - Performance Monitoring Unit (PMU) support for OMAP2, 3, and
     non-4430 OMAP4
   - OMAP hwmod code and data improvements
   - Preparation patches for the IOMMU runtime PM conversion
   - Preparation patches for OMAP4 full-chip retention support

  For Kirkwood/Dove/mvebu:
   - New driver for "address decoder controller" for mvebu, which is a
     piece of hardware that configures addressable devices and
     peripherals.  First user is the boot rom aperture on armada XP
     since it is needed for SMP support.
   - New device tree bindings for peripherals such as gpio-fan, iconnect
     nand, mv_cesa and the above address decoder controller.
   - Some defconfig updates, mostly to enable new DT boards and a few
     drivers.
   - New drivers using the pincontrol subsystem for dove, kirkwood and
     mvebu
   - New clean gpio driver for mvebu"

* tag 'soc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (98 commits)
  ARM: mvebu: fix build breaks from multi-platform conversion
  ARM: OMAP4460/4470: PMU: Enable PMU for OMAP4460/70
  ARM: OMAP2+: PMU: Add runtime PM support
  ARM: OMAP4430: PMU: prepare to create PMU device via HWMOD
  ARM: OMAP2+: PMU: Convert OMAP2/3 devices to use HWMOD
  ARM: OMAP3: hwmod data: Add debugss HWMOD data
  ARM: OMAP2+: clockdomain/hwmod: add workaround for EMU clockdomain idle problems
  ARM: OMAP: Add a timer attribute for timers that can interrupt the DSP
  hwrng: OMAP: remove SoC restrictions from driver registration
  ARM: OMAP: split OMAP1, OMAP2+ RNG device registration
  hwrng: OMAP: convert to use runtime PM
  hwrng: OMAP: store per-device data in per-device variables, not file statics
  ARM: OMAP2xxx: hwmod/CM: add RNG integration data
  ARM: OMAP2+: gpmc: minimal driver support
  ARM: OMAP2+: gpmc: Adapt to HWMOD
  ARM: OMAP2/3: hwmod data: add gpmc
  ARM: OMAP4: hwmod data: add mmu hwmod for ipu and dsp
  ARM: OMAP3: hwmod data: add mmu data for iva and isp
  ARM: OMAP: iommu: fix including iommu.h without IOMMU_API selected
  ARM: OMAP4: hwmod data: add missing HWMOD_NO_IDLEST flags to some PRCM IP blocks
  ...
hifive-unleashed-5.1
Linus Torvalds 2012-10-07 20:55:16 +09:00
parent 84424026c0 54d69df584
commit 5e090ed7af
150 changed files with 8253 additions and 869 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
Documentation/devicetree/bindings/crypto/mv_cesa.txt 100644
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Marvell Cryptographic Engines And Security Accelerator
Required properties:
- compatible : should be "marvell,orion-crypto"
- reg : base physical address of the engine and length of memory mapped
region, followed by base physical address of sram and its memory
length
- reg-names : "regs" , "sram";
- interrupts : interrupt number
Examples:
crypto@30000 {
compatible = "marvell,orion-crypto";
reg = <0x30000 0x10000>,
<0x4000000 0x800>;
reg-names = "regs" , "sram";
interrupts = <22>;
status = "okay";
};

25
Documentation/devicetree/bindings/gpio/gpio-fan.txt 100644
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Bindings for fan connected to GPIO lines
Required properties:
- compatible : "gpio-fan"
- gpios: Specifies the pins that map to bits in the control value,
ordered MSB-->LSB.
- gpio-fan,speed-map: A mapping of possible fan RPM speeds and the
control value that should be set to achieve them. This array
must have the RPM values in ascending order.
Optional properties:
- alarm-gpios: This pin going active indicates something is wrong with
the fan, and a udev event will be fired.
Examples:
gpio_fan {
compatible = "gpio-fan";
gpios = <&gpio1 14 1
&gpio1 13 1>;
gpio-fan,speed-map = <0 0
3000 1
6000 2>;
alarm-gpios = <&gpio1 15 1>;
};

53
Documentation/devicetree/bindings/gpio/gpio-mvebu.txt 100644
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* Marvell EBU GPIO controller
Required properties:
- compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio"
or "marvell,armadaxp-gpio". "marvell,orion-gpio" should be used for
Orion, Kirkwood, Dove, Discovery (except MV78200) and Armada
370. "marvell,mv78200-gpio" should be used for the Discovery
MV78200. "marvel,armadaxp-gpio" should be used for all Armada XP
SoCs (MV78230, MV78260, MV78460).
- reg: Address and length of the register set for the device. Only one
entry is expected, except for the "marvell,armadaxp-gpio" variant
for which two entries are expected: one for the general registers,
one for the per-cpu registers.
- interrupts: The list of interrupts that are used for all the pins
managed by this GPIO bank. There can be more than one interrupt
(example: 1 interrupt per 8 pins on Armada XP, which means 4
interrupts per bank of 32 GPIOs).
- interrupt-controller: identifies the node as an interrupt controller
- #interrupt-cells: specifies the number of cells needed to encode an
interrupt source. Should be two.
The first cell is the GPIO number.
The second cell is used to specify flags:
bits[3:0] trigger type and level flags:
1 = low-to-high edge triggered.
2 = high-to-low edge triggered.
4 = active high level-sensitive.
8 = active low level-sensitive.
- gpio-controller: marks the device node as a gpio controller
- ngpios: number of GPIOs this controller has
- #gpio-cells: Should be two. The first cell is the pin number. The
second cell is reserved for flags, unused at the moment.
Example:
gpio0: gpio@d0018100 {
compatible = "marvell,armadaxp-gpio";
reg = <0xd0018100 0x40>,
<0xd0018800 0x30>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <16>, <17>, <18>, <19>;
};

95
Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt 100644
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* Marvell Armada 370 SoC pinctrl driver for mpp
Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
part and usage.
Required properties:
- compatible: "marvell,88f6710-pinctrl"
Available mpp pins/groups and functions:
Note: brackets (x) are not part of the mpp name for marvell,function and given
only for more detailed description in this document.
name pins functions
================================================================================
mpp0 0 gpio, uart0(rxd)
mpp1 1 gpo, uart0(txd)
mpp2 2 gpio, i2c0(sck), uart0(txd)
mpp3 3 gpio, i2c0(sda), uart0(rxd)
mpp4 4 gpio, cpu_pd(vdd)
mpp5 5 gpo, ge0(txclko), uart1(txd), spi1(clk), audio(mclk)
mpp6 6 gpio, ge0(txd0), sata0(prsnt), tdm(rst), audio(sdo)
mpp7 7 gpo, ge0(txd1), tdm(tdx), audio(lrclk)
mpp8 8 gpio, ge0(txd2), uart0(rts), tdm(drx), audio(bclk)
mpp9 9 gpo, ge0(txd3), uart1(txd), sd0(clk), audio(spdifo)
mpp10 10 gpio, ge0(txctl), uart0(cts), tdm(fsync), audio(sdi)
mpp11 11 gpio, ge0(rxd0), uart1(rxd), sd0(cmd), spi0(cs1),
sata1(prsnt), spi1(cs1)
mpp12 12 gpio, ge0(rxd1), i2c1(sda), sd0(d0), spi1(cs0),
audio(spdifi)
mpp13 13 gpio, ge0(rxd2), i2c1(sck), sd0(d1), tdm(pclk),
audio(rmclk)
mpp14 14 gpio, ge0(rxd3), pcie(clkreq0), sd0(d2), spi1(mosi),
spi0(cs2)
mpp15 15 gpio, ge0(rxctl), pcie(clkreq1), sd0(d3), spi1(miso),
spi0(cs3)
mpp16 16 gpio, ge0(rxclk), uart1(rxd), tdm(int), audio(extclk)
mpp17 17 gpo, ge(mdc)
mpp18 18 gpio, ge(mdio)
mpp19 19 gpio, ge0(txclk), ge1(txclkout), tdm(pclk)
mpp20 20 gpo, ge0(txd4), ge1(txd0)
mpp21 21 gpo, ge0(txd5), ge1(txd1), uart1(txd)
mpp22 22 gpo, ge0(txd6), ge1(txd2), uart0(rts)
mpp23 23 gpo, ge0(txd7), ge1(txd3), spi1(mosi)
mpp24 24 gpio, ge0(col), ge1(txctl), spi1(cs0)
mpp25 25 gpio, ge0(rxerr), ge1(rxd0), uart1(rxd)
mpp26 26 gpio, ge0(crs), ge1(rxd1), spi1(miso)
mpp27 27 gpio, ge0(rxd4), ge1(rxd2), uart0(cts)
mpp28 28 gpio, ge0(rxd5), ge1(rxd3)
mpp29 29 gpio, ge0(rxd6), ge1(rxctl), i2c1(sda)
mpp30 30 gpio, ge0(rxd7), ge1(rxclk), i2c1(sck)
mpp31 31 gpio, tclk, ge0(txerr)
mpp32 32 gpio, spi0(cs0)
mpp33 33 gpio, dev(bootcs), spi0(cs0)
mpp34 34 gpo, dev(wen0), spi0(mosi)
mpp35 35 gpo, dev(oen), spi0(sck)
mpp36 36 gpo, dev(a1), spi0(miso)
mpp37 37 gpo, dev(a0), sata0(prsnt)
mpp38 38 gpio, dev(ready), uart1(cts), uart0(cts)
mpp39 39 gpo, dev(ad0), audio(spdifo)
mpp40 40 gpio, dev(ad1), uart1(rts), uart0(rts)
mpp41 41 gpio, dev(ad2), uart1(rxd)
mpp42 42 gpo, dev(ad3), uart1(txd)
mpp43 43 gpo, dev(ad4), audio(bclk)
mpp44 44 gpo, dev(ad5), audio(mclk)
mpp45 45 gpo, dev(ad6), audio(lrclk)
mpp46 46 gpo, dev(ad7), audio(sdo)
mpp47 47 gpo, dev(ad8), sd0(clk), audio(spdifo)
mpp48 48 gpio, dev(ad9), uart0(rts), sd0(cmd), sata1(prsnt),
spi0(cs1)
mpp49 49 gpio, dev(ad10), pcie(clkreq1), sd0(d0), spi1(cs0),
audio(spdifi)
mpp50 50 gpio, dev(ad11), uart0(cts), sd0(d1), spi1(miso),
audio(rmclk)
mpp51 51 gpio, dev(ad12), i2c1(sda), sd0(d2), spi1(mosi)
mpp52 52 gpio, dev(ad13), i2c1(sck), sd0(d3), spi1(sck)
mpp53 53 gpio, dev(ad14), sd0(clk), tdm(pclk), spi0(cs2),
pcie(clkreq1)
mpp54 54 gpo, dev(ad15), tdm(dtx)
mpp55 55 gpio, dev(cs1), uart1(txd), tdm(rst), sata1(prsnt),
sata0(prsnt)
mpp56 56 gpio, dev(cs2), uart1(cts), uart0(cts), spi0(cs3),
pcie(clkreq0), spi1(cs1)
mpp57 57 gpio, dev(cs3), uart1(rxd), tdm(fsync), sata0(prsnt),
audio(sdo)
mpp58 58 gpio, dev(cs0), uart1(rts), tdm(int), audio(extclk),
uart0(rts)
mpp59 59 gpo, dev(ale0), uart1(rts), uart0(rts), audio(bclk)
mpp60 60 gpio, dev(ale1), uart1(rxd), sata0(prsnt), pcie(rst-out),
audio(sdi)
mpp61 61 gpo, dev(wen1), uart1(txd), audio(rclk)
mpp62 62 gpio, dev(a2), uart1(cts), tdm(drx), pcie(clkreq0),
audio(mclk), uart0(cts)
mpp63 63 gpo, spi0(sck), tclk
mpp64 64 gpio, spi0(miso), spi0-1(cs1)
mpp65 65 gpio, spi0(mosi), spi0-1(cs2)

100
Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt 100644
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* Marvell Armada XP SoC pinctrl driver for mpp
Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
part and usage.
Required properties:
- compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl",
"marvell,mv78460-pinctrl"
This driver supports all Armada XP variants, i.e. mv78230, mv78260, and mv78460.
Available mpp pins/groups and functions:
Note: brackets (x) are not part of the mpp name for marvell,function and given
only for more detailed description in this document.
* Marvell Armada XP (all variants)
name pins functions
================================================================================
mpp0 0 gpio, ge0(txclko), lcd(d0)
mpp1 1 gpio, ge0(txd0), lcd(d1)
mpp2 2 gpio, ge0(txd1), lcd(d2)
mpp3 3 gpio, ge0(txd2), lcd(d3)
mpp4 4 gpio, ge0(txd3), lcd(d4)
mpp5 5 gpio, ge0(txctl), lcd(d5)
mpp6 6 gpio, ge0(rxd0), lcd(d6)
mpp7 7 gpio, ge0(rxd1), lcd(d7)
mpp8 8 gpio, ge0(rxd2), lcd(d8)
mpp9 9 gpio, ge0(rxd3), lcd(d9)
mpp10 10 gpio, ge0(rxctl), lcd(d10)
mpp11 11 gpio, ge0(rxclk), lcd(d11)
mpp12 12 gpio, ge0(txd4), ge1(txd0), lcd(d12)
mpp13 13 gpio, ge0(txd5), ge1(txd1), lcd(d13)
mpp14 14 gpio, ge0(txd6), ge1(txd2), lcd(d15)
mpp15 15 gpio, ge0(txd7), ge1(txd3), lcd(d16)
mpp16 16 gpio, ge0(txd7), ge1(txd3), lcd(d16)
mpp17 17 gpio, ge0(col), ge1(txctl), lcd(d17)
mpp18 18 gpio, ge0(rxerr), ge1(rxd0), lcd(d18), ptp(trig)
mpp19 19 gpio, ge0(crs), ge1(rxd1), lcd(d19), ptp(evreq)
mpp20 20 gpio, ge0(rxd4), ge1(rxd2), lcd(d20), ptp(clk)
mpp21 21 gpio, ge0(rxd5), ge1(rxd3), lcd(d21), mem(bat)
mpp22 22 gpio, ge0(rxd6), ge1(rxctl), lcd(d22), sata0(prsnt)
mpp23 23 gpio, ge0(rxd7), ge1(rxclk), lcd(d23), sata1(prsnt)
mpp24 24 gpio, lcd(hsync), sata1(prsnt), nf(bootcs-re), tdm(rst)
mpp25 25 gpio, lcd(vsync), sata0(prsnt), nf(bootcs-we), tdm(pclk)
mpp26 26 gpio, lcd(clk), tdm(fsync), vdd(cpu1-pd)
mpp27 27 gpio, lcd(e), tdm(dtx), ptp(trig)
mpp28 28 gpio, lcd(pwm), tdm(drx), ptp(evreq)
mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk), vdd(cpu0-pd)
mpp30 30 gpio, tdm(int1), sd0(clk)
mpp31 31 gpio, tdm(int2), sd0(cmd), vdd(cpu0-pd)
mpp32 32 gpio, tdm(int3), sd0(d0), vdd(cpu1-pd)
mpp33 33 gpio, tdm(int4), sd0(d1), mem(bat)
mpp34 34 gpio, tdm(int5), sd0(d2), sata0(prsnt)
mpp35 35 gpio, tdm(int6), sd0(d3), sata1(prsnt)
mpp36 36 gpio, spi(mosi)
mpp37 37 gpio, spi(miso)
mpp38 38 gpio, spi(sck)
mpp39 39 gpio, spi(cs0)
mpp40 40 gpio, spi(cs1), uart2(cts), lcd(vga-hsync), vdd(cpu1-pd),
pcie(clkreq0)
mpp41 41 gpio, spi(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt),
pcie(clkreq1)
mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm-1(timer),
vdd(cpu0-pd)
mpp43 43 gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout),
vdd(cpu2-3-pd){1}
mpp44 44 gpio, uart2(cts), uart3(rxd), spi(cs4), pcie(clkreq2),
mem(bat)
mpp45 45 gpio, uart2(rts), uart3(txd), spi(cs5), sata1(prsnt)
mpp46 46 gpio, uart3(rts), uart1(rts), spi(cs6), sata0(prsnt)
mpp47 47 gpio, uart3(cts), uart1(cts), spi(cs7), pcie(clkreq3),
ref(clkout)
mpp48 48 gpio, tclk, dev(burst/last)
* Marvell Armada XP (mv78260 and mv78460 only)
name pins functions
================================================================================
mpp49 49 gpio, dev(we3)
mpp50 50 gpio, dev(we2)
mpp51 51 gpio, dev(ad16)
mpp52 52 gpio, dev(ad17)
mpp53 53 gpio, dev(ad18)
mpp54 54 gpio, dev(ad19)
mpp55 55 gpio, dev(ad20), vdd(cpu0-pd)
mpp56 56 gpio, dev(ad21), vdd(cpu1-pd)
mpp57 57 gpio, dev(ad22), vdd(cpu2-3-pd){1}
mpp58 58 gpio, dev(ad23)
mpp59 59 gpio, dev(ad24)
mpp60 60 gpio, dev(ad25)
mpp61 61 gpio, dev(ad26)
mpp62 62 gpio, dev(ad27)
mpp63 63 gpio, dev(ad28)
mpp64 64 gpio, dev(ad29)
mpp65 65 gpio, dev(ad30)
mpp66 66 gpio, dev(ad31)
Notes:
* {1} vdd(cpu2-3-pd) only available on mv78460.

72
Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt 100644
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* Marvell Dove SoC pinctrl driver for mpp
Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
part and usage.
Required properties:
- compatible: "marvell,dove-pinctrl"
- clocks: (optional) phandle of pdma clock
Available mpp pins/groups and functions:
Note: brackets (x) are not part of the mpp name for marvell,function and given
only for more detailed description in this document.
name pins functions
================================================================================
mpp0 0 gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm)
mpp1 1 gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm)
mpp2 2 gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt),
uart1(rts)
mpp3 3 gpio, pmu, uart2(rxd), sdio0(ledctrl), sata(act),
uart1(cts), lcd-spi(cs1)
mpp4 4 gpio, pmu, uart3(rts), sdio1(cd), spi1(miso)
mpp5 5 gpio, pmu, uart3(cts), sdio1(wp), spi1(cs)
mpp6 6 gpio, pmu, uart3(txd), sdio1(buspwr), spi1(mosi)
mpp7 7 gpio, pmu, uart3(rxd), sdio1(ledctrl), spi1(sck)
mpp8 8 gpio, pmu, watchdog(rstout)
mpp9 9 gpio, pmu, pex1(clkreq)
mpp10 10 gpio, pmu, ssp(sclk)
mpp11 11 gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl),
sdio1(ledctrl), pex0(clkreq)
mpp12 12 gpio, pmu, uart2(rts), audio0(extclk), sdio1(cd), sata(act)
mpp13 13 gpio, pmu, uart2(cts), audio1(extclk), sdio1(wp),
ssp(extclk)
mpp14 14 gpio, pmu, uart2(txd), sdio1(buspwr), ssp(rxd)
mpp15 15 gpio, pmu, uart2(rxd), sdio1(ledctrl), ssp(sfrm)
mpp16 16 gpio, uart3(rts), sdio0(cd), ac97(sdi1), lcd-spi(cs1)
mpp17 17 gpio, uart3(cts), sdio0(wp), ac97(sdi2), twsi(sda),
ac97-1(sysclko)
mpp18 18 gpio, uart3(txd), sdio0(buspwr), ac97(sdi3), lcd0(pwm)
mpp19 19 gpio, uart3(rxd), sdio0(ledctrl), twsi(sck)
mpp20 20 gpio, sdio0(cd), sdio1(cd), spi1(miso), lcd-spi(miso),
ac97(sysclko)
mpp21 21 gpio, sdio0(wp), sdio1(wp), spi1(cs), lcd-spi(cs0),
uart1(cts), ssp(sfrm)
mpp22 22 gpio, sdio0(buspwr), sdio1(buspwr), spi1(mosi),
lcd-spi(mosi), uart1(cts), ssp(txd)
mpp23 23 gpio, sdio0(ledctrl), sdio1(ledctrl), spi1(sck),
lcd-spi(sck), ssp(sclk)
mpp_camera 24-39 gpio, camera
mpp_sdio0 40-45 gpio, sdio0
mpp_sdio1 46-51 gpio, sdio1
mpp_audio1 52-57 gpio, i2s1/spdifo, i2s1, spdifo, twsi, ssp/spdifo, ssp,
ssp/twsi
mpp_spi0 58-61 gpio, spi0
mpp_uart1 62-63 gpio, uart1
mpp_nand 64-71 gpo, nand
audio0 - i2s, ac97
twsi - none, opt1, opt2, opt3
Notes:
* group "mpp_audio1" allows the following functions and gpio pins:
- gpio : gpio on pins 52-57
- i2s1/spdifo : audio1 i2s on pins 52-55 and spdifo on 57, no gpios
- i2s1 : audio1 i2s on pins 52-55, gpio on pins 56,57
- spdifo : spdifo on pin 57, gpio on pins 52-55
- twsi : twsi on pins 56,57, gpio on pins 52-55
- ssp/spdifo : ssp on pins 52-55, spdifo on pin 57, no gpios
- ssp : ssp on pins 52-55, gpio on pins 56,57
- ssp/twsi : ssp on pins 52-55, twsi on pins 56,57, no gpios
* group "audio0" internally muxes i2s0 or ac97 controller to the dedicated
audio0 pins.
* group "twsi" internally muxes twsi controller to the dedicated or option pins.

279
Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt 100644
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@ -0,0 +1,279 @@
* Marvell Kirkwood SoC pinctrl driver for mpp
Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
part and usage.
Required properties:
- compatible: "marvell,88f6180-pinctrl",
"marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
"marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl"
This driver supports all kirkwood variants, i.e. 88f6180, 88f619x, and 88f628x.
Available mpp pins/groups and functions:
Note: brackets (x) are not part of the mpp name for marvell,function and given
only for more detailed description in this document.
* Marvell Kirkwood 88f6180
name pins functions
================================================================================
mpp0 0 gpio, nand(io2), spi(cs)
mpp1 1 gpo, nand(io3), spi(mosi)
mpp2 2 gpo, nand(io4), spi(sck)
mpp3 3 gpo, nand(io5), spi(miso)
mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk)
mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig)
mpp6 6 sysrst(out), spi(mosi), ptp(trig)
mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig)
mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
mii(col)
mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
mii(crs)
mpp10 10 gpo, spi(sck), uart0(txd), ptp(trig)
mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
ptp-2(trig)
mpp12 12 gpo, sdio(clk)
mpp13 13 gpio, sdio(cmd), uart1(txd)
mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col)
mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd)
mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
mpp17 17 gpio, sdio(d3)
mpp18 18 gpo, nand(io0)
mpp19 19 gpo, nand(io1)
mpp20 20 gpio, mii(rxerr)
mpp21 21 gpio, audio(spdifi)
mpp22 22 gpio, audio(spdifo)
mpp23 23 gpio, audio(rmclk)
mpp24 24 gpio, audio(bclk)
mpp25 25 gpio, audio(sdo)
mpp26 26 gpio, audio(lrclk)
mpp27 27 gpio, audio(mclk)
mpp28 28 gpio, audio(sdi)
mpp29 29 gpio, audio(extclk)
* Marvell Kirkwood 88f6190
name pins functions
================================================================================
mpp0 0 gpio, nand(io2), spi(cs)
mpp1 1 gpo, nand(io3), spi(mosi)
mpp2 2 gpo, nand(io4), spi(sck)
mpp3 3 gpo, nand(io5), spi(miso)
mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk)
mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
mpp6 6 sysrst(out), spi(mosi), ptp(trig)
mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig)
mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
mii(col), mii-1(rxerr)
mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
mii(crs), sata0(prsnt)
mpp10 10 gpo, spi(sck), uart0(txd), ptp(trig)
mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
ptp-2(trig), sata0(act)
mpp12 12 gpo, sdio(clk)
mpp13 13 gpio, sdio(cmd), uart1(txd)
mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col)
mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
mpp17 17 gpio, sdio(d3), sata0(prsnt)
mpp18 18 gpo, nand(io0)
mpp19 19 gpo, nand(io1)
mpp20 20 gpio, ge1(txd0)
mpp21 21 gpio, ge1(txd1), sata0(act)
mpp22 22 gpio, ge1(txd2)
mpp23 23 gpio, ge1(txd3), sata0(prsnt)
mpp24 24 gpio, ge1(rxd0)
mpp25 25 gpio, ge1(rxd1)
mpp26 26 gpio, ge1(rxd2)
mpp27 27 gpio, ge1(rxd3)
mpp28 28 gpio, ge1(col)
mpp29 29 gpio, ge1(txclk)
mpp30 30 gpio, ge1(rxclk)
mpp31 31 gpio, ge1(rxclk)
mpp32 32 gpio, ge1(txclko)
mpp33 33 gpo, ge1(txclk)
mpp34 34 gpio, ge1(txen)
mpp35 35 gpio, ge1(rxerr), sata0(act), mii(rxerr)
* Marvell Kirkwood 88f6192
name pins functions
================================================================================
mpp0 0 gpio, nand(io2), spi(cs)
mpp1 1 gpo, nand(io3), spi(mosi)
mpp2 2 gpo, nand(io4), spi(sck)
mpp3 3 gpo, nand(io5), spi(miso)
mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk), sata1(act)
mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
mpp6 6 sysrst(out), spi(mosi), ptp(trig)
mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig)
mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
mii(col), mii-1(rxerr), sata1(prsnt)
mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
mii(crs), sata0(prsnt)
mpp10 10 gpo, spi(sck), uart0(txd), ptp(trig), sata1(act)
mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
ptp-2(trig), sata0(act)
mpp12 12 gpo, sdio(clk)
mpp13 13 gpio, sdio(cmd), uart1(txd)
mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt)
mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
sata1(act)
mpp17 17 gpio, sdio(d3), sata0(prsnt)
mpp18 18 gpo, nand(io0)
mpp19 19 gpo, nand(io1)
mpp20 20 gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
sata1(act)
mpp21 21 gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
audio(spdifo)
mpp22 22 gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
sata1(prsnt)
mpp23 23 gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
audio(bclk)
mpp24 24 gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo)
mpp25 25 gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk)
mpp26 26 gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk)
mpp27 27 gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi)
mpp28 28 gpio, ge1(col), ts(mp8), tdm(int), audio(extclk)
mpp29 29 gpio, ge1(txclk), ts(mp9), tdm(rst)
mpp30 30 gpio, ge1(rxclk), ts(mp10), tdm(pclk)
mpp31 31 gpio, ge1(rxclk), ts(mp11), tdm(fs)
mpp32 32 gpio, ge1(txclko), ts(mp12), tdm(drx)
mpp33 33 gpo, ge1(txclk), tdm(drx)
mpp34 34 gpio, ge1(txen), tdm(spi-cs1)
mpp35 35 gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql)
* Marvell Kirkwood 88f6281
name pins functions
================================================================================
mpp0 0 gpio, nand(io2), spi(cs)
mpp1 1 gpo, nand(io3), spi(mosi)
mpp2 2 gpo, nand(io4), spi(sck)
mpp3 3 gpo, nand(io5), spi(miso)
mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk), sata1(act)
mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
mpp6 6 sysrst(out), spi(mosi), ptp(trig)
mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig)
mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
mii(col), mii-1(rxerr), sata1(prsnt)
mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
mii(crs), sata0(prsnt)
mpp10 10 gpo, spi(sck), uart0(txd), ptp(trig), sata1(act)
mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
ptp-2(trig), sata0(act)
mpp12 12 gpio, sdio(clk)
mpp13 13 gpio, sdio(cmd), uart1(txd)
mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt)
mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
sata1(act)
mpp17 17 gpio, sdio(d3), sata0(prsnt)
mpp18 18 gpo, nand(io0)
mpp19 19 gpo, nand(io1)
mpp20 20 gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
sata1(act)
mpp21 21 gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
audio(spdifo)
mpp22 22 gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
sata1(prsnt)
mpp23 23 gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
audio(bclk)
mpp24 24 gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo)
mpp25 25 gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk)
mpp26 26 gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk)
mpp27 27 gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi)
mpp28 28 gpio, ge1(col), ts(mp8), tdm(int), audio(extclk)
mpp29 29 gpio, ge1(txclk), ts(mp9), tdm(rst)
mpp30 30 gpio, ge1(rxclk), ts(mp10), tdm(pclk)
mpp31 31 gpio, ge1(rxclk), ts(mp11), tdm(fs)
mpp32 32 gpio, ge1(txclko), ts(mp12), tdm(drx)
mpp33 33 gpo, ge1(txclk), tdm(drx)
mpp34 34 gpio, ge1(txen), tdm(spi-cs1), sata1(act)
mpp35 35 gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql)
mpp36 36 gpio, ts(mp0), tdm(spi-cs1), audio(spdifi)
mpp37 37 gpio, ts(mp1), tdm(tx2ql), audio(spdifo)
mpp38 38 gpio, ts(mp2), tdm(rx2ql), audio(rmclk)
mpp39 39 gpio, ts(mp3), tdm(spi-cs0), audio(bclk)
mpp40 40 gpio, ts(mp4), tdm(spi-sck), audio(sdo)
mpp41 41 gpio, ts(mp5), tdm(spi-miso), audio(lrclk)
mpp42 42 gpio, ts(mp6), tdm(spi-mosi), audio(mclk)
mpp43 43 gpio, ts(mp7), tdm(int), audio(sdi)
mpp44 44 gpio, ts(mp8), tdm(rst), audio(extclk)
mpp45 45 gpio, ts(mp9), tdm(pclk)
mpp46 46 gpio, ts(mp10), tdm(fs)
mpp47 47 gpio, ts(mp11), tdm(drx)
mpp48 48 gpio, ts(mp12), tdm(dtx)
mpp49 49 gpio, ts(mp9), tdm(rx0ql), ptp(clk)
* Marvell Kirkwood 88f6282
name pins functions
================================================================================
mpp0 0 gpio, nand(io2), spi(cs)
mpp1 1 gpo, nand(io3), spi(mosi)
mpp2 2 gpo, nand(io4), spi(sck)
mpp3 3 gpo, nand(io5), spi(miso)
mpp4 4 gpio, nand(io6), uart0(rxd), sata1(act), lcd(hsync)
mpp5 5 gpo, nand(io7), uart0(txd), sata0(act), lcd(vsync)
mpp6 6 sysrst(out), spi(mosi)
mpp7 7 gpo, spi(cs), lcd(pwm)
mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), mii(col),
mii-1(rxerr), sata1(prsnt)
mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), mii(crs),
sata0(prsnt)
mpp10 10 gpo, spi(sck), uart0(txd), sata1(act)
mpp11 11 gpio, spi(miso), uart0(rxd), sata0(act)
mpp12 12 gpo, sdio(clk), audio(spdifo), spi(mosi), twsi(sda)
mpp13 13 gpio, sdio(cmd), uart1(txd), audio(rmclk), lcd(pwm)
mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt),
audio(spdifi), audio-1(sdi)
mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act),
spi(cs)
mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
sata1(act), lcd(extclk)
mpp17 17 gpio, sdio(d3), sata0(prsnt), sata1(act), twsi1(sck)
mpp18 18 gpo, nand(io0), pex(clkreq)
mpp19 19 gpo, nand(io1)
mpp20 20 gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
sata1(act), lcd(d0)
mpp21 21 gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
audio(spdifo), lcd(d1)
mpp22 22 gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
sata1(prsnt), lcd(d2)
mpp23 23 gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
audio(bclk), lcd(d3)
mpp24 24 gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo),
lcd(d4)
mpp25 25 gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk),
lcd(d5)
mpp26 26 gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk),
lcd(d6)
mpp27 27 gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi),
lcd(d7)
mpp28 28 gpio, ge1(col), ts(mp8), tdm(int), audio(extclk),
lcd(d8)
mpp29 29 gpio, ge1(txclk), ts(mp9), tdm(rst), lcd(d9)
mpp30 30 gpio, ge1(rxclk), ts(mp10), tdm(pclk), lcd(d10)
mpp31 31 gpio, ge1(rxclk), ts(mp11), tdm(fs), lcd(d11)
mpp32 32 gpio, ge1(txclko), ts(mp12), tdm(drx), lcd(d12)
mpp33 33 gpo, ge1(txclk), tdm(drx), lcd(d13)
mpp34 34 gpio, ge1(txen), tdm(spi-cs1), sata1(act), lcd(d14)
mpp35 35 gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql),
lcd(d15)
mpp36 36 gpio, ts(mp0), tdm(spi-cs1), audio(spdifi), twsi1(sda)
mpp37 37 gpio, ts(mp1), tdm(tx2ql), audio(spdifo), twsi1(sck)
mpp38 38 gpio, ts(mp2), tdm(rx2ql), audio(rmclk), lcd(d18)
mpp39 39 gpio, ts(mp3), tdm(spi-cs0), audio(bclk), lcd(d19)
mpp40 40 gpio, ts(mp4), tdm(spi-sck), audio(sdo), lcd(d20)
mpp41 41 gpio, ts(mp5), tdm(spi-miso), audio(lrclk), lcd(d21)
mpp42 42 gpio, ts(mp6), tdm(spi-mosi), audio(mclk), lcd(d22)
mpp43 43 gpio, ts(mp7), tdm(int), audio(sdi), lcd(d23)
mpp44 44 gpio, ts(mp8), tdm(rst), audio(extclk), lcd(clk)
mpp45 45 gpio, ts(mp9), tdm(pclk), lcd(e)
mpp46 46 gpio, ts(mp10), tdm(fs), lcd(hsync)
mpp47 47 gpio, ts(mp11), tdm(drx), lcd(vsync)
mpp48 48 gpio, ts(mp12), tdm(dtx), lcd(d16)
mpp49 49 gpo, tdm(rx0ql), pex(clkreq), lcd(d17)

46
Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt 100644
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@ -0,0 +1,46 @@
* Marvell SoC pinctrl core driver for mpp
The pinctrl driver enables Marvell SoCs to configure the multi-purpose pins
(mpp) to a specific function. For each SoC family there is a SoC specific
driver using this core driver.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
A Marvell SoC pin configuration node is a node of a group of pins which can
be used for a specific device or function. Each node requires one or more
mpp pins or group of pins and a mpp function common to all pins.
Required properties for pinctrl driver:
- compatible: "marvell,<soc>-pinctrl"
Please refer to each marvell,<soc>-pinctrl.txt binding doc for supported SoCs.
Required properties for pin configuration node:
- marvell,pins: string array of mpp pins or group of pins to be muxed.
- marvell,function: string representing a function to mux to for all
marvell,pins given in this pin configuration node. The function has to be
common for all marvell,pins. Please refer to marvell,<soc>-pinctrl.txt for
valid pin/pin group names and available function names for each SoC.
Examples:
uart1: serial@12100 {
compatible = "ns16550a";
reg = <0x12100 0x100>;
reg-shift = <2>;
interrupts = <7>;
pinctrl-0 = <&pmx_uart1_sw>;
pinctrl-names = "default";
};
pinctrl: pinctrl@d0200 {
compatible = "marvell,dove-pinctrl";
reg = <0xd0200 0x20>;
pmx_uart1_sw: pmx-uart1-sw {
marvell,pins = "mpp_uart1";
marvell,function = "uart1";
};
};

15
arch/arm/Kconfig
View File

@ -529,10 +529,11 @@ config ARCH_IXP4XX
config ARCH_DOVE
bool "Marvell Dove"
select CPU_V7
select PCI
select ARCH_REQUIRE_GPIOLIB
select GENERIC_CLOCKEVENTS
select PLAT_ORION
select MIGHT_HAVE_PCI
select PLAT_ORION_LEGACY
select USB_ARCH_HAS_EHCI
help
Support for the Marvell Dove SoC 88AP510
@ -542,7 +543,7 @@ config ARCH_KIRKWOOD
select PCI
select ARCH_REQUIRE_GPIOLIB
select GENERIC_CLOCKEVENTS
select PLAT_ORION
select PLAT_ORION_LEGACY
help
Support for the following Marvell Kirkwood series SoCs:
88F6180, 88F6192 and 88F6281.
@ -568,7 +569,7 @@ config ARCH_MV78XX0
select PCI
select ARCH_REQUIRE_GPIOLIB
select GENERIC_CLOCKEVENTS
select PLAT_ORION
select PLAT_ORION_LEGACY
help
Support for the following Marvell MV78xx0 series SoCs:
MV781x0, MV782x0.
@ -580,7 +581,7 @@ config ARCH_ORION5X
select PCI
select ARCH_REQUIRE_GPIOLIB
select GENERIC_CLOCKEVENTS
select PLAT_ORION
select PLAT_ORION_LEGACY
help
Support for the following Marvell Orion 5x series SoCs:
Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
@ -1138,6 +1139,10 @@ config PLAT_ORION
select IRQ_DOMAIN
select COMMON_CLK
config PLAT_ORION_LEGACY
bool
select PLAT_ORION
config PLAT_PXA
bool

6
arch/arm/boot/dts/Makefile
View File

@ -17,6 +17,9 @@ dtb-$(CONFIG_ARCH_AT91) += aks-cdu.dtb \
usb_a9263.dtb \
usb_a9g20.dtb
dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
dove-cubox.dtb \
dove-dove-db.dtb
dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos4210-smdkv310.dtb \
exynos4210-trats.dtb \
@ -33,10 +36,13 @@ dtb-$(CONFIG_SOC_IMX6Q) += imx6q-arm2.dtb \
dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-dns320.dtb \
kirkwood-dns325.dtb \
kirkwood-dockstar.dtb \
kirkwood-dreamplug.dtb \
kirkwood-goflexnet.dtb \
kirkwood-ib62x0.dtb \
kirkwood-iconnect.dtb \
kirkwood-iomega_ix2_200.dtb \
kirkwood-km_kirkwood.dtb \
kirkwood-lschlv2.dtb \
kirkwood-lsxhl.dtb \
kirkwood-ts219-6281.dtb \

5
arch/arm/boot/dts/armada-370-xp.dtsi
View File

@ -63,6 +63,11 @@
reg = <0xd0020300 0x30>;
interrupts = <37>, <38>, <39>, <40>;
};
addr-decoding@d0020000 {
compatible = "marvell,armada-addr-decoding-controller";
reg = <0xd0020000 0x258>;
};
};
};

44
arch/arm/boot/dts/armada-370.dtsi
View File

@ -21,6 +21,12 @@
model = "Marvell Armada 370 family SoC";
compatible = "marvell,armada370", "marvell,armada-370-xp";
aliases {
gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
};
mpic: interrupt-controller@d0020000 {
reg = <0xd0020a00 0x1d0>,
<0xd0021870 0x58>;
@ -31,5 +37,43 @@
compatible = "marvell,armada-370-xp-system-controller";
reg = <0xd0018200 0x100>;
};
pinctrl {
compatible = "marvell,mv88f6710-pinctrl";
reg = <0xd0018000 0x38>;
};
gpio0: gpio@d0018100 {
compatible = "marvell,orion-gpio";
reg = <0xd0018100 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <82>, <83>, <84>, <85>;
};
gpio1: gpio@d0018140 {
compatible = "marvell,orion-gpio";
reg = <0xd0018140 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <87>, <88>, <89>, <90>;
};
gpio2: gpio@d0018180 {
compatible = "marvell,orion-gpio";
reg = <0xd0018180 0x40>;
ngpios = <2>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <91>;
};
};
};

4
arch/arm/boot/dts/armada-xp-db.dts
View File

@ -14,11 +14,11 @@
*/
/dts-v1/;
/include/ "armada-xp.dtsi"
/include/ "armada-xp-mv78460.dtsi"
/ {
model = "Marvell Armada XP Evaluation Board";
compatible = "marvell,axp-db", "marvell,armadaxp", "marvell,armada-370-xp";
compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
chosen {
bootargs = "console=ttyS0,115200 earlyprintk";

57
arch/arm/boot/dts/armada-xp-mv78230.dtsi 100644
View File

@ -0,0 +1,57 @@
/*
* Device Tree Include file for Marvell Armada XP family SoC
*
* Copyright (C) 2012 Marvell
*
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*
* Contains definitions specific to the Armada XP MV78230 SoC that are not
* common to all Armada XP SoCs.
*/
/include/ "armada-xp.dtsi"
/ {
model = "Marvell Armada XP MV78230 SoC";
compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
aliases {
gpio0 = &gpio0;
gpio1 = &gpio1;
};
soc {
pinctrl {
compatible = "marvell,mv78230-pinctrl";
reg = <0xd0018000 0x38>;
};
gpio0: gpio@d0018100 {
compatible = "marvell,armadaxp-gpio";
reg = <0xd0018100 0x40>,
<0xd0018800 0x30>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <16>, <17>, <18>, <19>;
};
gpio1: gpio@d0018140 {
compatible = "marvell,armadaxp-gpio";
reg = <0xd0018140 0x40>,
<0xd0018840 0x30>;
ngpios = <17>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <20>, <21>, <22>;
};
};
};

70
arch/arm/boot/dts/armada-xp-mv78260.dtsi 100644
View File

@ -0,0 +1,70 @@
/*
* Device Tree Include file for Marvell Armada XP family SoC
*
* Copyright (C) 2012 Marvell
*
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*
* Contains definitions specific to the Armada XP MV78260 SoC that are not
* common to all Armada XP SoCs.
*/
/include/ "armada-xp.dtsi"
/ {
model = "Marvell Armada XP MV78260 SoC";
compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
aliases {
gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
};
soc {
pinctrl {
compatible = "marvell,mv78260-pinctrl";
reg = <0xd0018000 0x38>;
};
gpio0: gpio@d0018100 {
compatible = "marvell,armadaxp-gpio";
reg = <0xd0018100 0x40>,
<0xd0018800 0x30>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <16>, <17>, <18>, <19>;
};
gpio1: gpio@d0018140 {
compatible = "marvell,armadaxp-gpio";
reg = <0xd0018140 0x40>,
<0xd0018840 0x30>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <20>, <21>, <22>, <23>;
};
gpio2: gpio@d0018180 {
compatible = "marvell,armadaxp-gpio";
reg = <0xd0018180 0x40>,
<0xd0018870 0x30>;
ngpios = <3>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <24>;
};
};
};

70
arch/arm/boot/dts/armada-xp-mv78460.dtsi 100644
View File

@ -0,0 +1,70 @@
/*
* Device Tree Include file for Marvell Armada XP family SoC
*
* Copyright (C) 2012 Marvell
*
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*
* Contains definitions specific to the Armada XP MV78460 SoC that are not
* common to all Armada XP SoCs.
*/
/include/ "armada-xp.dtsi"
/ {
model = "Marvell Armada XP MV78460 SoC";
compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
aliases {
gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
};
soc {
pinctrl {
compatible = "marvell,mv78460-pinctrl";
reg = <0xd0018000 0x38>;
};
gpio0: gpio@d0018100 {
compatible = "marvell,armadaxp-gpio";
reg = <0xd0018100 0x40>,
<0xd0018800 0x30>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <16>, <17>, <18>, <19>;
};
gpio1: gpio@d0018140 {
compatible = "marvell,armadaxp-gpio";
reg = <0xd0018140 0x40>,
<0xd0018840 0x30>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <20>, <21>, <22>, <23>;
};
gpio2: gpio@d0018180 {
compatible = "marvell,armadaxp-gpio";
reg = <0xd0018180 0x40>,
<0xd0018870 0x30>;
ngpios = <3>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <24>;
};
};
};

38
arch/arm/boot/dts/dove-cm-a510.dts 100644
View File

@ -0,0 +1,38 @@
/dts-v1/;
/include/ "dove.dtsi"
/ {
model = "Compulab CM-A510";
compatible = "compulab,cm-a510", "marvell,dove";
memory {
device_type = "memory";
reg = <0x00000000 0x40000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8 earlyprintk";
};
};
&uart0 { status = "okay"; };
&uart1 { status = "okay"; };
&sdio0 { status = "okay"; };
&sdio1 { status = "okay"; };
&sata0 { status = "okay"; };
&spi0 {
status = "okay";
/* spi0.0: 4M Flash Winbond W25Q32BV */
spi-flash@0 {
compatible = "st,w25q32";
spi-max-frequency = <20000000>;
reg = <0>;
};
};
&i2c0 {
status = "okay";
};

42
arch/arm/boot/dts/dove-cubox.dts 100644
View File

@ -0,0 +1,42 @@
/dts-v1/;
/include/ "dove.dtsi"
/ {
model = "SolidRun CuBox";
compatible = "solidrun,cubox", "marvell,dove";
memory {
device_type = "memory";
reg = <0x00000000 0x40000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8 earlyprintk";
};
leds {
compatible = "gpio-leds";
power {
label = "Power";
gpios = <&gpio0 18 1>;
linux,default-trigger = "default-on";
};
};
};
&uart0 { status = "okay"; };
&sdio0 { status = "okay"; };
&sata0 { status = "okay"; };
&i2c0 { status = "okay"; };
&spi0 {
status = "okay";
/* spi0.0: 4M Flash Winbond W25Q32BV */
spi-flash@0 {
compatible = "st,w25q32";
spi-max-frequency = <20000000>;
reg = <0>;
};
};

38
arch/arm/boot/dts/dove-dove-db.dts 100644
View File

@ -0,0 +1,38 @@
/dts-v1/;
/include/ "dove.dtsi"
/ {
model = "Marvell DB-MV88AP510-BP Development Board";
compatible = "marvell,dove-db", "marvell,dove";
memory {
device_type = "memory";
reg = <0x00000000 0x40000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8 earlyprintk";
};
};
&uart0 { status = "okay"; };
&uart1 { status = "okay"; };
&sdio0 { status = "okay"; };
&sdio1 { status = "okay"; };
&sata0 { status = "okay"; };
&spi0 {
status = "okay";
/* spi0.0: 4M Flash ST-M25P32-VMF6P */
spi-flash@0 {
compatible = "st,m25p32";
spi-max-frequency = <20000000>;
reg = <0>;
};
};
&i2c0 {
status = "okay";
};

143
arch/arm/boot/dts/dove.dtsi 100644
View File

@ -0,0 +1,143 @@
/include/ "skeleton.dtsi"
/ {
compatible = "marvell,dove";
model = "Marvell Armada 88AP510 SoC";
interrupt-parent = <&intc>;
intc: interrupt-controller {
compatible = "marvell,orion-intc";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0xf1020204 0x04>,
<0xf1020214 0x04>;
};
mbus@f1000000 {
compatible = "simple-bus";
ranges = <0 0xf1000000 0x4000000>;
#address-cells = <1>;
#size-cells = <1>;
uart0: serial@12000 {
compatible = "ns16550a";
reg = <0x12000 0x100>;
reg-shift = <2>;
interrupts = <7>;
clock-frequency = <166666667>;
status = "disabled";
};
uart1: serial@12100 {
compatible = "ns16550a";
reg = <0x12100 0x100>;
reg-shift = <2>;
interrupts = <8>;
clock-frequency = <166666667>;
status = "disabled";
};
uart2: serial@12200 {
compatible = "ns16550a";
reg = <0x12000 0x100>;
reg-shift = <2>;
interrupts = <9>;
clock-frequency = <166666667>;
status = "disabled";
};
uart3: serial@12300 {
compatible = "ns16550a";
reg = <0x12100 0x100>;
reg-shift = <2>;
interrupts = <10>;
clock-frequency = <166666667>;
status = "disabled";
};
wdt: wdt@20300 {
compatible = "marvell,orion-wdt";
reg = <0x20300 0x28>;
};
gpio0: gpio@d0400 {
compatible = "marvell,orion-gpio";
#gpio-cells = <2>;
gpio-controller;
reg = <0xd0400 0x20>;
ngpio = <32>;
interrupts = <12>, <13>, <14>, <60>;
};
gpio1: gpio@d0420 {
compatible = "marvell,orion-gpio";
#gpio-cells = <2>;
gpio-controller;
reg = <0xd0420 0x20>;
ngpio = <32>;
interrupts = <61>;
};
gpio2: gpio@e8400 {
compatible = "marvell,orion-gpio";
#gpio-cells = <2>;
gpio-controller;
reg = <0xe8400 0x0c>;
ngpio = <8>;
};
spi0: spi@10600 {
compatible = "marvell,orion-spi";
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
interrupts = <6>;
reg = <0x10600 0x28>;
status = "disabled";
};
spi1: spi@14600 {
compatible = "marvell,orion-spi";
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
interrupts = <5>;
reg = <0x14600 0x28>;
status = "disabled";
};
i2c0: i2c@11000 {
compatible = "marvell,mv64xxx-i2c";
reg = <0x11000 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <11>;
clock-frequency = <400000>;
timeout-ms = <1000>;
status = "disabled";
};
sdio0: sdio@92000 {
compatible = "marvell,dove-sdhci";
reg = <0x92000 0x100>;
interrupts = <35>, <37>;
status = "disabled";
};
sdio1: sdio@90000 {
compatible = "marvell,dove-sdhci";
reg = <0x90000 0x100>;
interrupts = <36>, <38>;
status = "disabled";
};
sata0: sata@a0000 {
compatible = "marvell,orion-sata";
reg = <0xa0000 0x2400>;
interrupts = <62>;
nr-ports = <1>;
status = "disabled";
};
};
};

10
arch/arm/boot/dts/kirkwood-dnskw.dtsi
View File

@ -25,6 +25,16 @@
};
};
gpio_fan {
/* Fan: ADDA AD045HB-G73 40mm 6000rpm@5v */
compatible = "gpio-fan";
gpios = <&gpio1 14 1
&gpio1 13 1>;
gpio-fan,speed-map = <0 0
3000 1
6000 2>;
};
ocp@f1000000 {
sata@80000 {
status = "okay";

57
arch/arm/boot/dts/kirkwood-dockstar.dts 100644
View File

@ -0,0 +1,57 @@
/dts-v1/;
/include/ "kirkwood.dtsi"
/ {
model = "Seagate FreeAgent Dockstar";
compatible = "seagate,dockstar", "marvell,kirkwood-88f6281", "marvell,kirkwood";
memory {
device_type = "memory";
reg = <0x00000000 0x8000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10";
};
ocp@f1000000 {
serial@12000 {
clock-frequency = <200000000>;
status = "ok";
};
nand@3000000 {
status = "okay";
partition@0 {
label = "u-boot";
reg = <0x0000000 0x100000>;
read-only;
};
partition@100000 {
label = "uImage";
reg = <0x0100000 0x400000>;
};
partition@500000 {
label = "data";
reg = <0x0500000 0xfb00000>;
};
};
};
gpio-leds {
compatible = "gpio-leds";
health {
label = "status:green:health";
gpios = <&gpio1 14 1>;
linux,default-trigger = "default-on";
};
fault {
label = "status:orange:fault";
gpios = <&gpio1 15 1>;
};
};
};

50
arch/arm/boot/dts/kirkwood-iconnect.dts
View File

@ -12,7 +12,7 @@
};
chosen {
bootargs = "console=ttyS0,115200n8 earlyprintk mtdparts=orion_nand:0xc0000@0x0(uboot),0x20000@0xa0000(env),0x300000@0x100000(zImage),0x300000@0x540000(initrd),0x1f400000@0x980000(boot)";
bootargs = "console=ttyS0,115200n8 earlyprintk";
linux,initrd-start = <0x4500040>;
linux,initrd-end = <0x4800000>;
};
@ -30,7 +30,37 @@
clock-frequency = <200000000>;
status = "ok";
};
nand@3000000 {
status = "okay";
partition@0 {
label = "uboot";
reg = <0x0000000 0xc0000>;
};
partition@a0000 {
label = "env";
reg = <0xa0000 0x20000>;
};
partition@100000 {
label = "zImage";
reg = <0x100000 0x300000>;
};
partition@540000 {
label = "initrd";
reg = <0x540000 0x300000>;
};
partition@980000 {
label = "boot";
reg = <0x980000 0x1f400000>;
};
};
};
gpio-leds {
compatible = "gpio-leds";
@ -69,4 +99,22 @@
gpios = <&gpio1 16 0>;
};
};
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
button@1 {
label = "OTB Button";
linux,code = <133>;
gpios = <&gpio1 3 1>;
debounce-interval = <100>;
};
button@2 {
label = "Reset";
linux,code = <0x198>;
gpios = <&gpio0 12 1>;
debounce-interval = <100>;
};
};
};

105
arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts 100644
View File

@ -0,0 +1,105 @@
/dts-v1/;
/include/ "kirkwood.dtsi"
/ {
model = "Iomega StorCenter ix2-200";
compatible = "iom,ix2-200", "marvell,kirkwood-88f6281", "marvell,kirkwood";
memory {
device_type = "memory";
reg = <0x00000000 0x10000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8 earlyprintk";
};
ocp@f1000000 {
i2c@11000 {
status = "okay";
lm63: lm63@4c {
compatible = "national,lm63";
reg = <0x4c>;
};
};
serial@12000 {
clock-frequency = <200000000>;
status = "ok";
};
nand@3000000 {
status = "okay";
partition@0 {
label = "u-boot";
reg = <0x0000000 0x100000>;
read-only;
};
partition@a0000 {
label = "env";
reg = <0xa0000 0x20000>;
read-only;
};
partition@100000 {
label = "uImage";
reg = <0x100000 0x300000>;
};
partition@400000 {
label = "uInitrd";
reg = <0x540000 0x1000000>;
};
};
sata@80000 {
status = "okay";
nr-ports = <2>;
};
};
gpio-leds {
compatible = "gpio-leds";
power_led {
label = "status:white:power_led";
gpios = <&gpio0 16 0>;
linux,default-trigger = "default-on";
};
health_led1 {
label = "status:red:health_led";
gpios = <&gpio1 5 0>;
};
health_led2 {
label = "status:white:health_led";
gpios = <&gpio1 4 0>;
};
backup_led {
label = "status:blue:backup_led";
gpios = <&gpio0 15 0>;
};
};
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
Power {
label = "Power Button";
linux,code = <116>;
gpios = <&gpio0 14 1>;
};
Reset {
label = "Reset Button";
linux,code = <0x198>;
gpios = <&gpio0 12 1>;
};
OTB {
label = "OTB Button";
linux,code = <133>;
gpios = <&gpio1 3 1>;
};
};
};

29
arch/arm/boot/dts/kirkwood-km_kirkwood.dts 100644
View File

@ -0,0 +1,29 @@
/dts-v1/;
/include/ "kirkwood.dtsi"
/ {
model = "Keymile Kirkwood Reference Design";
compatible = "keymile,km_kirkwood", "marvell,kirkwood-98DX4122", "marvell,kirkwood";
memory {
device_type = "memory";
reg = <0x00000000 0x08000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8 earlyprintk";
};
ocp@f1000000 {
serial@12000 {
clock-frequency = <200000000>;
status = "ok";
};
nand@3000000 {
status = "ok";
chip-delay = <25>;
};
};
};

12
arch/arm/boot/dts/kirkwood.dtsi
View File

@ -14,7 +14,8 @@
ocp@f1000000 {
compatible = "simple-bus";
ranges = <0 0xf1000000 0x4000000>;
ranges = <0x00000000 0xf1000000 0x4000000
0xf5000000 0xf5000000 0x0000400>;
#address-cells = <1>;
#size-cells = <1>;
@ -105,5 +106,14 @@
clock-frequency = <100000>;
status = "disabled";
};
crypto@30000 {
compatible = "marvell,orion-crypto";
reg = <0x30000 0x10000>,
<0xf5000000 0x800>;
reg-names = "regs", "sram";
interrupts = <22>;
status = "okay";
};
};
};

38
arch/arm/configs/kirkwood_defconfig
View File

@ -1,5 +1,7 @@
CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_LOG_BUF_SHIFT=19
CONFIG_PROFILING=y
CONFIG_OPROFILE=y
@ -15,9 +17,19 @@ CONFIG_MACH_MV88F6281GTW_GE=y
CONFIG_MACH_SHEEVAPLUG=y
CONFIG_MACH_ESATA_SHEEVAPLUG=y
CONFIG_MACH_GURUPLUG=y
CONFIG_MACH_DOCKSTAR=y
CONFIG_MACH_DREAMPLUG_DT=y
CONFIG_MACH_ICONNECT_DT=y
CONFIG_MACH_DLINK_KIRKWOOD_DT=y
CONFIG_MACH_IB62X0_DT=y
CONFIG_MACH_TS219_DT=y
CONFIG_MACH_DOCKSTAR_DT=y
CONFIG_MACH_GOFLEXNET_DT=y
CONFIG_MACH_LSXL_DT=y
CONFIG_MACH_IOMEGA_IX2_200_DT=y
CONFIG_MACH_KM_KIRKWOOD_DT=y
CONFIG_MACH_TS219=y
CONFIG_MACH_TS41X=y
CONFIG_MACH_DOCKSTAR=y
CONFIG_MACH_OPENRD_BASE=y
CONFIG_MACH_OPENRD_CLIENT=y
CONFIG_MACH_OPENRD_ULTIMATE=y
@ -29,8 +41,6 @@ CONFIG_MACH_NET2BIG_V2=y
CONFIG_MACH_NET5BIG_V2=y
CONFIG_MACH_T5325=y
# CONFIG_CPU_FEROCEON_OLD_ID is not set
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
# CONFIG_OABI_COMPAT is not set
@ -47,13 +57,11 @@ CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
# CONFIG_IPV6 is not set
CONFIG_NET_DSA=y
CONFIG_NET_DSA_MV88E6123_61_65=y
CONFIG_NET_PKTGEN=m
CONFIG_CFG80211=y
CONFIG_MAC80211=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
@ -69,7 +77,6 @@ CONFIG_MTD_M25P80=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_ORION=y
CONFIG_BLK_DEV_LOOP=y
# CONFIG_MISC_DEVICES is not set
# CONFIG_SCSI_PROC_FS is not set
CONFIG_BLK_DEV_SD=y
CONFIG_BLK_DEV_SR=m
@ -78,22 +85,21 @@ CONFIG_ATA=y
CONFIG_SATA_AHCI=y
CONFIG_SATA_MV=y
CONFIG_NETDEVICES=y
CONFIG_MARVELL_PHY=y
CONFIG_NET_ETHERNET=y
CONFIG_MII=y
CONFIG_NET_PCI=y
CONFIG_NET_DSA_MV88E6123_61_65=y
CONFIG_MV643XX_ETH=y
# CONFIG_NETDEV_10000 is not set
CONFIG_MARVELL_PHY=y
CONFIG_LIBERTAS=y
CONFIG_LIBERTAS_SDIO=y
CONFIG_INPUT_EVDEV=y
CONFIG_KEYBOARD_GPIO=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_LEGACY_PTY_COUNT=16
# CONFIG_DEVKMEM is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
CONFIG_LEGACY_PTY_COUNT=16
CONFIG_SERIAL_OF_PLATFORM=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
# CONFIG_I2C_COMPAT is not set
@ -103,7 +109,8 @@ CONFIG_SPI=y
CONFIG_SPI_ORION=y
CONFIG_GPIO_SYSFS=y
# CONFIG_HWMON is not set
# CONFIG_VGA_CONSOLE is not set
CONFIG_WATCHDOG=y
CONFIG_ORION_WATCHDOG=y
CONFIG_HID_DRAGONRISE=y
CONFIG_HID_GYRATION=y
CONFIG_HID_TWINHAN=y
@ -119,10 +126,8 @@ CONFIG_HID_TOPSEED=y
CONFIG_HID_THRUSTMASTER=y
CONFIG_HID_ZEROPLUS=y
CONFIG_USB=y
CONFIG_USB_DEVICEFS=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_ROOT_HUB_TT=y
CONFIG_USB_EHCI_TT_NEWSCHED=y
CONFIG_USB_PRINTER=m
CONFIG_USB_STORAGE=y
CONFIG_USB_STORAGE_DATAFAB=y
@ -148,7 +153,6 @@ CONFIG_MV_XOR=y
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
# CONFIG_EXT3_FS_XATTR is not set
CONFIG_INOTIFY=y
CONFIG_ISO9660_FS=m
CONFIG_JOLIET=y
CONFIG_UDF_FS=m
@ -158,7 +162,6 @@ CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
CONFIG_CRAMFS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_ROOT_NFS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_850=y
@ -171,11 +174,8 @@ CONFIG_DEBUG_KERNEL=y
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_PREEMPT is not set
CONFIG_DEBUG_INFO=y
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y
# CONFIG_FTRACE is not set
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_ERRORS=y
CONFIG_DEBUG_LL=y
CONFIG_CRYPTO_CBC=m
CONFIG_CRYPTO_PCBC=m

2
arch/arm/configs/mvebu_defconfig
View File

@ -21,6 +21,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_SYSFS=y
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
# CONFIG_EXT3_FS_XATTR is not set

7
arch/arm/mach-dove/Kconfig
View File

@ -15,6 +15,13 @@ config MACH_CM_A510
Say 'Y' here if you want your kernel to support the
CompuLab CM-A510 Board.
config MACH_DOVE_DT
bool "Marvell Dove Flattened Device Tree"
select USE_OF
help
Say 'Y' here if you want your kernel to support the
Marvell Dove using flattened device tree.
endmenu
endif

4
arch/arm/mach-dove/Makefile
View File

@ -1,4 +1,4 @@
obj-y += common.o addr-map.o irq.o pcie.o mpp.o
obj-y += common.o addr-map.o irq.o mpp.o
obj-$(CONFIG_PCI) += pcie.o
obj-$(CONFIG_MACH_DOVE_DB) += dove-db-setup.o
obj-$(CONFIG_MACH_CM_A510) += cm-a510.o

157
arch/arm/mach-dove/common.c
View File

@ -16,6 +16,8 @@
#include <linux/clk-provider.h>
#include <linux/ata_platform.h>
#include <linux/gpio.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <asm/page.h>
#include <asm/setup.h>
#include <asm/timex.h>
@ -24,6 +26,7 @@
#include <asm/mach/time.h>
#include <asm/mach/pci.h>
#include <mach/dove.h>
#include <mach/pm.h>
#include <mach/bridge-regs.h>
#include <asm/mach/arch.h>
#include <linux/irq.h>
@ -33,19 +36,17 @@
#include <plat/addr-map.h>
#include "common.h"
static int get_tclk(void);
/*****************************************************************************
* I/O Address Mapping
****************************************************************************/
static struct map_desc dove_io_desc[] __initdata = {
{
.virtual = DOVE_SB_REGS_VIRT_BASE,
.virtual = (unsigned long) DOVE_SB_REGS_VIRT_BASE,
.pfn = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE),
.length = DOVE_SB_REGS_SIZE,
.type = MT_DEVICE,
}, {
.virtual = DOVE_NB_REGS_VIRT_BASE,
.virtual = (unsigned long) DOVE_NB_REGS_VIRT_BASE,
.pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
.length = DOVE_NB_REGS_SIZE,
.type = MT_DEVICE,
@ -60,14 +61,69 @@ void __init dove_map_io(void)
/*****************************************************************************
* CLK tree
****************************************************************************/
static int dove_tclk;
static DEFINE_SPINLOCK(gating_lock);
static struct clk *tclk;
static void __init clk_init(void)
static struct clk __init *dove_register_gate(const char *name,
const char *parent, u8 bit_idx)
{
tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
get_tclk());
return clk_register_gate(NULL, name, parent, 0,
(void __iomem *)CLOCK_GATING_CONTROL,
bit_idx, 0, &gating_lock);
}
orion_clkdev_init(tclk);
static void __init dove_clk_init(void)
{
struct clk *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1;
struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma;
struct clk *xor0, *xor1, *ge, *gephy;
tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
dove_tclk);
usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0);
usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1);
sata = dove_register_gate("sata", "tclk", CLOCK_GATING_BIT_SATA);
pex0 = dove_register_gate("pex0", "tclk", CLOCK_GATING_BIT_PCIE0);
pex1 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE1);
sdio0 = dove_register_gate("sdio0", "tclk", CLOCK_GATING_BIT_SDIO0);
sdio1 = dove_register_gate("sdio1", "tclk", CLOCK_GATING_BIT_SDIO1);
nand = dove_register_gate("nand", "tclk", CLOCK_GATING_BIT_NAND);
camera = dove_register_gate("camera", "tclk", CLOCK_GATING_BIT_CAMERA);
i2s0 = dove_register_gate("i2s0", "tclk", CLOCK_GATING_BIT_I2S0);
i2s1 = dove_register_gate("i2s1", "tclk", CLOCK_GATING_BIT_I2S1);
crypto = dove_register_gate("crypto", "tclk", CLOCK_GATING_BIT_CRYPTO);
ac97 = dove_register_gate("ac97", "tclk", CLOCK_GATING_BIT_AC97);
pdma = dove_register_gate("pdma", "tclk", CLOCK_GATING_BIT_PDMA);
xor0 = dove_register_gate("xor0", "tclk", CLOCK_GATING_BIT_XOR0);
xor1 = dove_register_gate("xor1", "tclk", CLOCK_GATING_BIT_XOR1);
gephy = dove_register_gate("gephy", "tclk", CLOCK_GATING_BIT_GIGA_PHY);
ge = dove_register_gate("ge", "gephy", CLOCK_GATING_BIT_GBE);
orion_clkdev_add(NULL, "orion_spi.0", tclk);
orion_clkdev_add(NULL, "orion_spi.1", tclk);
orion_clkdev_add(NULL, "orion_wdt", tclk);
orion_clkdev_add(NULL, "mv64xxx_i2c.0", tclk);
orion_clkdev_add(NULL, "orion-ehci.0", usb0);
orion_clkdev_add(NULL, "orion-ehci.1", usb1);
orion_clkdev_add(NULL, "mv643xx_eth.0", ge);
orion_clkdev_add("0", "sata_mv.0", sata);
orion_clkdev_add("0", "pcie", pex0);
orion_clkdev_add("1", "pcie", pex1);
orion_clkdev_add(NULL, "sdhci-dove.0", sdio0);
orion_clkdev_add(NULL, "sdhci-dove.1", sdio1);
orion_clkdev_add(NULL, "orion_nand", nand);
orion_clkdev_add(NULL, "cafe1000-ccic.0", camera);
orion_clkdev_add(NULL, "kirkwood-i2s.0", i2s0);
orion_clkdev_add(NULL, "kirkwood-i2s.1", i2s1);
orion_clkdev_add(NULL, "mv_crypto", crypto);
orion_clkdev_add(NULL, "dove-ac97", ac97);
orion_clkdev_add(NULL, "dove-pdma", pdma);
orion_clkdev_add(NULL, "mv_xor_shared.0", xor0);
orion_clkdev_add(NULL, "mv_xor_shared.1", xor1);
}
/*****************************************************************************
@ -178,22 +234,31 @@ void __init dove_init_early(void)
orion_time_set_base(TIMER_VIRT_BASE);
}
static int get_tclk(void)
static int __init dove_find_tclk(void)
{
/* use DOVE_RESET_SAMPLE_HI/LO to detect tclk */
return 166666667;
}
static void __init dove_timer_init(void)
{
dove_tclk = dove_find_tclk();
orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
IRQ_DOVE_BRIDGE, get_tclk());
IRQ_DOVE_BRIDGE, dove_tclk);
}
struct sys_timer dove_timer = {
.init = dove_timer_init,
};
/*****************************************************************************
* Cryptographic Engines and Security Accelerator (CESA)
****************************************************************************/
void __init dove_crypto_init(void)
{
orion_crypto_init(DOVE_CRYPT_PHYS_BASE, DOVE_CESA_PHYS_BASE,
DOVE_CESA_SIZE, IRQ_DOVE_CRYPTO);
}
/*****************************************************************************
* XOR 0
****************************************************************************/
@ -275,8 +340,8 @@ void __init dove_sdio1_init(void)
void __init dove_init(void)
{
printk(KERN_INFO "Dove 88AP510 SoC, ");
printk(KERN_INFO "TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000);
pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
(dove_tclk + 499999) / 1000000);
#ifdef CONFIG_CACHE_TAUROS2
tauros2_init(0);
@ -284,7 +349,7 @@ void __init dove_init(void)
dove_setup_cpu_mbus();
/* Setup root of clk tree */
clk_init();
dove_clk_init();
/* internal devices that every board has */
dove_rtc_init();
@ -307,3 +372,67 @@ void dove_restart(char mode, const char *cmd)
while (1)
;
}
#if defined(CONFIG_MACH_DOVE_DT)
/*
* Auxdata required until real OF clock provider
*/
struct of_dev_auxdata dove_auxdata_lookup[] __initdata = {
OF_DEV_AUXDATA("marvell,orion-spi", 0xf1010600, "orion_spi.0", NULL),
OF_DEV_AUXDATA("marvell,orion-spi", 0xf1014600, "orion_spi.1", NULL),
OF_DEV_AUXDATA("marvell,orion-wdt", 0xf1020300, "orion_wdt", NULL),
OF_DEV_AUXDATA("marvell,mv64xxx-i2c", 0xf1011000, "mv64xxx_i2c.0",
NULL),
OF_DEV_AUXDATA("marvell,orion-sata", 0xf10a0000, "sata_mv.0", NULL),
OF_DEV_AUXDATA("marvell,dove-sdhci", 0xf1092000, "sdhci-dove.0", NULL),
OF_DEV_AUXDATA("marvell,dove-sdhci", 0xf1090000, "sdhci-dove.1", NULL),
{},
};
static struct mv643xx_eth_platform_data dove_dt_ge00_data = {
.phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT,
};
static void __init dove_dt_init(void)
{
pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
(dove_tclk + 499999) / 1000000);
#ifdef CONFIG_CACHE_TAUROS2
tauros2_init();
#endif
dove_setup_cpu_mbus();
/* Setup root of clk tree */
dove_clk_init();
/* Internal devices not ported to DT yet */
dove_rtc_init();
dove_xor0_init();
dove_xor1_init();
dove_ge00_init(&dove_dt_ge00_data);
dove_ehci0_init();
dove_ehci1_init();
dove_pcie_init(1, 1);
dove_crypto_init();
of_platform_populate(NULL, of_default_bus_match_table,
dove_auxdata_lookup, NULL);
}
static const char * const dove_dt_board_compat[] = {
"marvell,dove",
NULL
};
DT_MACHINE_START(DOVE_DT, "Marvell Dove (Flattened Device Tree)")
.map_io = dove_map_io,
.init_early = dove_init_early,
.init_irq = orion_dt_init_irq,
.timer = &dove_timer,
.init_machine = dove_dt_init,
.restart = dove_restart,
.dt_compat = dove_dt_board_compat,
MACHINE_END
#endif

4
arch/arm/mach-dove/common.h
View File

@ -26,7 +26,11 @@ void dove_init_irq(void);
void dove_setup_cpu_mbus(void);
void dove_ge00_init(struct mv643xx_eth_platform_data *eth_data);
void dove_sata_init(struct mv_sata_platform_data *sata_data);
#ifdef CONFIG_PCI
void dove_pcie_init(int init_port0, int init_port1);
#else
static inline void dove_pcie_init(int init_port0, int init_port1) { }
#endif
void dove_ehci0_init(void);
void dove_ehci1_init(void);
void dove_uart0_init(void);

16
arch/arm/mach-dove/include/mach/bridge-regs.h
View File

@ -13,22 +13,22 @@
#include <mach/dove.h>
#define CPU_CONFIG (BRIDGE_VIRT_BASE | 0x0000)
#define CPU_CONFIG (BRIDGE_VIRT_BASE + 0x0000)
#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104)
#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104)
#define CPU_CTRL_PCIE0_LINK 0x00000001
#define CPU_RESET 0x00000002
#define CPU_CTRL_PCIE1_LINK 0x00000008
#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
#define SOFT_RESET_OUT_EN 0x00000004
#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c)
#define SOFT_RESET 0x00000001
#define BRIDGE_INT_TIMER1_CLR (~0x0004)
#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200)
#define IRQ_CAUSE_LOW_OFF 0x0000
#define IRQ_MASK_LOW_OFF 0x0004
#define FIQ_MASK_LOW_OFF 0x0008
@ -47,9 +47,9 @@
#define ENDPOINT_MASK_HIGH (IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF)
#define PCIE_INTERRUPT_MASK (IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF)
#define POWER_MANAGEMENT (BRIDGE_VIRT_BASE | 0x011c)
#define POWER_MANAGEMENT (BRIDGE_VIRT_BASE + 0x011c)
#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE | 0x0300)
#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300)
#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300)
#endif

126
arch/arm/mach-dove/include/mach/dove.h
View File

@ -25,7 +25,7 @@
*/
#define DOVE_CESA_PHYS_BASE 0xc8000000
#define DOVE_CESA_VIRT_BASE 0xfdb00000
#define DOVE_CESA_VIRT_BASE IOMEM(0xfdb00000)
#define DOVE_CESA_SIZE SZ_1M
#define DOVE_PCIE0_MEM_PHYS_BASE 0xe0000000
@ -38,15 +38,15 @@
#define DOVE_BOOTROM_SIZE SZ_128M
#define DOVE_SCRATCHPAD_PHYS_BASE 0xf0000000
#define DOVE_SCRATCHPAD_VIRT_BASE 0xfdd00000
#define DOVE_SCRATCHPAD_VIRT_BASE IOMEM(0xfdd00000)
#define DOVE_SCRATCHPAD_SIZE SZ_1M
#define DOVE_SB_REGS_PHYS_BASE 0xf1000000
#define DOVE_SB_REGS_VIRT_BASE 0xfde00000
#define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfde00000)
#define DOVE_SB_REGS_SIZE SZ_8M
#define DOVE_NB_REGS_PHYS_BASE 0xf1800000
#define DOVE_NB_REGS_VIRT_BASE 0xfe600000
#define DOVE_NB_REGS_VIRT_BASE IOMEM(0xfe600000)
#define DOVE_NB_REGS_SIZE SZ_8M
#define DOVE_PCIE0_IO_PHYS_BASE 0xf2000000
@ -62,75 +62,75 @@
*/
/* SPI, I2C, UART */
#define DOVE_I2C_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x11000)
#define DOVE_UART0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12000)
#define DOVE_UART0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12000)
#define DOVE_UART1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12100)
#define DOVE_UART1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12100)
#define DOVE_UART2_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12200)
#define DOVE_UART2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12200)
#define DOVE_UART3_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12300)
#define DOVE_UART3_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12300)
#define DOVE_SPI0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x10600)
#define DOVE_SPI1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x14600)
#define DOVE_I2C_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x11000)
#define DOVE_UART0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12000)
#define DOVE_UART0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12000)
#define DOVE_UART1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12100)
#define DOVE_UART1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12100)
#define DOVE_UART2_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12200)
#define DOVE_UART2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12200)
#define DOVE_UART3_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12300)
#define DOVE_UART3_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12300)
#define DOVE_SPI0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x10600)
#define DOVE_SPI1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x14600)
/* North-South Bridge */
#define BRIDGE_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x20000)
#define BRIDGE_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x20000)
#define BRIDGE_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x20000)
#define BRIDGE_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x20000)
/* Cryptographic Engine */
#define DOVE_CRYPT_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x30000)
#define DOVE_CRYPT_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x30000)
/* PCIe 0 */
#define DOVE_PCIE0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x40000)
#define DOVE_PCIE0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x40000)
/* USB */
#define DOVE_USB0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x50000)
#define DOVE_USB1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x51000)
#define DOVE_USB0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x50000)
#define DOVE_USB1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x51000)
/* XOR 0 Engine */
#define DOVE_XOR0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60800)
#define DOVE_XOR0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60800)
#define DOVE_XOR0_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60A00)
#define DOVE_XOR0_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60A00)
#define DOVE_XOR0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60800)
#define DOVE_XOR0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60800)
#define DOVE_XOR0_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60A00)
#define DOVE_XOR0_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60A00)
/* XOR 1 Engine */
#define DOVE_XOR1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60900)
#define DOVE_XOR1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60900)
#define DOVE_XOR1_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60B00)
#define DOVE_XOR1_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60B00)
#define DOVE_XOR1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60900)
#define DOVE_XOR1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60900)
#define DOVE_XOR1_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60B00)
#define DOVE_XOR1_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60B00)
/* Gigabit Ethernet */
#define DOVE_GE00_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x70000)
#define DOVE_GE00_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x70000)
/* PCIe 1 */
#define DOVE_PCIE1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x80000)
#define DOVE_PCIE1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x80000)
/* CAFE */
#define DOVE_SDIO0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x92000)
#define DOVE_SDIO1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x90000)
#define DOVE_CAM_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x94000)
#define DOVE_CAFE_WIN_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x98000)
#define DOVE_SDIO0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x92000)
#define DOVE_SDIO1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x90000)
#define DOVE_CAM_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x94000)
#define DOVE_CAFE_WIN_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x98000)
/* SATA */
#define DOVE_SATA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xa0000)
#define DOVE_SATA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xa0000)
/* I2S/SPDIF */
#define DOVE_AUD0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xb0000)
#define DOVE_AUD1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xb4000)
#define DOVE_AUD0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xb0000)
#define DOVE_AUD1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xb4000)
/* NAND Flash Controller */
#define DOVE_NFC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xc0000)
#define DOVE_NFC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xc0000)
/* MPP, GPIO, Reset Sampling */
#define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0200)
#define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0200)
#define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10)
#define DOVE_RESET_SAMPLE_LO (DOVE_MPP_VIRT_BASE | 0x014)
#define DOVE_RESET_SAMPLE_HI (DOVE_MPP_VIRT_BASE | 0x018)
#define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0400)
#define DOVE_GPIO_HI_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0420)
#define DOVE_GPIO2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe8400)
#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe803c)
#define DOVE_RESET_SAMPLE_LO (DOVE_MPP_VIRT_BASE + 0x014)
#define DOVE_RESET_SAMPLE_HI (DOVE_MPP_VIRT_BASE + 0x018)
#define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0400)
#define DOVE_GPIO_HI_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0420)
#define DOVE_GPIO2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe8400)
#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe803c)
#define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1)
#define DOVE_NAND_GPIO_EN (1 << 0)
#define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40)
@ -142,44 +142,44 @@
#define DOVE_SD0_GPIO_SEL (1 << 0)
/* Power Management */
#define DOVE_PMU_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0000)
#define DOVE_PMU_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0000)
#define DOVE_PMU_SIG_CTRL (DOVE_PMU_VIRT_BASE + 0x802c)
/* Real Time Clock */
#define DOVE_RTC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xd8500)
#define DOVE_RTC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xd8500)
/* AC97 */
#define DOVE_AC97_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xe0000)
#define DOVE_AC97_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe0000)
#define DOVE_AC97_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xe0000)
#define DOVE_AC97_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe0000)
/* Peripheral DMA */
#define DOVE_PDMA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xe4000)
#define DOVE_PDMA_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe4000)
#define DOVE_PDMA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xe4000)
#define DOVE_PDMA_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe4000)
#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE | 0xe802C)
#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C)
#define DOVE_TWSI_ENABLE_OPTION1 (1 << 7)
#define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE | 0xe8030)
#define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE + 0xe8030)
#define DOVE_TWSI_ENABLE_OPTION2 (1 << 20)
#define DOVE_TWSI_ENABLE_OPTION3 (1 << 21)
#define DOVE_TWSI_OPTION3_GPIO (1 << 22)
#define DOVE_SSP_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xec000)
#define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE | 0xe8034)
#define DOVE_SSP_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xec000)
#define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE + 0xe8034)
#define DOVE_SSP_ON_AU1 (1 << 0)
#define DOVE_SSP_CLOCK_ENABLE (1 << 1)
#define DOVE_SSP_BPB_CLOCK_SRC_SSP (1 << 11)
/* Memory Controller */
#define DOVE_MC_VIRT_BASE (DOVE_NB_REGS_VIRT_BASE | 0x00000)
#define DOVE_MC_VIRT_BASE (DOVE_NB_REGS_VIRT_BASE + 0x00000)
/* LCD Controller */
#define DOVE_LCD_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x10000)
#define DOVE_LCD1_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x20000)
#define DOVE_LCD2_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x10000)
#define DOVE_LCD_DCON_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x30000)
#define DOVE_LCD_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x10000)
#define DOVE_LCD1_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x20000)
#define DOVE_LCD2_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x10000)
#define DOVE_LCD_DCON_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x30000)
/* Graphic Engine */
#define DOVE_GPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x40000)
#define DOVE_GPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x40000)
/* Video Engine */
#define DOVE_VPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x400000)
#define DOVE_VPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x400000)
#endif

54
arch/arm/mach-dove/include/mach/pm.h
View File

@ -13,24 +13,42 @@
#include <mach/irqs.h>
#define CLOCK_GATING_CONTROL (DOVE_PMU_VIRT_BASE + 0x38)
#define CLOCK_GATING_USB0_MASK (1 << 0)
#define CLOCK_GATING_USB1_MASK (1 << 1)
#define CLOCK_GATING_GBE_MASK (1 << 2)
#define CLOCK_GATING_SATA_MASK (1 << 3)
#define CLOCK_GATING_PCIE0_MASK (1 << 4)
#define CLOCK_GATING_PCIE1_MASK (1 << 5)
#define CLOCK_GATING_SDIO0_MASK (1 << 8)
#define CLOCK_GATING_SDIO1_MASK (1 << 9)
#define CLOCK_GATING_NAND_MASK (1 << 10)
#define CLOCK_GATING_CAMERA_MASK (1 << 11)
#define CLOCK_GATING_I2S0_MASK (1 << 12)
#define CLOCK_GATING_I2S1_MASK (1 << 13)
#define CLOCK_GATING_CRYPTO_MASK (1 << 15)
#define CLOCK_GATING_AC97_MASK (1 << 21)
#define CLOCK_GATING_PDMA_MASK (1 << 22)
#define CLOCK_GATING_XOR0_MASK (1 << 23)
#define CLOCK_GATING_XOR1_MASK (1 << 24)
#define CLOCK_GATING_GIGA_PHY_MASK (1 << 30)
#define CLOCK_GATING_BIT_USB0 0
#define CLOCK_GATING_BIT_USB1 1
#define CLOCK_GATING_BIT_GBE 2
#define CLOCK_GATING_BIT_SATA 3
#define CLOCK_GATING_BIT_PCIE0 4
#define CLOCK_GATING_BIT_PCIE1 5
#define CLOCK_GATING_BIT_SDIO0 8
#define CLOCK_GATING_BIT_SDIO1 9
#define CLOCK_GATING_BIT_NAND 10
#define CLOCK_GATING_BIT_CAMERA 11
#define CLOCK_GATING_BIT_I2S0 12
#define CLOCK_GATING_BIT_I2S1 13
#define CLOCK_GATING_BIT_CRYPTO 15
#define CLOCK_GATING_BIT_AC97 21
#define CLOCK_GATING_BIT_PDMA 22
#define CLOCK_GATING_BIT_XOR0 23
#define CLOCK_GATING_BIT_XOR1 24
#define CLOCK_GATING_BIT_GIGA_PHY 30
#define CLOCK_GATING_USB0_MASK (1 << CLOCK_GATING_BIT_USB0)
#define CLOCK_GATING_USB1_MASK (1 << CLOCK_GATING_BIT_USB1)
#define CLOCK_GATING_GBE_MASK (1 << CLOCK_GATING_BIT_GBE)
#define CLOCK_GATING_SATA_MASK (1 << CLOCK_GATING_BIT_SATA)
#define CLOCK_GATING_PCIE0_MASK (1 << CLOCK_GATING_BIT_PCIE0)
#define CLOCK_GATING_PCIE1_MASK (1 << CLOCK_GATING_BIT_PCIE1)
#define CLOCK_GATING_SDIO0_MASK (1 << CLOCK_GATING_BIT_SDIO0)
#define CLOCK_GATING_SDIO1_MASK (1 << CLOCK_GATING_BIT_SDIO1)
#define CLOCK_GATING_NAND_MASK (1 << CLOCK_GATING_BIT_NAND)
#define CLOCK_GATING_CAMERA_MASK (1 << CLOCK_GATING_BIT_CAMERA)
#define CLOCK_GATING_I2S0_MASK (1 << CLOCK_GATING_BIT_I2S0)
#define CLOCK_GATING_I2S1_MASK (1 << CLOCK_GATING_BIT_I2S1)
#define CLOCK_GATING_CRYPTO_MASK (1 << CLOCK_GATING_BIT_CRYPTO)
#define CLOCK_GATING_AC97_MASK (1 << CLOCK_GATING_BIT_AC97)
#define CLOCK_GATING_PDMA_MASK (1 << CLOCK_GATING_BIT_PDMA)
#define CLOCK_GATING_XOR0_MASK (1 << CLOCK_GATING_BIT_XOR0)
#define CLOCK_GATING_XOR1_MASK (1 << CLOCK_GATING_BIT_XOR1)
#define CLOCK_GATING_GIGA_PHY_MASK (1 << CLOCK_GATING_BIT_GIGA_PHY)
#define PMU_INTERRUPT_CAUSE (DOVE_PMU_VIRT_BASE + 0x50)
#define PMU_INTERRUPT_MASK (DOVE_PMU_VIRT_BASE + 0x54)

10
arch/arm/mach-dove/irq.c
View File

@ -100,19 +100,19 @@ void __init dove_init_irq(void)
{
int i;
orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
/*
* Initialize gpiolib for GPIOs 0-71.
*/
orion_gpio_init(NULL, 0, 32, (void __iomem *)DOVE_GPIO_LO_VIRT_BASE, 0,
orion_gpio_init(NULL, 0, 32, DOVE_GPIO_LO_VIRT_BASE, 0,
IRQ_DOVE_GPIO_START, gpio0_irqs);
orion_gpio_init(NULL, 32, 32, (void __iomem *)DOVE_GPIO_HI_VIRT_BASE, 0,
orion_gpio_init(NULL, 32, 32, DOVE_GPIO_HI_VIRT_BASE, 0,
IRQ_DOVE_GPIO_START + 32, gpio1_irqs);
orion_gpio_init(NULL, 64, 8, (void __iomem *)DOVE_GPIO2_VIRT_BASE, 0,
orion_gpio_init(NULL, 64, 8, DOVE_GPIO2_VIRT_BASE, 0,
IRQ_DOVE_GPIO_START + 64, gpio2_irqs);
/*

6
arch/arm/mach-dove/pcie.c
View File

@ -182,18 +182,18 @@ static struct hw_pci dove_pci __initdata = {
.map_irq = dove_pcie_map_irq,
};
static void __init add_pcie_port(int index, unsigned long base)
static void __init add_pcie_port(int index, void __iomem *base)
{
printk(KERN_INFO "Dove PCIe port %d: ", index);
if (orion_pcie_link_up((void __iomem *)base)) {
if (orion_pcie_link_up(base)) {
struct pcie_port *pp = &pcie_port[num_pcie_ports++];
printk(KERN_INFO "link up\n");
pp->index = index;
pp->root_bus_nr = -1;
pp->base = (void __iomem *)base;
pp->base = base;
spin_lock_init(&pp->conf_lock);
memset(&pp->res, 0, sizeof(pp->res));
} else {

21
arch/arm/mach-kirkwood/Kconfig
View File

@ -94,6 +94,13 @@ config MACH_TS219_DT
or MV6282. If you have the wrong one, the buttons will not
work.
config MACH_DOCKSTAR_DT
bool "Seagate FreeAgent Dockstar (Flattened Device Tree)"
select ARCH_KIRKWOOD_DT
help
Say 'Y' here if you want your kernel to support the
Seagate FreeAgent Dockstar (Flattened Device Tree).
config MACH_GOFLEXNET_DT
bool "Seagate GoFlex Net (Flattened Device Tree)"
select ARCH_KIRKWOOD_DT
@ -109,6 +116,20 @@ config MACH_LSXL_DT
Buffalo Linkstation LS-XHL & LS-CHLv2 devices, using
Flattened Device Tree.
config MACH_IOMEGA_IX2_200_DT
bool "Iomega StorCenter ix2-200 (Flattened Device Tree)"
select ARCH_KIRKWOOD_DT
help
Say 'Y' here if you want your kernel to support the
Iomega StorCenter ix2-200 (Flattened Device Tree).
config MACH_KM_KIRKWOOD_DT
bool "Keymile Kirkwood Reference Design (Flattened Device Tree)"
select ARCH_KIRKWOOD_DT
help
Say 'Y' here if you want your kernel to support the
Keymile Kirkwood Reference Desgin, using Flattened Device Tree.
config MACH_TS219
bool "QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and TS-219P+ Turbo NAS"
help

3
arch/arm/mach-kirkwood/Makefile
View File

@ -26,5 +26,8 @@ obj-$(CONFIG_MACH_ICONNECT_DT) += board-iconnect.o
obj-$(CONFIG_MACH_DLINK_KIRKWOOD_DT) += board-dnskw.o
obj-$(CONFIG_MACH_IB62X0_DT) += board-ib62x0.o
obj-$(CONFIG_MACH_TS219_DT) += board-ts219.o tsx1x-common.o
obj-$(CONFIG_MACH_DOCKSTAR_DT) += board-dockstar.o
obj-$(CONFIG_MACH_GOFLEXNET_DT) += board-goflexnet.o
obj-$(CONFIG_MACH_LSXL_DT) += board-lsxl.o
obj-$(CONFIG_MACH_IOMEGA_IX2_200_DT) += board-iomega_ix2_200.o
obj-$(CONFIG_MACH_KM_KIRKWOOD_DT) += board-km_kirkwood.o

3
arch/arm/mach-kirkwood/addr-map.c
View File

@ -86,5 +86,6 @@ void __init kirkwood_setup_cpu_mbus(void)
/*
* Setup MBUS dram target info.
*/
orion_setup_cpu_mbus_target(&addr_map_cfg, DDR_WINDOW_CPU_BASE);
orion_setup_cpu_mbus_target(&addr_map_cfg,
(void __iomem *) DDR_WINDOW_CPU_BASE);
}

35
arch/arm/mach-kirkwood/board-dnskw.c
View File

@ -14,18 +14,8 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/ata_platform.h>
#include <linux/mv643xx_eth.h>
#include <linux/of.h>
#include <linux/gpio.h>
#include <linux/input.h>
#include <linux/gpio-fan.h>
#include <linux/leds.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/kirkwood.h>
#include <mach/bridge-regs.h>
#include "common.h"
#include "mpp.h"
@ -67,29 +57,6 @@ static unsigned int dnskw_mpp_config[] __initdata = {
0
};
/* Fan: ADDA AD045HB-G73 40mm 6000rpm@5v */
static struct gpio_fan_speed dnskw_fan_speed[] = {
{ 0, 0 },
{ 3000, 1 },
{ 6000, 2 },
};
static unsigned dnskw_fan_pins[] = {46, 45};
static struct gpio_fan_platform_data dnskw_fan_data = {
.num_ctrl = ARRAY_SIZE(dnskw_fan_pins),
.ctrl = dnskw_fan_pins,
.num_speed = ARRAY_SIZE(dnskw_fan_speed),
.speed = dnskw_fan_speed,
};
static struct platform_device dnskw_fan_device = {
.name = "gpio-fan",
.id = -1,
.dev = {
.platform_data = &dnskw_fan_data,
},
};
static void dnskw_power_off(void)
{
gpio_set_value(36, 1);
@ -114,8 +81,6 @@ void __init dnskw_init(void)
kirkwood_ehci_init();
kirkwood_ge00_init(&dnskw_ge00_data);
platform_device_register(&dnskw_fan_device);
/* Register power-off GPIO. */
if (gpio_request(36, "dnskw:power:off") == 0
&& gpio_direction_output(36, 0) == 0)

61
arch/arm/mach-kirkwood/board-dockstar.c 100644
View File

@ -0,0 +1,61 @@
/*
* arch/arm/mach-kirkwood/board-dockstar.c
*
* Seagate FreeAgent Dockstar Board Init for drivers not converted to
* flattened device tree yet.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*
* Copied and modified for Seagate GoFlex Net support by
* Joshua Coombs <josh.coombs@gmail.com> based on ArchLinux ARM's
* GoFlex kernel patches.
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/ata_platform.h>
#include <linux/mv643xx_eth.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_fdt.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/gpio.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/kirkwood.h>
#include <mach/bridge-regs.h>
#include <linux/platform_data/mmc-mvsdio.h>
#include "common.h"
#include "mpp.h"
static struct mv643xx_eth_platform_data dockstar_ge00_data = {
.phy_addr = MV643XX_ETH_PHY_ADDR(0),
};
static unsigned int dockstar_mpp_config[] __initdata = {
MPP29_GPIO, /* USB Power Enable */
MPP46_GPIO, /* LED green */
MPP47_GPIO, /* LED orange */
0
};
void __init dockstar_dt_init(void)
{
/*
* Basic setup. Needs to be called early.
*/
kirkwood_mpp_conf(dockstar_mpp_config);
if (gpio_request(29, "USB Power Enable") != 0 ||
gpio_direction_output(29, 1) != 0)
pr_err("can't setup GPIO 29 (USB Power Enable)\n");
kirkwood_ehci_init();
kirkwood_ge00_init(&dockstar_ge00_data);
}

14
arch/arm/mach-kirkwood/board-dt.c
View File

@ -33,6 +33,7 @@ struct of_dev_auxdata kirkwood_auxdata_lookup[] __initdata = {
OF_DEV_AUXDATA("marvell,orion-wdt", 0xf1020300, "orion_wdt", NULL),
OF_DEV_AUXDATA("marvell,orion-sata", 0xf1080000, "sata_mv.0", NULL),
OF_DEV_AUXDATA("marvell,orion-nand", 0xf4000000, "orion_nand", NULL),
OF_DEV_AUXDATA("marvell,orion-crypto", 0xf1030000, "mv_crypto", NULL),
{},
};
@ -60,7 +61,6 @@ static void __init kirkwood_dt_init(void)
/* internal devices that every board has */
kirkwood_xor0_init();
kirkwood_xor1_init();
kirkwood_crypto_init();
#ifdef CONFIG_KEXEC
kexec_reinit = kirkwood_enable_pcie;
@ -81,12 +81,21 @@ static void __init kirkwood_dt_init(void)
if (of_machine_is_compatible("qnap,ts219"))
qnap_dt_ts219_init();
if (of_machine_is_compatible("seagate,dockstar"))
dockstar_dt_init();
if (of_machine_is_compatible("seagate,goflexnet"))
goflexnet_init();
if (of_machine_is_compatible("buffalo,lsxl"))
lsxl_init();
if (of_machine_is_compatible("iom,ix2-200"))
iomega_ix2_200_init();
if (of_machine_is_compatible("keymile,km_kirkwood"))
km_kirkwood_init();
of_platform_populate(NULL, kirkwood_dt_match_table,
kirkwood_auxdata_lookup, NULL);
}
@ -98,8 +107,11 @@ static const char *kirkwood_dt_board_compat[] = {
"iom,iconnect",
"raidsonic,ib-nas62x0",
"qnap,ts219",
"seagate,dockstar",
"seagate,goflexnet",
"buffalo,lsxl",
"iom,ix2-200",
"keymile,km_kirkwood",
NULL
};

48
arch/arm/mach-kirkwood/board-iconnect.c
View File

@ -16,11 +16,8 @@
#include <linux/of_fdt.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/mtd/partitions.h>
#include <linux/mv643xx_eth.h>
#include <linux/gpio.h>
#include <linux/input.h>
#include <linux/gpio_keys.h>
#include <asm/mach/arch.h>
#include <mach/kirkwood.h>
#include "common.h"
@ -44,57 +41,12 @@ static unsigned int iconnect_mpp_config[] __initdata = {
0
};
static struct mtd_partition iconnect_nand_parts[] = {
{
.name = "flash",
.offset = 0,
.size = MTDPART_SIZ_FULL,
},
};
/* yikes... theses are the original input buttons */
/* but I'm not convinced by the sw event choices */
static struct gpio_keys_button iconnect_buttons[] = {
{
.type = EV_SW,
.code = SW_LID,
.gpio = 12,
.desc = "Reset Button",
.active_low = 1,
.debounce_interval = 100,
}, {
.type = EV_SW,
.code = SW_TABLET_MODE,
.gpio = 35,
.desc = "OTB Button",
.active_low = 1,
.debounce_interval = 100,
},
};
static struct gpio_keys_platform_data iconnect_button_data = {
.buttons = iconnect_buttons,
.nbuttons = ARRAY_SIZE(iconnect_buttons),
};
static struct platform_device iconnect_button_device = {
.name = "gpio-keys",
.id = -1,
.num_resources = 0,
.dev = {
.platform_data = &iconnect_button_data,
},
};
void __init iconnect_init(void)
{
kirkwood_mpp_conf(iconnect_mpp_config);
kirkwood_nand_init(ARRAY_AND_SIZE(iconnect_nand_parts), 25);
kirkwood_ehci_init();
kirkwood_ge00_init(&iconnect_ge00_data);
platform_device_register(&iconnect_button_device);
}
static int __init iconnect_pci_init(void)

57
arch/arm/mach-kirkwood/board-iomega_ix2_200.c 100644
View File

@ -0,0 +1,57 @@
/*
* arch/arm/mach-kirkwood/board-iomega_ix2_200.c
*
* Iomega StorCenter ix2-200
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/mv643xx_eth.h>
#include <linux/ethtool.h>
#include <mach/kirkwood.h>
#include "common.h"
#include "mpp.h"
static struct mv643xx_eth_platform_data iomega_ix2_200_ge00_data = {
.phy_addr = MV643XX_ETH_PHY_NONE,
.speed = SPEED_1000,
.duplex = DUPLEX_FULL,
};
static unsigned int iomega_ix2_200_mpp_config[] __initdata = {
MPP12_GPIO, /* Reset Button */
MPP14_GPIO, /* Power Button */
MPP15_GPIO, /* Backup LED (blue) */
MPP16_GPIO, /* Power LED (white) */
MPP35_GPIO, /* OTB Button */
MPP36_GPIO, /* Rebuild LED (white) */
MPP37_GPIO, /* Health LED (red) */
MPP38_GPIO, /* SATA LED brightness control 1 */
MPP39_GPIO, /* SATA LED brightness control 2 */
MPP40_GPIO, /* Backup LED brightness control 1 */
MPP41_GPIO, /* Backup LED brightness control 2 */
MPP42_GPIO, /* Power LED brightness control 1 */
MPP43_GPIO, /* Power LED brightness control 2 */
MPP44_GPIO, /* Health LED brightness control 1 */
MPP45_GPIO, /* Health LED brightness control 2 */
MPP46_GPIO, /* Rebuild LED brightness control 1 */
MPP47_GPIO, /* Rebuild LED brightness control 2 */
0
};
void __init iomega_ix2_200_init(void)
{
/*
* Basic setup. Needs to be called early.
*/
kirkwood_mpp_conf(iomega_ix2_200_mpp_config);
kirkwood_ehci_init();
kirkwood_ge01_init(&iomega_ix2_200_ge00_data);
}

57
arch/arm/mach-kirkwood/board-km_kirkwood.c 100644
View File

@ -0,0 +1,57 @@
/*
* Copyright 2012 2012 KEYMILE AG, CH-3097 Bern
* Valentin Longchamp <valentin.longchamp@keymile.com>
*
* arch/arm/mach-kirkwood/board-km_kirkwood.c
*
* Keymile km_kirkwood Reference Desing Init for drivers not converted to
* flattened device tree yet.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/mv643xx_eth.h>
#include <linux/clk.h>
#include <linux/clk-private.h>
#include "common.h"
#include "mpp.h"
static struct mv643xx_eth_platform_data km_kirkwood_ge00_data = {
.phy_addr = MV643XX_ETH_PHY_ADDR(0),
};
static unsigned int km_kirkwood_mpp_config[] __initdata = {
MPP8_GPIO, /* I2C SDA */
MPP9_GPIO, /* I2C SCL */
0
};
void __init km_kirkwood_init(void)
{
struct clk *sata_clk;
/*
* Basic setup. Needs to be called early.
*/
kirkwood_mpp_conf(km_kirkwood_mpp_config);
/*
* Our variant of kirkwood (integrated in the Bobcat) hangs on accessing
* SATA bits (14-15) of the Clock Gating Control Register. Since these
* devices are also not present in this variant, their clocks get
* disabled because unused when clk_disable_unused() gets called.
* That's why we change the flags to these clocks to CLK_IGNORE_UNUSED
*/
sata_clk = clk_get_sys("sata_mv.0", "0");
if (!IS_ERR(sata_clk))
sata_clk->flags |= CLK_IGNORE_UNUSED;
sata_clk = clk_get_sys("sata_mv.0", "1");
if (!IS_ERR(sata_clk))
sata_clk->flags |= CLK_IGNORE_UNUSED;
kirkwood_ehci_init();
kirkwood_ge00_init(&km_kirkwood_ge00_data);
}

8
arch/arm/mach-kirkwood/common.c
View File

@ -42,7 +42,7 @@
****************************************************************************/
static struct map_desc kirkwood_io_desc[] __initdata = {
{
.virtual = KIRKWOOD_REGS_VIRT_BASE,
.virtual = (unsigned long) KIRKWOOD_REGS_VIRT_BASE,
.pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
.length = KIRKWOOD_REGS_SIZE,
.type = MT_DEVICE,
@ -205,8 +205,7 @@ static struct clk *tclk;
static struct clk __init *kirkwood_register_gate(const char *name, u8 bit_idx)
{
return clk_register_gate(NULL, name, "tclk", 0,
(void __iomem *)CLOCK_GATING_CTRL,
return clk_register_gate(NULL, name, "tclk", 0, CLOCK_GATING_CTRL,
bit_idx, 0, &gating_lock);
}
@ -215,8 +214,7 @@ static struct clk __init *kirkwood_register_gate_fn(const char *name,
void (*fn_en)(void),
void (*fn_dis)(void))
{
return clk_register_gate_fn(NULL, name, "tclk", 0,
(void __iomem *)CLOCK_GATING_CTRL,
return clk_register_gate_fn(NULL, name, "tclk", 0, CLOCK_GATING_CTRL,
bit_idx, 0, &gating_lock, fn_en, fn_dis);
}

18
arch/arm/mach-kirkwood/common.h
View File

@ -82,6 +82,12 @@ void ib62x0_init(void);
static inline void ib62x0_init(void) {};
#endif
#ifdef CONFIG_MACH_DOCKSTAR_DT
void dockstar_dt_init(void);
#else
static inline void dockstar_dt_init(void) {};
#endif
#ifdef CONFIG_MACH_GOFLEXNET_DT
void goflexnet_init(void);
#else
@ -94,6 +100,18 @@ void lsxl_init(void);
static inline void lsxl_init(void) {};
#endif
#ifdef CONFIG_MACH_IOMEGA_IX2_200_DT
void iomega_ix2_200_init(void);
#else
static inline void iomega_ix2_200_init(void) {};
#endif
#ifdef CONFIG_MACH_KM_KIRKWOOD_DT
void km_kirkwood_init(void);
#else
static inline void km_kirkwood_init(void) {};
#endif
/* early init functions not converted to fdt yet */
char *kirkwood_id(void);
void kirkwood_l2_init(void);

20
arch/arm/mach-kirkwood/include/mach/bridge-regs.h
View File

@ -13,37 +13,37 @@
#include <mach/kirkwood.h>
#define CPU_CONFIG (BRIDGE_VIRT_BASE | 0x0100)
#define CPU_CONFIG (BRIDGE_VIRT_BASE + 0x0100)
#define CPU_CONFIG_ERROR_PROP 0x00000004
#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104)
#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104)
#define CPU_RESET 0x00000002
#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
#define WDT_RESET_OUT_EN 0x00000002
#define SOFT_RESET_OUT_EN 0x00000004
#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c)
#define SOFT_RESET 0x00000001
#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE + 0x0110)
#define WDT_INT_REQ 0x0008
#define BRIDGE_INT_TIMER1_CLR (~0x0004)
#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200)
#define IRQ_CAUSE_LOW_OFF 0x0000
#define IRQ_MASK_LOW_OFF 0x0004
#define IRQ_CAUSE_HIGH_OFF 0x0010
#define IRQ_MASK_HIGH_OFF 0x0014
#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE | 0x0300)
#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300)
#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300)
#define L2_CONFIG_REG (BRIDGE_VIRT_BASE | 0x0128)
#define L2_CONFIG_REG (BRIDGE_VIRT_BASE + 0x0128)
#define L2_WRITETHROUGH 0x00000010
#define CLOCK_GATING_CTRL (BRIDGE_VIRT_BASE | 0x11c)
#define CLOCK_GATING_CTRL (BRIDGE_VIRT_BASE + 0x11c)
#define CGC_BIT_GE0 (0)
#define CGC_BIT_PEX0 (2)
#define CGC_BIT_USB0 (3)

92
arch/arm/mach-kirkwood/include/mach/kirkwood.h
View File

@ -45,7 +45,7 @@
#define KIRKWOOD_PCIE_IO_SIZE SZ_64K
#define KIRKWOOD_REGS_PHYS_BASE 0xf1000000
#define KIRKWOOD_REGS_VIRT_BASE 0xfed00000
#define KIRKWOOD_REGS_VIRT_BASE IOMEM(0xfed00000)
#define KIRKWOOD_REGS_SIZE SZ_1M
#define KIRKWOOD_PCIE_MEM_PHYS_BASE 0xe0000000
@ -59,61 +59,61 @@
/*
* Register Map
*/
#define DDR_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x00000)
#define DDR_WINDOW_CPU_BASE (DDR_VIRT_BASE | 0x1500)
#define DDR_OPERATION_BASE (DDR_VIRT_BASE | 0x1418)
#define DDR_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x00000)
#define DDR_WINDOW_CPU_BASE (DDR_VIRT_BASE + 0x1500)
#define DDR_OPERATION_BASE (DDR_VIRT_BASE + 0x1418)
#define DEV_BUS_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x10000)
#define DEV_BUS_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x10000)
#define SAMPLE_AT_RESET (DEV_BUS_VIRT_BASE | 0x0030)
#define DEVICE_ID (DEV_BUS_VIRT_BASE | 0x0034)
#define GPIO_LOW_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x0100)
#define GPIO_HIGH_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x0140)
#define RTC_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0300)
#define SPI_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0600)
#define I2C_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1000)
#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000)
#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000)
#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100)
#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100)
#define DEV_BUS_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x10000)
#define DEV_BUS_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x10000)
#define SAMPLE_AT_RESET (DEV_BUS_VIRT_BASE + 0x0030)
#define DEVICE_ID (DEV_BUS_VIRT_BASE + 0x0034)
#define GPIO_LOW_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x0100)
#define GPIO_HIGH_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x0140)
#define RTC_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x0300)
#define SPI_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x0600)
#define I2C_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1000)
#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2000)
#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2000)
#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2100)
#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2100)
#define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x20000)
#define BRIDGE_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x20000)
#define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x20000)
#define BRIDGE_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x20000)
#define CRYPTO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x30000)
#define CRYPTO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x30000)
#define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x40000)
#define PCIE_LINK_CTRL (PCIE_VIRT_BASE | 0x70)
#define PCIE_STATUS (PCIE_VIRT_BASE | 0x1a04)
#define PCIE1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x44000)
#define PCIE1_LINK_CTRL (PCIE1_VIRT_BASE | 0x70)
#define PCIE1_STATUS (PCIE1_VIRT_BASE | 0x1a04)
#define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x40000)
#define PCIE_LINK_CTRL (PCIE_VIRT_BASE + 0x70)
#define PCIE_STATUS (PCIE_VIRT_BASE + 0x1a04)
#define PCIE1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x44000)
#define PCIE1_LINK_CTRL (PCIE1_VIRT_BASE + 0x70)
#define PCIE1_STATUS (PCIE1_VIRT_BASE + 0x1a04)
#define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x50000)
#define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x50000)
#define XOR0_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x60800)
#define XOR0_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x60800)
#define XOR1_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x60900)
#define XOR1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x60900)
#define XOR0_HIGH_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x60A00)
#define XOR0_HIGH_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x60A00)
#define XOR1_HIGH_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x60B00)
#define XOR1_HIGH_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x60B00)
#define XOR0_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x60800)
#define XOR0_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x60800)
#define XOR1_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x60900)
#define XOR1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x60900)
#define XOR0_HIGH_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x60A00)
#define XOR0_HIGH_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x60A00)
#define XOR1_HIGH_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x60B00)
#define XOR1_HIGH_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x60B00)
#define GE00_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x70000)
#define GE01_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x74000)
#define GE00_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x70000)
#define GE01_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x74000)
#define SATA_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x80000)
#define SATA_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x80000)
#define SATA0_IF_CTRL (SATA_VIRT_BASE | 0x2050)
#define SATA0_PHY_MODE_2 (SATA_VIRT_BASE | 0x2330)
#define SATA1_IF_CTRL (SATA_VIRT_BASE | 0x4050)
#define SATA1_PHY_MODE_2 (SATA_VIRT_BASE | 0x4330)
#define SATA_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x80000)
#define SATA_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x80000)
#define SATA0_IF_CTRL (SATA_VIRT_BASE + 0x2050)
#define SATA0_PHY_MODE_2 (SATA_VIRT_BASE + 0x2330)
#define SATA1_IF_CTRL (SATA_VIRT_BASE + 0x4050)
#define SATA1_PHY_MODE_2 (SATA_VIRT_BASE + 0x4330)
#define SDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x90000)
#define SDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x90000)
#define AUDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0xA0000)
#define AUDIO_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0xA0000)
#define AUDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0xA0000)
#define AUDIO_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0xA0000)
/*
* Supported devices and revisions.

9
arch/arm/mach-kirkwood/irq.c
View File

@ -10,6 +10,7 @@
#include <linux/gpio.h>
#include <linux/kernel.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <mach/bridge-regs.h>
#include <plat/orion-gpio.h>
#include <plat/irq.h>
@ -30,14 +31,14 @@ static int __initdata gpio1_irqs[4] = {
void __init kirkwood_init_irq(void)
{
orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
/*
* Initialize gpiolib for GPIOs 0-49.
*/
orion_gpio_init(NULL, 0, 32, (void __iomem *)GPIO_LOW_VIRT_BASE, 0,
orion_gpio_init(NULL, 0, 32, GPIO_LOW_VIRT_BASE, 0,
IRQ_KIRKWOOD_GPIO_START, gpio0_irqs);
orion_gpio_init(NULL, 32, 18, (void __iomem *)GPIO_HIGH_VIRT_BASE, 0,
orion_gpio_init(NULL, 32, 18, GPIO_HIGH_VIRT_BASE, 0,
IRQ_KIRKWOOD_GPIO_START + 32, gpio1_irqs);
}

12
arch/arm/mach-kirkwood/pcie.c
View File

@ -47,8 +47,8 @@ void kirkwood_enable_pcie(void)
void kirkwood_pcie_id(u32 *dev, u32 *rev)
{
kirkwood_enable_pcie();
*dev = orion_pcie_dev_id((void __iomem *)PCIE_VIRT_BASE);
*rev = orion_pcie_rev((void __iomem *)PCIE_VIRT_BASE);
*dev = orion_pcie_dev_id(PCIE_VIRT_BASE);
*rev = orion_pcie_rev(PCIE_VIRT_BASE);
}
struct pcie_port {
@ -133,7 +133,7 @@ static struct pci_ops pcie_ops = {
static void __init pcie0_ioresources_init(struct pcie_port *pp)
{
pp->base = (void __iomem *)PCIE_VIRT_BASE;
pp->base = PCIE_VIRT_BASE;
pp->irq = IRQ_KIRKWOOD_PCIE;
/*
@ -147,7 +147,7 @@ static void __init pcie0_ioresources_init(struct pcie_port *pp)
static void __init pcie1_ioresources_init(struct pcie_port *pp)
{
pp->base = (void __iomem *)PCIE1_VIRT_BASE;
pp->base = PCIE1_VIRT_BASE;
pp->irq = IRQ_KIRKWOOD_PCIE1;
/*
@ -255,11 +255,11 @@ static struct hw_pci kirkwood_pci __initdata = {
.map_irq = kirkwood_pcie_map_irq,
};
static void __init add_pcie_port(int index, unsigned long base)
static void __init add_pcie_port(int index, void __iomem *base)
{
printk(KERN_INFO "Kirkwood PCIe port %d: ", index);
if (orion_pcie_link_up((void __iomem *)base)) {
if (orion_pcie_link_up(base)) {
printk(KERN_INFO "link up\n");
pcie_port_map[num_pcie_ports++] = index;
} else

3
arch/arm/mach-kirkwood/ts41x-setup.c
View File

@ -20,6 +20,7 @@
#include <linux/gpio.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <linux/io.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/kirkwood.h>
@ -161,7 +162,7 @@ static int __init ts41x_pci_init(void)
* (Marvell 88sx7042/sata_mv) is known to stop working
* after a few minutes.
*/
orion_pcie_reset((void __iomem *)PCIE_VIRT_BASE);
orion_pcie_reset(PCIE_VIRT_BASE);
kirkwood_pcie_id(&dev, &rev);
if (dev == MV88F6282_DEV_ID)

6
arch/arm/mach-mv78xx0/addr-map.c
View File

@ -48,7 +48,7 @@ static void __init __iomem *win_cfg_base(const struct orion_addr_map_cfg *cfg, i
* so we don't need to take that into account here.
*/
return (void __iomem *)((win < 8) ? WIN0_OFF(win) : WIN8_OFF(win));
return (win < 8) ? WIN0_OFF(win) : WIN8_OFF(win);
}
/*
@ -72,10 +72,10 @@ void __init mv78xx0_setup_cpu_mbus(void)
*/
if (mv78xx0_core_index() == 0)
orion_setup_cpu_mbus_target(&addr_map_cfg,
DDR_WINDOW_CPU0_BASE);
(void __iomem *) DDR_WINDOW_CPU0_BASE);
else
orion_setup_cpu_mbus_target(&addr_map_cfg,
DDR_WINDOW_CPU1_BASE);
(void __iomem *) DDR_WINDOW_CPU1_BASE);
}
void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,

4
arch/arm/mach-mv78xx0/common.c
View File

@ -130,12 +130,12 @@ static int get_tclk(void)
****************************************************************************/
static struct map_desc mv78xx0_io_desc[] __initdata = {
{
.virtual = MV78XX0_CORE_REGS_VIRT_BASE,
.virtual = (unsigned long) MV78XX0_CORE_REGS_VIRT_BASE,
.pfn = 0,
.length = MV78XX0_CORE_REGS_SIZE,
.type = MT_DEVICE,
}, {
.virtual = MV78XX0_REGS_VIRT_BASE,
.virtual = (unsigned long) MV78XX0_REGS_VIRT_BASE,
.pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE),
.length = MV78XX0_REGS_SIZE,
.type = MT_DEVICE,

12
arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
View File

@ -11,18 +11,18 @@
#include <mach/mv78xx0.h>
#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104)
#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104)
#define L2_WRITETHROUGH 0x00020000
#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
#define SOFT_RESET_OUT_EN 0x00000004
#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c)
#define SOFT_RESET 0x00000001
#define BRIDGE_INT_TIMER1_CLR (~0x0004)
#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200)
#define IRQ_CAUSE_ERR_OFF 0x0000
#define IRQ_CAUSE_LOW_OFF 0x0004
#define IRQ_CAUSE_HIGH_OFF 0x0008
@ -30,7 +30,7 @@
#define IRQ_MASK_LOW_OFF 0x0010
#define IRQ_MASK_HIGH_OFF 0x0014
#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE | 0x0300)
#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300)
#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300)
#endif

72
arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
View File

@ -41,7 +41,7 @@
*/
#define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000
#define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000
#define MV78XX0_CORE_REGS_VIRT_BASE 0xfe400000
#define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000)
#define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000
#define MV78XX0_CORE_REGS_SIZE SZ_16K
@ -49,7 +49,7 @@
#define MV78XX0_PCIE_IO_SIZE SZ_1M
#define MV78XX0_REGS_PHYS_BASE 0xf1000000
#define MV78XX0_REGS_VIRT_BASE 0xfd000000
#define MV78XX0_REGS_VIRT_BASE IOMEM(0xfd000000)
#define MV78XX0_REGS_SIZE SZ_1M
#define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000
@ -64,47 +64,47 @@
/*
* Register Map
*/
#define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x00000)
#define DDR_WINDOW_CPU0_BASE (DDR_VIRT_BASE | 0x1500)
#define DDR_WINDOW_CPU1_BASE (DDR_VIRT_BASE | 0x1570)
#define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x00000)
#define DDR_WINDOW_CPU0_BASE (DDR_VIRT_BASE + 0x1500)
#define DDR_WINDOW_CPU1_BASE (DDR_VIRT_BASE + 0x1570)
#define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x10000)
#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x10000)
#define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE | 0x0030)
#define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE | 0x0034)
#define GPIO_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x0100)
#define I2C_0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1000)
#define I2C_1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1100)
#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000)
#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000)
#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100)
#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100)
#define UART2_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2200)
#define UART2_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2200)
#define UART3_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2300)
#define UART3_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2300)
#define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x10000)
#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x10000)
#define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE + 0x0030)
#define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE + 0x0034)
#define GPIO_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x0100)
#define I2C_0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1000)
#define I2C_1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1100)
#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2000)
#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2000)
#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2100)
#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2100)
#define UART2_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2200)
#define UART2_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2200)
#define UART3_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2300)
#define UART3_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2300)
#define GE10_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x30000)
#define GE11_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x34000)
#define GE10_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x30000)
#define GE11_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x34000)
#define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x40000)
#define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x44000)
#define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x48000)
#define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x4c000)
#define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x40000)
#define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x44000)
#define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x48000)
#define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x4c000)
#define USB0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x50000)
#define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x51000)
#define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x52000)
#define USB0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x50000)
#define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x51000)
#define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x52000)
#define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x70000)
#define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x74000)
#define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x70000)
#define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x74000)
#define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x80000)
#define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x84000)
#define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x88000)
#define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x8c000)
#define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x80000)
#define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x84000)
#define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x88000)
#define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x8c000)
#define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0xa0000)
#define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0xa0000)
/*
* Supported devices and revisions.

9
arch/arm/mach-mv78xx0/irq.c
View File

@ -10,6 +10,7 @@
#include <linux/gpio.h>
#include <linux/kernel.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <mach/bridge-regs.h>
#include <plat/orion-gpio.h>
#include <plat/irq.h>
@ -24,16 +25,16 @@ static int __initdata gpio0_irqs[4] = {
void __init mv78xx0_init_irq(void)
{
orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
orion_irq_init(64, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF));
orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
orion_irq_init(64, IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF);
/*
* Initialize gpiolib for GPIOs 0-31. (The GPIO interrupt mask
* registers for core #1 are at an offset of 0x18 from those of
* core #0.)
*/
orion_gpio_init(NULL, 0, 32, (void __iomem *)GPIO_VIRT_BASE,
orion_gpio_init(NULL, 0, 32, GPIO_VIRT_BASE,
mv78xx0_core_index() ? 0x18 : 0,
IRQ_MV78XX0_GPIO_START, gpio0_irqs);
}

12
arch/arm/mach-mv78xx0/pcie.c
View File

@ -34,8 +34,8 @@ static struct resource pcie_io_space;
void __init mv78xx0_pcie_id(u32 *dev, u32 *rev)
{
*dev = orion_pcie_dev_id((void __iomem *)PCIE00_VIRT_BASE);
*rev = orion_pcie_rev((void __iomem *)PCIE00_VIRT_BASE);
*dev = orion_pcie_dev_id(PCIE00_VIRT_BASE);
*rev = orion_pcie_rev(PCIE00_VIRT_BASE);
}
u32 pcie_port_size[8] = {
@ -223,11 +223,11 @@ static struct hw_pci mv78xx0_pci __initdata = {
.map_irq = mv78xx0_pcie_map_irq,
};
static void __init add_pcie_port(int maj, int min, unsigned long base)
static void __init add_pcie_port(int maj, int min, void __iomem *base)
{
printk(KERN_INFO "MV78xx0 PCIe port %d.%d: ", maj, min);
if (orion_pcie_link_up((void __iomem *)base)) {
if (orion_pcie_link_up(base)) {
struct pcie_port *pp = &pcie_port[num_pcie_ports++];
printk("link up\n");
@ -235,7 +235,7 @@ static void __init add_pcie_port(int maj, int min, unsigned long base)
pp->maj = maj;
pp->min = min;
pp->root_bus_nr = -1;
pp->base = (void __iomem *)base;
pp->base = base;
spin_lock_init(&pp->conf_lock);
memset(&pp->res, 0, sizeof(pp->res));
} else {
@ -249,7 +249,7 @@ void __init mv78xx0_pcie_init(int init_port0, int init_port1)
if (init_port0) {
add_pcie_port(0, 0, PCIE00_VIRT_BASE);
if (!orion_pcie_x4_mode((void __iomem *)PCIE00_VIRT_BASE)) {
if (!orion_pcie_x4_mode(PCIE00_VIRT_BASE)) {
add_pcie_port(0, 1, PCIE01_VIRT_BASE);
add_pcie_port(0, 2, PCIE02_VIRT_BASE);
add_pcie_port(0, 3, PCIE03_VIRT_BASE);

22
arch/arm/mach-mvebu/Kconfig
View File

@ -6,6 +6,8 @@ config ARCH_MVEBU
select GENERIC_IRQ_CHIP
select IRQ_DOMAIN
select MULTI_IRQ_HANDLER
select PINCTRL
select PLAT_ORION
select SPARSE_IRQ
if ARCH_MVEBU
@ -13,13 +15,25 @@ if ARCH_MVEBU
menu "Marvell SOC with device tree"
config MACH_ARMADA_370_XP
bool "Marvell Armada 370 and Aramada XP boards"
bool
select ARMADA_370_XP_TIMER
select CPU_V7
help
Say 'Y' here if you want your kernel to support boards based on
Marvell Armada 370 or Armada XP with device tree.
config MACH_ARMADA_370
bool "Marvell Armada 370 boards"
select MACH_ARMADA_370_XP
select PINCTRL_ARMADA_370
help
Say 'Y' here if you want your kernel to support boards based
on the Marvell Armada 370 SoC with device tree.
config MACH_ARMADA_XP
bool "Marvell Armada XP boards"
select MACH_ARMADA_370_XP
select PINCTRL_ARMADA_XP
help
Say 'Y' here if you want your kernel to support boards based
on the Marvell Armada XP SoC with device tree.
endmenu

5
arch/arm/mach-mvebu/Makefile
View File

@ -1,4 +1,5 @@
ccflags-$(ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
-I$(srctree)/arch/arm/plat-orion/include
obj-y += system-controller.o
obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o
obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o addr-map.o

134
arch/arm/mach-mvebu/addr-map.c 100644
View File

@ -0,0 +1,134 @@
/*
* Address map functions for Marvell 370 / XP SoCs
*
* Copyright (C) 2012 Marvell
*
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/mbus.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <plat/addr-map.h>
/*
* Generic Address Decode Windows bit settings
*/
#define ARMADA_XP_TARGET_DEV_BUS 1
#define ARMADA_XP_ATTR_DEV_BOOTROM 0x1D
#define ARMADA_XP_TARGET_ETH1 3
#define ARMADA_XP_TARGET_PCIE_0_2 4
#define ARMADA_XP_TARGET_ETH0 7
#define ARMADA_XP_TARGET_PCIE_1_3 8
#define ARMADA_370_TARGET_DEV_BUS 1
#define ARMADA_370_ATTR_DEV_BOOTROM 0x1D
#define ARMADA_370_TARGET_PCIE_0 4
#define ARMADA_370_TARGET_PCIE_1 8
#define ARMADA_WINDOW_8_PLUS_OFFSET 0x90
#define ARMADA_SDRAM_ADDR_DECODING_OFFSET 0x180
static const struct __initdata orion_addr_map_info
armada_xp_addr_map_info[] = {
/*
* Window for the BootROM, needed for SMP on Armada XP
*/
{ 0, 0xfff00000, SZ_1M, ARMADA_XP_TARGET_DEV_BUS,
ARMADA_XP_ATTR_DEV_BOOTROM, -1 },
/* End marker */
{ -1, 0, 0, 0, 0, 0 },
};
static const struct __initdata orion_addr_map_info
armada_370_addr_map_info[] = {
/* End marker */
{ -1, 0, 0, 0, 0, 0 },
};
static struct of_device_id of_addr_decoding_controller_table[] = {
{ .compatible = "marvell,armada-addr-decoding-controller" },
{ /* end of list */ },
};
static void __iomem *
armada_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
{
unsigned int offset;
/* The register layout is a bit annoying and the below code
* tries to cope with it.
* - At offset 0x0, there are the registers for the first 8
* windows, with 4 registers of 32 bits per window (ctrl,
* base, remap low, remap high)
* - Then at offset 0x80, there is a hole of 0x10 bytes for
* the internal registers base address and internal units
* sync barrier register.
* - Then at offset 0x90, there the registers for 12
* windows, with only 2 registers of 32 bits per window
* (ctrl, base).
*/
if (win < 8)
offset = (win << 4);
else
offset = ARMADA_WINDOW_8_PLUS_OFFSET + (win << 3);
return cfg->bridge_virt_base + offset;
}
static struct __initdata orion_addr_map_cfg addr_map_cfg = {
.num_wins = 20,
.remappable_wins = 8,
.win_cfg_base = armada_cfg_base,
};
static int __init armada_setup_cpu_mbus(void)
{
struct device_node *np;
void __iomem *mbus_unit_addr_decoding_base;
void __iomem *sdram_addr_decoding_base;
np = of_find_matching_node(NULL, of_addr_decoding_controller_table);
if (!np)
return -ENODEV;
mbus_unit_addr_decoding_base = of_iomap(np, 0);
BUG_ON(!mbus_unit_addr_decoding_base);
sdram_addr_decoding_base =
mbus_unit_addr_decoding_base +
ARMADA_SDRAM_ADDR_DECODING_OFFSET;
addr_map_cfg.bridge_virt_base = mbus_unit_addr_decoding_base;
/*
* Disable, clear and configure windows.
*/
if (of_machine_is_compatible("marvell,armadaxp"))
orion_config_wins(&addr_map_cfg, armada_xp_addr_map_info);
else if (of_machine_is_compatible("marvell,armada370"))
orion_config_wins(&addr_map_cfg, armada_370_addr_map_info);
else {
pr_err("Unsupported SoC\n");
return -EINVAL;
}
/*
* Setup MBUS dram target info.
*/
orion_setup_cpu_mbus_target(&addr_map_cfg,
sdram_addr_decoding_base);
return 0;
}
/* Using a early_initcall is needed so that this initialization gets
* done before the SMP initialization, which requires the BootROM to
* be remapped. */
early_initcall(armada_setup_cpu_mbus);

2
arch/arm/mach-mvebu/armada-370-xp.c
View File

@ -25,7 +25,7 @@
static struct map_desc armada_370_xp_io_desc[] __initdata = {
{
.virtual = ARMADA_370_XP_REGS_VIRT_BASE,
.virtual = (unsigned long) ARMADA_370_XP_REGS_VIRT_BASE,
.pfn = __phys_to_pfn(ARMADA_370_XP_REGS_PHYS_BASE),
.length = ARMADA_370_XP_REGS_SIZE,
.type = MT_DEVICE,

2
arch/arm/mach-mvebu/armada-370-xp.h
View File

@ -16,7 +16,7 @@
#define __MACH_ARMADA_370_XP_H
#define ARMADA_370_XP_REGS_PHYS_BASE 0xd0000000
#define ARMADA_370_XP_REGS_VIRT_BASE 0xfeb00000
#define ARMADA_370_XP_REGS_VIRT_BASE IOMEM(0xfeb00000)
#define ARMADA_370_XP_REGS_SIZE SZ_1M
#endif /* __MACH_ARMADA_370_XP_H */

1
arch/arm/mach-mvebu/include/mach/gpio.h 100644
View File

@ -0,0 +1 @@
/* empty */

28
arch/arm/mach-omap1/devices.c
View File

@ -357,6 +357,33 @@ static inline void omap_init_uwire(void) {}
#endif
#define OMAP1_RNG_BASE 0xfffe5000
static struct resource omap1_rng_resources[] = {
{
.start = OMAP1_RNG_BASE,
.end = OMAP1_RNG_BASE + 0x4f,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device omap1_rng_device = {
.name = "omap_rng",
.id = -1,
.num_resources = ARRAY_SIZE(omap1_rng_resources),
.resource = omap1_rng_resources,
};
static void omap1_init_rng(void)
{
if (!cpu_is_omap16xx())
return;
(void) platform_device_register(&omap1_rng_device);
}
/*-------------------------------------------------------------------------*/
/*
* This gets called after board-specific INIT_MACHINE, and initializes most
* on-chip peripherals accessible on this board (except for few like USB):
@ -395,6 +422,7 @@ static int __init omap1_init_devices(void)
omap_init_spi100k();
omap_init_sti();
omap_init_uwire();
omap1_init_rng();
return 0;
}

2
arch/arm/mach-omap1/timer.c
View File

@ -141,7 +141,7 @@ static int __init omap1_dm_timer_init(void)
pdata->set_timer_src = omap1_dm_timer_set_src;
pdata->timer_capability = OMAP_TIMER_ALWON |
OMAP_TIMER_NEEDS_RESET;
OMAP_TIMER_NEEDS_RESET | OMAP_TIMER_HAS_DSP_IRQ;
ret = platform_device_add_data(pdev, pdata, sizeof(*pdata));
if (ret) {

1
arch/arm/mach-omap2/Makefile
View File

@ -179,6 +179,7 @@ obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
# EMU peripherals
obj-$(CONFIG_OMAP3_EMU) += emu.o
obj-$(CONFIG_HW_PERF_EVENTS) += pmu.o
obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o
mailbox_mach-objs := mailbox.o

4
arch/arm/mach-omap2/board-apollon.c
View File

@ -202,7 +202,7 @@ static inline void __init apollon_init_smc91x(void)
return;
}
clk_enable(gpmc_fck);
clk_prepare_enable(gpmc_fck);
rate = clk_get_rate(gpmc_fck);
eth_cs = APOLLON_ETH_CS;
@ -246,7 +246,7 @@ static inline void __init apollon_init_smc91x(void)
gpmc_cs_free(APOLLON_ETH_CS);
}
out:
clk_disable(gpmc_fck);
clk_disable_unprepare(gpmc_fck);
clk_put(gpmc_fck);
}

6
arch/arm/mach-omap2/board-h4.c
View File

@ -265,9 +265,9 @@ static inline void __init h4_init_debug(void)
return;
}
clk_enable(gpmc_fck);
clk_prepare_enable(gpmc_fck);
rate = clk_get_rate(gpmc_fck);
clk_disable(gpmc_fck);
clk_disable_unprepare(gpmc_fck);
clk_put(gpmc_fck);
if (is_gpmc_muxed())
@ -311,7 +311,7 @@ static inline void __init h4_init_debug(void)
gpmc_cs_free(eth_cs);
out:
clk_disable(gpmc_fck);
clk_disable_unprepare(gpmc_fck);
clk_put(gpmc_fck);
}

2
arch/arm/mach-omap2/board-omap4panda.c
View File

@ -171,7 +171,7 @@ static void __init omap4_ehci_init(void)
return;
}
clk_set_rate(phy_ref_clk, 19200000);
clk_enable(phy_ref_clk);
clk_prepare_enable(phy_ref_clk);
/* disable the power to the usb hub prior to init and reset phy+hub */
ret = gpio_request_array(panda_ehci_gpios,

2
arch/arm/mach-omap2/clkt2xxx_apll.c
View File

@ -59,7 +59,7 @@ static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)
omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
omap2_cm_wait_idlest(cm_idlest_pll, status_mask,
OMAP24XX_CM_IDLEST_VAL, clk->name);
OMAP24XX_CM_IDLEST_VAL, __clk_get_name(clk));
/*
* REVISIT: Should we return an error code if omap2_wait_clock_ready()

10
arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
View File

@ -68,14 +68,15 @@ unsigned long omap2_table_mpu_recalc(struct clk *clk)
long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
{
const struct prcm_config *ptr;
long highest_rate;
long highest_rate, sys_clk_rate;
highest_rate = -EINVAL;
sys_clk_rate = __clk_get_rate(sclk);
for (ptr = rate_table; ptr->mpu_speed; ptr++) {
if (!(ptr->flags & cpu_mask))
continue;
if (ptr->xtal_speed != sclk->rate)
if (ptr->xtal_speed != sys_clk_rate)
continue;
highest_rate = ptr->mpu_speed;
@ -94,12 +95,15 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate)
const struct prcm_config *prcm;
unsigned long found_speed = 0;
unsigned long flags;
long sys_clk_rate;
sys_clk_rate = __clk_get_rate(sclk);
for (prcm = rate_table; prcm->mpu_speed; prcm++) {
if (!(prcm->flags & cpu_mask))
continue;
if (prcm->xtal_speed != sclk->rate)
if (prcm->xtal_speed != sys_clk_rate)
continue;
if (prcm->mpu_speed <= rate) {

20
arch/arm/mach-omap2/clkt34xx_dpll3m2.c
View File

@ -56,6 +56,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
struct omap_sdrc_params *sdrc_cs0;
struct omap_sdrc_params *sdrc_cs1;
int ret;
unsigned long clkrate;
if (!clk || !rate)
return -EINVAL;
@ -64,11 +65,12 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
if (validrate != rate)
return -EINVAL;
sdrcrate = sdrc_ick_p->rate;
if (rate > clk->rate)
sdrcrate <<= ((rate / clk->rate) >> 1);
sdrcrate = __clk_get_rate(sdrc_ick_p);
clkrate = __clk_get_rate(clk);
if (rate > clkrate)
sdrcrate <<= ((rate / clkrate) >> 1);
else
sdrcrate >>= ((clk->rate / rate) >> 1);
sdrcrate >>= ((clkrate / rate) >> 1);
ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
if (ret)
@ -82,7 +84,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
/*
* XXX This only needs to be done when the CPU frequency changes
*/
_mpurate = arm_fck_p->rate / CYCLES_PER_MHZ;
_mpurate = __clk_get_rate(arm_fck_p) / CYCLES_PER_MHZ;
c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
c += 1; /* for safety */
c *= SDRC_MPURATE_LOOPS;
@ -90,8 +92,8 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
if (c == 0)
c = 1;
pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
validrate);
pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n",
clkrate, validrate);
pr_debug("clock: SDRC CS0 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
@ -102,14 +104,14 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
if (sdrc_cs1)
omap3_configure_core_dpll(
new_div, unlock_dll, c, rate > clk->rate,
new_div, unlock_dll, c, rate > clkrate,
sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
else
omap3_configure_core_dpll(
new_div, unlock_dll, c, rate > clk->rate,
new_div, unlock_dll, c, rate > clkrate,
sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
0, 0, 0, 0);

86
arch/arm/mach-omap2/clkt_clksel.c
View File

@ -72,7 +72,7 @@ static const struct clksel *_get_clksel_by_parent(struct clk *clk,
if (!clks->parent) {
/* This indicates a data problem */
WARN(1, "clock: %s: could not find parent clock %s in clksel array\n",
clk->name, src_clk->name);
__clk_get_name(clk), __clk_get_name(src_clk));
return NULL;
}
@ -127,7 +127,8 @@ static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk,
if (max_div == 0) {
/* This indicates an error in the clksel data */
WARN(1, "clock: %s: could not find divisor for parent %s\n",
clk->name, src_clk->parent->name);
__clk_get_name(clk),
__clk_get_name(__clk_get_parent(src_clk)));
return 0;
}
@ -176,8 +177,10 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
{
const struct clksel *clks;
const struct clksel_rate *clkr;
struct clk *parent;
clks = _get_clksel_by_parent(clk, clk->parent);
parent = __clk_get_parent(clk);
clks = _get_clksel_by_parent(clk, parent);
if (!clks)
return 0;
@ -191,8 +194,8 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
if (!clkr->div) {
/* This indicates a data error */
WARN(1, "clock: %s: could not find fieldval %d parent %s\n",
clk->name, field_val, clk->parent->name);
WARN(1, "clock: %s: could not find fieldval %d for parent %s\n",
__clk_get_name(clk), field_val, __clk_get_name(parent));
return 0;
}
@ -213,11 +216,13 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
{
const struct clksel *clks;
const struct clksel_rate *clkr;
struct clk *parent;
/* should never happen */
WARN_ON(div == 0);
clks = _get_clksel_by_parent(clk, clk->parent);
parent = __clk_get_parent(clk);
clks = _get_clksel_by_parent(clk, parent);
if (!clks)
return ~0;
@ -230,8 +235,8 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
}
if (!clkr->div) {
pr_err("clock: %s: could not find divisor %d parent %s\n",
clk->name, div, clk->parent->name);
pr_err("clock: %s: could not find divisor %d for parent %s\n",
__clk_get_name(clk), div, __clk_get_name(parent));
return ~0;
}
@ -281,16 +286,23 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
const struct clksel *clks;
const struct clksel_rate *clkr;
u32 last_div = 0;
struct clk *parent;
unsigned long parent_rate;
const char *clk_name;
parent = __clk_get_parent(clk);
parent_rate = __clk_get_rate(parent);
clk_name = __clk_get_name(clk);
if (!clk->clksel || !clk->clksel_mask)
return ~0;
pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n",
clk->name, target_rate);
clk_name, target_rate);
*new_div = 1;
clks = _get_clksel_by_parent(clk, clk->parent);
clks = _get_clksel_by_parent(clk, parent);
if (!clks)
return ~0;
@ -300,29 +312,29 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
/* Sanity check */
if (clkr->div <= last_div)
pr_err("clock: %s: clksel_rate table not sorted",
clk->name);
pr_err("clock: %s: clksel_rate table not sorted\n",
clk_name);
last_div = clkr->div;
test_rate = clk->parent->rate / clkr->div;
test_rate = parent_rate / clkr->div;
if (test_rate <= target_rate)
break; /* found it */
}
if (!clkr->div) {
pr_err("clock: %s: could not find divisor for target rate %ld parent %s\n",
clk->name, target_rate, clk->parent->name);
pr_err("clock: %s: could not find divisor for target rate %ld for parent %s\n",
clk_name, target_rate, __clk_get_name(parent));
return ~0;
}
*new_div = clkr->div;
pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div,
(clk->parent->rate / clkr->div));
(parent_rate / clkr->div));
return clk->parent->rate / clkr->div;
return parent_rate / clkr->div;
}
/*
@ -344,10 +356,15 @@ void omap2_init_clksel_parent(struct clk *clk)
const struct clksel *clks;
const struct clksel_rate *clkr;
u32 r, found = 0;
struct clk *parent;
const char *clk_name;
if (!clk->clksel || !clk->clksel_mask)
return;
parent = __clk_get_parent(clk);
clk_name = __clk_get_name(clk);
r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
r >>= __ffs(clk->clksel_mask);
@ -357,11 +374,13 @@ void omap2_init_clksel_parent(struct clk *clk)
continue;
if (clkr->val == r) {
if (clk->parent != clks->parent) {
if (parent != clks->parent) {
pr_debug("clock: %s: inited parent to %s (was %s)\n",
clk->name, clks->parent->name,
((clk->parent) ?
clk->parent->name : "NULL"));
clk_name,
__clk_get_name(clks->parent),
((parent) ?
__clk_get_name(parent) :
"NULL"));
clk_reparent(clk, clks->parent);
};
found = 1;
@ -371,7 +390,7 @@ void omap2_init_clksel_parent(struct clk *clk)
/* This indicates a data error */
WARN(!found, "clock: %s: init parent: could not find regval %0x\n",
clk->name, r);
clk_name, r);
return;
}
@ -389,15 +408,17 @@ unsigned long omap2_clksel_recalc(struct clk *clk)
{
unsigned long rate;
u32 div = 0;
struct clk *parent;
div = _read_divisor(clk);
if (div == 0)
return clk->rate;
return __clk_get_rate(clk);
rate = clk->parent->rate / div;
parent = __clk_get_parent(clk);
rate = __clk_get_rate(parent) / div;
pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n", clk->name,
rate, div);
pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n",
__clk_get_name(clk), rate, div);
return rate;
}
@ -452,9 +473,10 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
_write_clksel_reg(clk, field_val);
clk->rate = clk->parent->rate / new_div;
clk->rate = __clk_get_rate(__clk_get_parent(clk)) / new_div;
pr_debug("clock: %s: set rate to %ld\n", clk->name, clk->rate);
pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(clk),
__clk_get_rate(clk));
return 0;
}
@ -496,13 +518,15 @@ int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent)
clk_reparent(clk, new_parent);
/* CLKSEL clocks follow their parents' rates, divided by a divisor */
clk->rate = new_parent->rate;
clk->rate = __clk_get_rate(new_parent);
if (parent_div > 0)
clk->rate /= parent_div;
__clk_get_rate(clk) /= parent_div;
pr_debug("clock: %s: set parent to %s (new rate %ld)\n",
clk->name, clk->parent->name, clk->rate);
__clk_get_name(clk),
__clk_get_name(__clk_get_parent(clk)),
__clk_get_rate(clk));
return 0;
}

26
arch/arm/mach-omap2/clkt_dpll.c
View File

@ -87,7 +87,7 @@ static int _dpll_test_fint(struct clk *clk, u8 n)
dd = clk->dpll_data;
/* DPLL divider must result in a valid jitter correction val */
fint = clk->parent->rate / n;
fint = __clk_get_rate(__clk_get_parent(clk)) / n;
if (cpu_is_omap24xx()) {
/* Should not be called for OMAP2, so warn if it is called */
@ -252,16 +252,16 @@ u32 omap2_get_dpll_rate(struct clk *clk)
if (cpu_is_omap24xx()) {
if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
v == OMAP2XXX_EN_DPLL_FRBYPASS)
return dd->clk_bypass->rate;
return __clk_get_rate(dd->clk_bypass);
} else if (cpu_is_omap34xx()) {
if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
v == OMAP3XXX_EN_DPLL_FRBYPASS)
return dd->clk_bypass->rate;
return __clk_get_rate(dd->clk_bypass);
} else if (soc_is_am33xx() || cpu_is_omap44xx()) {
if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
v == OMAP4XXX_EN_DPLL_FRBYPASS ||
v == OMAP4XXX_EN_DPLL_MNBYPASS)
return dd->clk_bypass->rate;
return __clk_get_rate(dd->clk_bypass);
}
v = __raw_readl(dd->mult_div1_reg);
@ -270,7 +270,7 @@ u32 omap2_get_dpll_rate(struct clk *clk)
dpll_div = v & dd->div1_mask;
dpll_div >>= __ffs(dd->div1_mask);
dpll_clk = (long long)dd->clk_ref->rate * dpll_mult;
dpll_clk = (long long) __clk_get_rate(dd->clk_ref) * dpll_mult;
do_div(dpll_clk, dpll_div + 1);
return dpll_clk;
@ -296,16 +296,20 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
unsigned long scaled_rt_rp;
unsigned long new_rate = 0;
struct dpll_data *dd;
unsigned long ref_rate;
const char *clk_name;
if (!clk || !clk->dpll_data)
return ~0;
dd = clk->dpll_data;
ref_rate = __clk_get_rate(dd->clk_ref);
clk_name = __clk_get_name(clk);
pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n",
clk->name, target_rate);
clk_name, target_rate);
scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR);
scaled_rt_rp = target_rate / (ref_rate / DPLL_SCALE_FACTOR);
scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
dd->last_rounded_rate = 0;
@ -332,14 +336,14 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
break;
r = _dpll_test_mult(&m, n, &new_rate, target_rate,
dd->clk_ref->rate);
ref_rate);
/* m can't be set low enough for this n - try with a larger n */
if (r == DPLL_MULT_UNDERFLOW)
continue;
pr_debug("clock: %s: m = %d: n = %d: new_rate = %ld\n",
clk->name, m, n, new_rate);
clk_name, m, n, new_rate);
if (target_rate == new_rate) {
dd->last_rounded_m = m;
@ -350,8 +354,8 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
}
if (target_rate != new_rate) {
pr_debug("clock: %s: cannot round to rate %ld\n", clk->name,
target_rate);
pr_debug("clock: %s: cannot round to rate %ld\n",
clk_name, target_rate);
return ~0;
}

9
arch/arm/mach-omap2/clock.c
View File

@ -78,7 +78,7 @@ static void _omap2_module_wait_ready(struct clk *clk)
clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val);
omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), idlest_val,
clk->name);
__clk_get_name(clk));
}
/* Public functions */
@ -94,18 +94,21 @@ static void _omap2_module_wait_ready(struct clk *clk)
void omap2_init_clk_clkdm(struct clk *clk)
{
struct clockdomain *clkdm;
const char *clk_name;
if (!clk->clkdm_name)
return;
clk_name = __clk_get_name(clk);
clkdm = clkdm_lookup(clk->clkdm_name);
if (clkdm) {
pr_debug("clock: associated clk %s to clkdm %s\n",
clk->name, clk->clkdm_name);
clk_name, clk->clkdm_name);
clk->clkdm = clkdm;
} else {
pr_debug("clock: could not associate clk %s to clkdm %s\n",
clk->name, clk->clkdm_name);
clk_name, clk->clkdm_name);
}
}

24
arch/arm/mach-omap2/clock2420_data.c
View File

@ -1804,6 +1804,7 @@ static struct omap_clk omap2420_clks[] = {
CLK(NULL, "gfx_ick", &gfx_ick, CK_242X),
/* DSS domain clocks */
CLK("omapdss_dss", "ick", &dss_ick, CK_242X),
CLK(NULL, "dss_ick", &dss_ick, CK_242X),
CLK(NULL, "dss1_fck", &dss1_fck, CK_242X),
CLK(NULL, "dss2_fck", &dss2_fck, CK_242X),
CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_242X),
@ -1843,12 +1844,16 @@ static struct omap_clk omap2420_clks[] = {
CLK(NULL, "gpt12_ick", &gpt12_ick, CK_242X),
CLK(NULL, "gpt12_fck", &gpt12_fck, CK_242X),
CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_242X),
CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_242X),
CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_242X),
CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_242X),
CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_242X),
CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_242X),
CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_242X),
CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_242X),
CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_242X),
CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_242X),
CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_242X),
CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_242X),
CLK(NULL, "uart1_ick", &uart1_ick, CK_242X),
CLK(NULL, "uart1_fck", &uart1_fck, CK_242X),
@ -1859,12 +1864,15 @@ static struct omap_clk omap2420_clks[] = {
CLK(NULL, "gpios_ick", &gpios_ick, CK_242X),
CLK(NULL, "gpios_fck", &gpios_fck, CK_242X),
CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_242X),
CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_242X),
CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_242X),
CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_242X),
CLK(NULL, "wdt1_ick", &wdt1_ick, CK_242X),
CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_242X),
CLK("omap24xxcam", "fck", &cam_fck, CK_242X),
CLK(NULL, "cam_fck", &cam_fck, CK_242X),
CLK("omap24xxcam", "ick", &cam_ick, CK_242X),
CLK(NULL, "cam_ick", &cam_ick, CK_242X),
CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_242X),
CLK(NULL, "wdt4_ick", &wdt4_ick, CK_242X),
CLK(NULL, "wdt4_fck", &wdt4_fck, CK_242X),
@ -1873,16 +1881,22 @@ static struct omap_clk omap2420_clks[] = {
CLK(NULL, "mspro_ick", &mspro_ick, CK_242X),
CLK(NULL, "mspro_fck", &mspro_fck, CK_242X),
CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X),
CLK(NULL, "mmc_ick", &mmc_ick, CK_242X),
CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X),
CLK(NULL, "mmc_fck", &mmc_fck, CK_242X),
CLK(NULL, "fac_ick", &fac_ick, CK_242X),
CLK(NULL, "fac_fck", &fac_fck, CK_242X),
CLK(NULL, "eac_ick", &eac_ick, CK_242X),
CLK(NULL, "eac_fck", &eac_fck, CK_242X),
CLK("omap_hdq.0", "ick", &hdq_ick, CK_242X),
CLK(NULL, "hdq_ick", &hdq_ick, CK_242X),
CLK("omap_hdq.0", "fck", &hdq_fck, CK_242X),
CLK(NULL, "hdq_fck", &hdq_fck, CK_242X),
CLK("omap_i2c.1", "ick", &i2c1_ick, CK_242X),
CLK(NULL, "i2c1_ick", &i2c1_ick, CK_242X),
CLK(NULL, "i2c1_fck", &i2c1_fck, CK_242X),
CLK("omap_i2c.2", "ick", &i2c2_ick, CK_242X),
CLK(NULL, "i2c2_ick", &i2c2_ick, CK_242X),
CLK(NULL, "i2c2_fck", &i2c2_fck, CK_242X),
CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X),
CLK(NULL, "sdma_fck", &sdma_fck, CK_242X),
@ -1892,14 +1906,18 @@ static struct omap_clk omap2420_clks[] = {
CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X),
CLK(NULL, "des_ick", &des_ick, CK_242X),
CLK("omap-sham", "ick", &sha_ick, CK_242X),
CLK(NULL, "sha_ick", &sha_ick, CK_242X),
CLK("omap_rng", "ick", &rng_ick, CK_242X),
CLK(NULL, "rng_ick", &rng_ick, CK_242X),
CLK("omap-aes", "ick", &aes_ick, CK_242X),
CLK(NULL, "aes_ick", &aes_ick, CK_242X),
CLK(NULL, "pka_ick", &pka_ick, CK_242X),
CLK(NULL, "usb_fck", &usb_fck, CK_242X),
CLK("musb-hdrc", "fck", &osc_ck, CK_242X),
CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_243X),
CLK(NULL, "timer_sys_ck", &sys_ck, CK_243X),
CLK(NULL, "timer_ext_ck", &alt_ck, CK_243X),
CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_242X),
CLK(NULL, "timer_sys_ck", &sys_ck, CK_242X),
CLK(NULL, "timer_ext_ck", &alt_ck, CK_242X),
CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_242X),
};
/*

23
arch/arm/mach-omap2/clock2430_data.c
View File

@ -1888,6 +1888,7 @@ static struct omap_clk omap2430_clks[] = {
CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X),
/* DSS domain clocks */
CLK("omapdss_dss", "ick", &dss_ick, CK_243X),
CLK(NULL, "dss_ick", &dss_ick, CK_243X),
CLK(NULL, "dss1_fck", &dss1_fck, CK_243X),
CLK(NULL, "dss2_fck", &dss2_fck, CK_243X),
CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X),
@ -1927,20 +1928,28 @@ static struct omap_clk omap2430_clks[] = {
CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X),
CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X),
CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X),
CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_243X),
CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_243X),
CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X),
CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_243X),
CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_243X),
CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X),
CLK(NULL, "mcbsp3_ick", &mcbsp3_ick, CK_243X),
CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_243X),
CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X),
CLK(NULL, "mcbsp4_ick", &mcbsp4_ick, CK_243X),
CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_243X),
CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X),
CLK(NULL, "mcbsp5_ick", &mcbsp5_ick, CK_243X),
CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_243X),
CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X),
CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_243X),
CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_243X),
CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X),
CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_243X),
CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_243X),
CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X),
CLK(NULL, "mcspi3_ick", &mcspi3_ick, CK_243X),
CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_243X),
CLK(NULL, "uart1_ick", &uart1_ick, CK_243X),
CLK(NULL, "uart1_fck", &uart1_fck, CK_243X),
@ -1951,13 +1960,16 @@ static struct omap_clk omap2430_clks[] = {
CLK(NULL, "gpios_ick", &gpios_ick, CK_243X),
CLK(NULL, "gpios_fck", &gpios_fck, CK_243X),
CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X),
CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_243X),
CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_243X),
CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X),
CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X),
CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X),
CLK(NULL, "icr_ick", &icr_ick, CK_243X),
CLK("omap24xxcam", "fck", &cam_fck, CK_243X),
CLK(NULL, "cam_fck", &cam_fck, CK_243X),
CLK("omap24xxcam", "ick", &cam_ick, CK_243X),
CLK(NULL, "cam_ick", &cam_ick, CK_243X),
CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X),
CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X),
CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X),
@ -1966,10 +1978,14 @@ static struct omap_clk omap2430_clks[] = {
CLK(NULL, "fac_ick", &fac_ick, CK_243X),
CLK(NULL, "fac_fck", &fac_fck, CK_243X),
CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X),
CLK(NULL, "hdq_ick", &hdq_ick, CK_243X),
CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X),
CLK(NULL, "hdq_fck", &hdq_fck, CK_243X),
CLK("omap_i2c.1", "ick", &i2c1_ick, CK_243X),
CLK(NULL, "i2c1_ick", &i2c1_ick, CK_243X),
CLK(NULL, "i2chs1_fck", &i2chs1_fck, CK_243X),
CLK("omap_i2c.2", "ick", &i2c2_ick, CK_243X),
CLK(NULL, "i2c2_ick", &i2c2_ick, CK_243X),
CLK(NULL, "i2chs2_fck", &i2chs2_fck, CK_243X),
CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X),
CLK(NULL, "sdma_fck", &sdma_fck, CK_243X),
@ -1978,22 +1994,29 @@ static struct omap_clk omap2430_clks[] = {
CLK(NULL, "des_ick", &des_ick, CK_243X),
CLK("omap-sham", "ick", &sha_ick, CK_243X),
CLK("omap_rng", "ick", &rng_ick, CK_243X),
CLK(NULL, "rng_ick", &rng_ick, CK_243X),
CLK("omap-aes", "ick", &aes_ick, CK_243X),
CLK(NULL, "pka_ick", &pka_ick, CK_243X),
CLK(NULL, "usb_fck", &usb_fck, CK_243X),
CLK("musb-omap2430", "ick", &usbhs_ick, CK_243X),
CLK(NULL, "usbhs_ick", &usbhs_ick, CK_243X),
CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_243X),
CLK(NULL, "mmchs1_ick", &mmchs1_ick, CK_243X),
CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_243X),
CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_243X),
CLK(NULL, "mmchs2_ick", &mmchs2_ick, CK_243X),
CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_243X),
CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X),
CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X),
CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X),
CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X),
CLK(NULL, "mmchsdb1_fck", &mmchsdb1_fck, CK_243X),
CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X),
CLK(NULL, "mmchsdb2_fck", &mmchsdb2_fck, CK_243X),
CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_243X),
CLK(NULL, "timer_sys_ck", &sys_ck, CK_243X),
CLK(NULL, "timer_ext_ck", &alt_ck, CK_243X),
CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_243X),
};
/*

1
arch/arm/mach-omap2/clock33xx_data.c
View File

@ -1013,6 +1013,7 @@ static struct omap_clk am33xx_clks[] = {
CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck, CK_AM33XX),
CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck, CK_AM33XX),
CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_AM33XX),
CLK("cpu0", NULL, &dpll_mpu_ck, CK_AM33XX),
CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_AM33XX),
CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck, CK_AM33XX),
CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck, CK_AM33XX),

8
arch/arm/mach-omap2/clock3xxx.c
View File

@ -63,15 +63,15 @@ void __init omap3_clk_lock_dpll5(void)
dpll5_clk = clk_get(NULL, "dpll5_ck");
clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
clk_enable(dpll5_clk);
clk_prepare_enable(dpll5_clk);
/* Program dpll5_m2_clk divider for no division */
dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
clk_enable(dpll5_m2_clk);
clk_prepare_enable(dpll5_m2_clk);
clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST);
clk_disable(dpll5_m2_clk);
clk_disable(dpll5_clk);
clk_disable_unprepare(dpll5_m2_clk);
clk_disable_unprepare(dpll5_clk);
return;
}

37
arch/arm/mach-omap2/clock3xxx_data.c
View File

@ -3215,7 +3215,6 @@ static struct clk dummy_apb_pclk = {
* clkdev
*/
/* XXX At some point we should rename this file to clock3xxx_data.c */
static struct omap_clk omap3xxx_clks[] = {
CLK(NULL, "apb_pclk", &dummy_apb_pclk, CK_3XXX),
CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_3XXX),
@ -3243,11 +3242,13 @@ static struct omap_clk omap3xxx_clks[] = {
CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX),
CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_3XXX),
CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX),
CLK(NULL, "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
CLK(NULL, "dpll4_ck", &dpll4_ck, CK_3XXX),
CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_3XXX),
CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX),
CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
CLK(NULL, "omap_96m_alwon_fck_3630", &omap_96m_alwon_fck_3630, CK_36XX),
CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_3XXX),
CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_3XXX),
CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_3XXX),
@ -3263,6 +3264,7 @@ static struct omap_clk omap3xxx_clks[] = {
CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX),
CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_3XXX),
CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
CLK(NULL, "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
@ -3272,6 +3274,7 @@ static struct omap_clk omap3xxx_clks[] = {
CLK(NULL, "dpll1_fck", &dpll1_fck, CK_3XXX),
CLK(NULL, "mpu_ck", &mpu_ck, CK_3XXX),
CLK(NULL, "arm_fck", &arm_fck, CK_3XXX),
CLK(NULL, "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
CLK(NULL, "dpll2_fck", &dpll2_fck, CK_34XX | CK_36XX),
CLK(NULL, "iva2_ck", &iva2_ck, CK_34XX | CK_36XX),
@ -3295,6 +3298,7 @@ static struct omap_clk omap3xxx_clks[] = {
CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK("usbhs_omap", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK("usbhs_tll", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX),
CLK(NULL, "mmchs3_fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_3XXX),
@ -3315,6 +3319,7 @@ static struct omap_clk omap3xxx_clks[] = {
CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX),
CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX),
CLK(NULL, "hdq_fck", &hdq_fck, CK_3XXX),
CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1),
CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2PLUS | CK_36XX),
CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1),
@ -3322,6 +3327,8 @@ static struct omap_clk omap3xxx_clks[] = {
CLK(NULL, "core_l3_ick", &core_l3_ick, CK_3XXX),
CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1, CK_3430ES1),
CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX),
CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es1, CK_3430ES1),
CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX),
CLK(NULL, "sdrc_ick", &sdrc_ick, CK_3XXX),
CLK(NULL, "gpmc_fck", &gpmc_fck, CK_3XXX),
CLK(NULL, "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX),
@ -3329,28 +3336,42 @@ static struct omap_clk omap3xxx_clks[] = {
CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX),
CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK("usbhs_omap", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK("usbhs_tll", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK("omap_hsmmc.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK(NULL, "mmchs3_ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK(NULL, "icr_ick", &icr_ick, CK_34XX | CK_36XX),
CLK("omap-aes", "ick", &aes2_ick, CK_34XX | CK_36XX),
CLK("omap-sham", "ick", &sha12_ick, CK_34XX | CK_36XX),
CLK(NULL, "des2_ick", &des2_ick, CK_34XX | CK_36XX),
CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_3XXX),
CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_3XXX),
CLK(NULL, "mmchs2_ick", &mmchs2_ick, CK_3XXX),
CLK(NULL, "mmchs1_ick", &mmchs1_ick, CK_3XXX),
CLK(NULL, "mspro_ick", &mspro_ick, CK_34XX | CK_36XX),
CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX),
CLK(NULL, "hdq_ick", &hdq_ick, CK_3XXX),
CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX),
CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_3XXX),
CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_3XXX),
CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_3XXX),
CLK(NULL, "mcspi4_ick", &mcspi4_ick, CK_3XXX),
CLK(NULL, "mcspi3_ick", &mcspi3_ick, CK_3XXX),
CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_3XXX),
CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_3XXX),
CLK("omap_i2c.3", "ick", &i2c3_ick, CK_3XXX),
CLK("omap_i2c.2", "ick", &i2c2_ick, CK_3XXX),
CLK("omap_i2c.1", "ick", &i2c1_ick, CK_3XXX),
CLK(NULL, "i2c3_ick", &i2c3_ick, CK_3XXX),
CLK(NULL, "i2c2_ick", &i2c2_ick, CK_3XXX),
CLK(NULL, "i2c1_ick", &i2c1_ick, CK_3XXX),
CLK(NULL, "uart2_ick", &uart2_ick, CK_3XXX),
CLK(NULL, "uart1_ick", &uart1_ick, CK_3XXX),
CLK(NULL, "gpt11_ick", &gpt11_ick, CK_3XXX),
CLK(NULL, "gpt10_ick", &gpt10_ick, CK_3XXX),
CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_3XXX),
CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_3XXX),
CLK(NULL, "mcbsp5_ick", &mcbsp5_ick, CK_3XXX),
CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_3XXX),
CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1),
CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX),
CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_3XXX),
@ -3369,7 +3390,9 @@ static struct omap_clk omap3xxx_clks[] = {
CLK(NULL, "dss_96m_fck", &dss_96m_fck, CK_3XXX),
CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck, CK_3XXX),
CLK("omapdss_dss", "ick", &dss_ick_3430es1, CK_3430ES1),
CLK(NULL, "dss_ick", &dss_ick_3430es1, CK_3430ES1),
CLK("omapdss_dss", "ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK(NULL, "dss_ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK(NULL, "cam_mclk", &cam_mclk, CK_34XX | CK_36XX),
CLK(NULL, "cam_ick", &cam_ick, CK_34XX | CK_36XX),
CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_34XX | CK_36XX),
@ -3385,6 +3408,8 @@ static struct omap_clk omap3xxx_clks[] = {
CLK(NULL, "usb_host_hs_utmi_p2_clk", &dummy_ck, CK_3XXX),
CLK("usbhs_omap", "usb_tll_hs_usb_ch0_clk", &dummy_ck, CK_3XXX),
CLK("usbhs_omap", "usb_tll_hs_usb_ch1_clk", &dummy_ck, CK_3XXX),
CLK("usbhs_tll", "usb_tll_hs_usb_ch0_clk", &dummy_ck, CK_3XXX),
CLK("usbhs_tll", "usb_tll_hs_usb_ch1_clk", &dummy_ck, CK_3XXX),
CLK(NULL, "init_60m_fclk", &dummy_ck, CK_3XXX),
CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2PLUS | CK_36XX),
CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX),
@ -3394,6 +3419,7 @@ static struct omap_clk omap3xxx_clks[] = {
CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_34XX | CK_36XX),
CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2PLUS | CK_36XX),
CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX),
CLK(NULL, "wdt2_ick", &wdt2_ick, CK_3XXX),
CLK(NULL, "wdt1_ick", &wdt1_ick, CK_3XXX),
CLK(NULL, "gpio1_ick", &gpio1_ick, CK_3XXX),
CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
@ -3439,9 +3465,13 @@ static struct omap_clk omap3xxx_clks[] = {
CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_3XXX),
CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_3XXX),
CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_3XXX),
CLK(NULL, "mcbsp4_ick", &mcbsp2_ick, CK_3XXX),
CLK(NULL, "mcbsp3_ick", &mcbsp3_ick, CK_3XXX),
CLK(NULL, "mcbsp2_ick", &mcbsp4_ick, CK_3XXX),
CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_3XXX),
CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_3XXX),
CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_3XXX),
CLK(NULL, "emu_src_ck", &emu_src_ck, CK_3XXX),
CLK("etb", "emu_src_ck", &emu_src_ck, CK_3XXX),
CLK(NULL, "pclk_fck", &pclk_fck, CK_3XXX),
CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_3XXX),
@ -3457,8 +3487,12 @@ static struct omap_clk omap3xxx_clks[] = {
CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX),
CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX),
CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX),
CLK(NULL, "emac_ick", &emac_ick, CK_AM35XX),
CLK(NULL, "emac_fck", &emac_fck, CK_AM35XX),
CLK("davinci_emac.0", NULL, &emac_ick, CK_AM35XX),
CLK("davinci_mdio.0", NULL, &emac_fck, CK_AM35XX),
CLK(NULL, "vpfe_ick", &emac_ick, CK_AM35XX),
CLK(NULL, "vpfe_fck", &emac_fck, CK_AM35XX),
CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX),
CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX),
CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_am35xx, CK_AM35XX),
@ -3467,6 +3501,7 @@ static struct omap_clk omap3xxx_clks[] = {
CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX),
CLK(NULL, "timer_32k_ck", &omap_32k_fck, CK_3XXX),
CLK(NULL, "timer_sys_ck", &sys_ck, CK_3XXX),
CLK(NULL, "cpufreq_ck", &dpll1_ck, CK_3XXX),
};

21
arch/arm/mach-omap2/clock44xx_data.c
View File

@ -3156,6 +3156,7 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X),
CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X),
CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X),
CLK(NULL, "dss_fck", &dss_fck, CK_443X),
CLK("omapdss_dss", "ick", &dss_fck, CK_443X),
CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X),
CLK(NULL, "emif1_fck", &emif1_fck, CK_443X),
@ -3212,6 +3213,7 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X),
CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X),
CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X),
CLK(NULL, "rng_ick", &rng_ick, CK_443X),
CLK("omap_rng", "ick", &rng_ick, CK_443X),
CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X),
CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X),
@ -3243,6 +3245,7 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "uart3_fck", &uart3_fck, CK_443X),
CLK(NULL, "uart4_fck", &uart4_fck, CK_443X),
CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck, CK_443X),
CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X),
CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X),
CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X),
CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X),
@ -3253,15 +3256,19 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X),
CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X),
CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X),
CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X),
CLK("usbhs_omap", "hs_fck", &usb_host_hs_fck, CK_443X),
CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X),
CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X),
CLK(NULL, "usb_otg_hs_ick", &usb_otg_hs_ick, CK_443X),
CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X),
CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_443X),
CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X),
CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X),
CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X),
CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X),
CLK("usbhs_omap", "usbtll_ick", &usb_tll_hs_ick, CK_443X),
CLK("usbhs_tll", "usbtll_ick", &usb_tll_hs_ick, CK_443X),
CLK(NULL, "usim_ck", &usim_ck, CK_443X),
CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
CLK(NULL, "usim_fck", &usim_fck, CK_443X),
@ -3312,8 +3319,10 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "uart4_ick", &dummy_ck, CK_443X),
CLK("usbhs_omap", "usbhost_ick", &dummy_ck, CK_443X),
CLK("usbhs_omap", "usbtll_fck", &dummy_ck, CK_443X),
CLK("usbhs_tll", "usbtll_fck", &dummy_ck, CK_443X),
CLK("omap_wdt", "ick", &dummy_ck, CK_443X),
CLK(NULL, "timer_32k_ck", &sys_32k_ck, CK_443X),
/* TODO: Remove "omap_timer.X" aliases once DT migration is complete */
CLK("omap_timer.1", "timer_sys_ck", &sys_clkin_ck, CK_443X),
CLK("omap_timer.2", "timer_sys_ck", &sys_clkin_ck, CK_443X),
CLK("omap_timer.3", "timer_sys_ck", &sys_clkin_ck, CK_443X),
@ -3325,6 +3334,18 @@ static struct omap_clk omap44xx_clks[] = {
CLK("omap_timer.6", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
CLK("omap_timer.7", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
CLK("omap_timer.8", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
CLK("4a318000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
CLK("48032000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
CLK("48034000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
CLK("48036000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
CLK("4803e000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
CLK("48086000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
CLK("48088000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
CLK("49038000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
CLK("4903a000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
CLK("4903c000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
CLK("4903e000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
CLK(NULL, "cpufreq_ck", &dpll_mpu_ck, CK_443X),
};
int __init omap4xxx_clk_init(void)

17
arch/arm/mach-omap2/clockdomain.c
View File

@ -899,6 +899,23 @@ bool clkdm_in_hwsup(struct clockdomain *clkdm)
return ret;
}
/**
* clkdm_missing_idle_reporting - can @clkdm enter autoidle even if in use?
* @clkdm: struct clockdomain *
*
* Returns true if clockdomain @clkdm has the
* CLKDM_MISSING_IDLE_REPORTING flag set, or false if not or @clkdm is
* null. More information is available in the documentation for the
* CLKDM_MISSING_IDLE_REPORTING macro.
*/
bool clkdm_missing_idle_reporting(struct clockdomain *clkdm)
{
if (!clkdm)
return false;
return (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING) ? true : false;
}
/* Clockdomain-to-clock/hwmod framework interface code */
static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm)

20
arch/arm/mach-omap2/clockdomain.h
View File

@ -1,9 +1,7 @@
/*
* arch/arm/plat-omap/include/mach/clockdomain.h
*
* OMAP2/3 clockdomain framework functions
*
* Copyright (C) 2008 Texas Instruments, Inc.
* Copyright (C) 2008, 2012 Texas Instruments, Inc.
* Copyright (C) 2008-2011 Nokia Corporation
*
* Paul Walmsley
@ -34,6 +32,20 @@
* CLKDM_ACTIVE_WITH_MPU: The PRCM guarantees that this clockdomain is
* active whenever the MPU is active. True for interconnects and
* the WKUP clockdomains.
* CLKDM_MISSING_IDLE_REPORTING: The idle status of the IP blocks and
* clocks inside this clockdomain are not taken into account by
* the PRCM when determining whether the clockdomain is idle.
* Without this flag, if the clockdomain is set to
* hardware-supervised idle mode, the PRCM may transition the
* enclosing powerdomain to a low power state, even when devices
* inside the clockdomain and powerdomain are in use. (An example
* of such a clockdomain is the EMU clockdomain on OMAP3/4.) If
* this flag is set, and the clockdomain does not support the
* force-sleep mode, then the HW_AUTO mode will be used to put the
* clockdomain to sleep. Similarly, if the clockdomain supports
* the force-wakeup mode, then it will be used whenever a clock or
* IP block inside the clockdomain is active, rather than the
* HW_AUTO mode.
*/
#define CLKDM_CAN_FORCE_SLEEP (1 << 0)
#define CLKDM_CAN_FORCE_WAKEUP (1 << 1)
@ -41,6 +53,7 @@
#define CLKDM_CAN_DISABLE_AUTO (1 << 3)
#define CLKDM_NO_AUTODEPS (1 << 4)
#define CLKDM_ACTIVE_WITH_MPU (1 << 5)
#define CLKDM_MISSING_IDLE_REPORTING (1 << 6)
#define CLKDM_CAN_HWSUP (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO)
#define CLKDM_CAN_SWSUP (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP)
@ -187,6 +200,7 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm);
void clkdm_allow_idle(struct clockdomain *clkdm);
void clkdm_deny_idle(struct clockdomain *clkdm);
bool clkdm_in_hwsup(struct clockdomain *clkdm);
bool clkdm_missing_idle_reporting(struct clockdomain *clkdm);
int clkdm_wakeup(struct clockdomain *clkdm);
int clkdm_sleep(struct clockdomain *clkdm);

49
arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
View File

@ -162,6 +162,19 @@ static void _disable_hwsup(struct clockdomain *clkdm)
clkdm->clktrctrl_mask);
}
static int omap3_clkdm_sleep(struct clockdomain *clkdm)
{
omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs,
clkdm->clktrctrl_mask);
return 0;
}
static int omap3_clkdm_wakeup(struct clockdomain *clkdm)
{
omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs,
clkdm->clktrctrl_mask);
return 0;
}
static int omap2_clkdm_clk_enable(struct clockdomain *clkdm)
{
@ -170,6 +183,17 @@ static int omap2_clkdm_clk_enable(struct clockdomain *clkdm)
if (!clkdm->clktrctrl_mask)
return 0;
/*
* The CLKDM_MISSING_IDLE_REPORTING flag documentation has
* more details on the unpleasant problem this is working
* around
*/
if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING &&
!(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) {
_enable_hwsup(clkdm);
return 0;
}
hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
clkdm->clktrctrl_mask);
@ -193,6 +217,17 @@ static int omap2_clkdm_clk_disable(struct clockdomain *clkdm)
if (!clkdm->clktrctrl_mask)
return 0;
/*
* The CLKDM_MISSING_IDLE_REPORTING flag documentation has
* more details on the unpleasant problem this is working
* around
*/
if ((clkdm->flags & CLKDM_MISSING_IDLE_REPORTING) &&
(clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)) {
omap3_clkdm_wakeup(clkdm);
return 0;
}
hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
clkdm->clktrctrl_mask);
@ -209,20 +244,6 @@ static int omap2_clkdm_clk_disable(struct clockdomain *clkdm)
return 0;
}
static int omap3_clkdm_sleep(struct clockdomain *clkdm)
{
omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs,
clkdm->clktrctrl_mask);
return 0;
}
static int omap3_clkdm_wakeup(struct clockdomain *clkdm)
{
omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs,
clkdm->clktrctrl_mask);
return 0;
}
static void omap3_clkdm_allow_idle(struct clockdomain *clkdm)
{
if (atomic_read(&clkdm->usecount) > 0)

11
arch/arm/mach-omap2/clockdomain44xx.c
View File

@ -113,6 +113,17 @@ static int omap4_clkdm_clk_disable(struct clockdomain *clkdm)
if (!clkdm->prcm_partition)
return 0;
/*
* The CLKDM_MISSING_IDLE_REPORTING flag documentation has
* more details on the unpleasant problem this is working
* around
*/
if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING &&
!(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) {
omap4_clkdm_allow_idle(clkdm);
return 0;
}
hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
clkdm->cm_inst, clkdm->clkdm_offs);

7
arch/arm/mach-omap2/clockdomains3xxx_data.c
View File

@ -387,14 +387,11 @@ static struct clockdomain per_am35x_clkdm = {
.clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
};
/*
* Disable hw supervised mode for emu_clkdm, because emu_pwrdm is
* switched of even if sdti is in use
*/
static struct clockdomain emu_clkdm = {
.name = "emu_clkdm",
.pwrdm = { .name = "emu_pwrdm" },
.flags = /* CLKDM_CAN_ENABLE_AUTO | */CLKDM_CAN_SWSUP,
.flags = (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_SWSUP |
CLKDM_MISSING_IDLE_REPORTING),
.clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
};

3
arch/arm/mach-omap2/clockdomains44xx_data.c
View File

@ -390,7 +390,8 @@ static struct clockdomain emu_sys_44xx_clkdm = {
.prcm_partition = OMAP4430_PRM_PARTITION,
.cm_inst = OMAP4430_PRM_EMU_CM_INST,
.clkdm_offs = OMAP4430_PRM_EMU_CM_EMU_CDOFFS,
.flags = CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_FORCE_WAKEUP,
.flags = (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_FORCE_WAKEUP |
CLKDM_MISSING_IDLE_REPORTING),
};
static struct clockdomain l3_dma_44xx_clkdm = {

158
arch/arm/mach-omap2/cm-regbits-33xx.h
View File

@ -25,263 +25,328 @@
* CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER
*/
#define AM33XX_AUTO_DPLL_MODE_SHIFT 0
#define AM33XX_AUTO_DPLL_MODE_WIDTH 3
#define AM33XX_AUTO_DPLL_MODE_MASK (0x7 << 0)
/* Used by CM_WKUP_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_ADC_FCLK_SHIFT 14
#define AM33XX_CLKACTIVITY_ADC_FCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_ADC_FCLK_MASK (1 << 16)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_CAN_CLK_SHIFT 11
#define AM33XX_CLKACTIVITY_CAN_CLK_WIDTH 1
#define AM33XX_CLKACTIVITY_CAN_CLK_MASK (1 << 11)
/* Used by CM_PER_CLK_24MHZ_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_SHIFT 4
#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_MASK (1 << 4)
/* Used by CM_PER_CPSW_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_SHIFT 4
#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_MASK (1 << 4)
/* Used by CM_PER_L4HS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_SHIFT 4
#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_MASK (1 << 4)
/* Used by CM_PER_L4HS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_SHIFT 5
#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_MASK (1 << 5)
/* Used by CM_PER_L4HS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_SHIFT 6
#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_MASK (1 << 6)
/* Used by CM_PER_L3_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_SHIFT 6
#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_MASK (1 << 6)
/* Used by CM_CEFUSE_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9
#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_WIDTH 1
#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9)
/* Used by CM_L3_AON_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_DBGSYSCLK_SHIFT 2
#define AM33XX_CLKACTIVITY_DBGSYSCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_DBGSYSCLK_MASK (1 << 2)
/* Used by CM_L3_AON_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_DEBUG_CLKA_SHIFT 4
#define AM33XX_CLKACTIVITY_DEBUG_CLKA_WIDTH 1
#define AM33XX_CLKACTIVITY_DEBUG_CLKA_MASK (1 << 4)
/* Used by CM_PER_L3_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_EMIF_GCLK_SHIFT 2
#define AM33XX_CLKACTIVITY_EMIF_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_EMIF_GCLK_MASK (1 << 2)
/* Used by CM_GFX_L3_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_GFX_FCLK_SHIFT 9
#define AM33XX_CLKACTIVITY_GFX_FCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_GFX_FCLK_MASK (1 << 9)
/* Used by CM_GFX_L3_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_SHIFT 8
#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_MASK (1 << 8)
/* Used by CM_WKUP_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_SHIFT 8
#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_MASK (1 << 8)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_SHIFT 19
#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_MASK (1 << 19)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_SHIFT 20
#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_MASK (1 << 20)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_SHIFT 21
#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_MASK (1 << 21)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_SHIFT 22
#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_MASK (1 << 22)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_SHIFT 26
#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_MASK (1 << 26)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_SHIFT 18
#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_MASK (1 << 18)
/* Used by CM_WKUP_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_I2C0_GFCLK_SHIFT 11
#define AM33XX_CLKACTIVITY_I2C0_GFCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_I2C0_GFCLK_MASK (1 << 11)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_I2C_FCLK_SHIFT 24
#define AM33XX_CLKACTIVITY_I2C_FCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_I2C_FCLK_MASK (1 << 24)
/* Used by CM_PER_PRUSS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_SHIFT 5
#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_MASK (1 << 5)
/* Used by CM_PER_PRUSS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_SHIFT 4
#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_MASK (1 << 4)
/* Used by CM_PER_PRUSS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_SHIFT 6
#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_MASK (1 << 6)
/* Used by CM_PER_L3S_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_L3S_GCLK_SHIFT 3
#define AM33XX_CLKACTIVITY_L3S_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_L3S_GCLK_MASK (1 << 3)
/* Used by CM_L3_AON_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_L3_AON_GCLK_SHIFT 3
#define AM33XX_CLKACTIVITY_L3_AON_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_L3_AON_GCLK_MASK (1 << 3)
/* Used by CM_PER_L3_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_L3_GCLK_SHIFT 4
#define AM33XX_CLKACTIVITY_L3_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_L3_GCLK_MASK (1 << 4)
/* Used by CM_PER_L4FW_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_L4FW_GCLK_SHIFT 8
#define AM33XX_CLKACTIVITY_L4FW_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_L4FW_GCLK_MASK (1 << 8)
/* Used by CM_PER_L4HS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_L4HS_GCLK_SHIFT 3
#define AM33XX_CLKACTIVITY_L4HS_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_L4HS_GCLK_MASK (1 << 3)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_L4LS_GCLK_SHIFT 8
#define AM33XX_CLKACTIVITY_L4LS_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_L4LS_GCLK_MASK (1 << 8)
/* Used by CM_GFX_L4LS_GFX_CLKSTCTRL__1 */
#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_SHIFT 8
#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_MASK (1 << 8)
/* Used by CM_CEFUSE_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8
#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_WIDTH 1
#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8)
/* Used by CM_RTC_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_SHIFT 8
#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_MASK (1 << 8)
/* Used by CM_L4_WKUP_AON_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_SHIFT 2
#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_MASK (1 << 2)
/* Used by CM_WKUP_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_SHIFT 2
#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_MASK (1 << 2)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_LCDC_GCLK_SHIFT 17
#define AM33XX_CLKACTIVITY_LCDC_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_LCDC_GCLK_MASK (1 << 17)
/* Used by CM_PER_LCDC_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_SHIFT 4
#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_MASK (1 << 4)
/* Used by CM_PER_LCDC_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_SHIFT 5
#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_MASK (1 << 5)
/* Used by CM_PER_L3_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_MCASP_GCLK_SHIFT 7
#define AM33XX_CLKACTIVITY_MCASP_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_MCASP_GCLK_MASK (1 << 7)
/* Used by CM_PER_L3_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_MMC_FCLK_SHIFT 3
#define AM33XX_CLKACTIVITY_MMC_FCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_MMC_FCLK_MASK (1 << 3)
/* Used by CM_MPU_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_MPU_CLK_SHIFT 2
#define AM33XX_CLKACTIVITY_MPU_CLK_WIDTH 1
#define AM33XX_CLKACTIVITY_MPU_CLK_MASK (1 << 2)
/* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_SHIFT 4
#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_MASK (1 << 4)
/* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_SHIFT 5
#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_MASK (1 << 5)
/* Used by CM_RTC_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_RTC_32KCLK_SHIFT 9
#define AM33XX_CLKACTIVITY_RTC_32KCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_RTC_32KCLK_MASK (1 << 9)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_SPI_GCLK_SHIFT 25
#define AM33XX_CLKACTIVITY_SPI_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_SPI_GCLK_MASK (1 << 25)
/* Used by CM_WKUP_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_SR_SYSCLK_SHIFT 3
#define AM33XX_CLKACTIVITY_SR_SYSCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_SR_SYSCLK_MASK (1 << 3)
/* Used by CM_WKUP_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_TIMER0_GCLK_SHIFT 10
#define AM33XX_CLKACTIVITY_TIMER0_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_TIMER0_GCLK_MASK (1 << 10)
/* Used by CM_WKUP_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_TIMER1_GCLK_SHIFT 13
#define AM33XX_CLKACTIVITY_TIMER1_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_TIMER1_GCLK_MASK (1 << 13)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_TIMER2_GCLK_SHIFT 14
#define AM33XX_CLKACTIVITY_TIMER2_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_TIMER2_GCLK_MASK (1 << 14)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_TIMER3_GCLK_SHIFT 15
#define AM33XX_CLKACTIVITY_TIMER3_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_TIMER3_GCLK_MASK (1 << 15)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_TIMER4_GCLK_SHIFT 16
#define AM33XX_CLKACTIVITY_TIMER4_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_TIMER4_GCLK_MASK (1 << 16)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_TIMER5_GCLK_SHIFT 27
#define AM33XX_CLKACTIVITY_TIMER5_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_TIMER5_GCLK_MASK (1 << 27)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_TIMER6_GCLK_SHIFT 28
#define AM33XX_CLKACTIVITY_TIMER6_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_TIMER6_GCLK_MASK (1 << 28)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_TIMER7_GCLK_SHIFT 13
#define AM33XX_CLKACTIVITY_TIMER7_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_TIMER7_GCLK_MASK (1 << 13)
/* Used by CM_WKUP_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_UART0_GFCLK_SHIFT 12
#define AM33XX_CLKACTIVITY_UART0_GFCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_UART0_GFCLK_MASK (1 << 12)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_UART_GFCLK_SHIFT 10
#define AM33XX_CLKACTIVITY_UART_GFCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_UART_GFCLK_MASK (1 << 10)
/* Used by CM_WKUP_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_WDT0_GCLK_SHIFT 9
#define AM33XX_CLKACTIVITY_WDT0_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_WDT0_GCLK_MASK (1 << 9)
/* Used by CM_WKUP_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_WDT1_GCLK_SHIFT 4
#define AM33XX_CLKACTIVITY_WDT1_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_WDT1_GCLK_MASK (1 << 4)
/* Used by CLKSEL_GFX_FCLK */
#define AM33XX_CLKDIV_SEL_GFX_FCLK_SHIFT 0
#define AM33XX_CLKDIV_SEL_GFX_FCLK_WIDTH 1
#define AM33XX_CLKDIV_SEL_GFX_FCLK_MASK (1 << 0)
/* Used by CM_CLKOUT_CTRL */
#define AM33XX_CLKOUT2DIV_SHIFT 3
#define AM33XX_CLKOUT2DIV_MASK (0x05 << 3)
#define AM33XX_CLKOUT2DIV_WIDTH 3
#define AM33XX_CLKOUT2DIV_MASK (0x7 << 3)
/* Used by CM_CLKOUT_CTRL */
#define AM33XX_CLKOUT2EN_SHIFT 7
#define AM33XX_CLKOUT2EN_WIDTH 1
#define AM33XX_CLKOUT2EN_MASK (1 << 7)
/* Used by CM_CLKOUT_CTRL */
#define AM33XX_CLKOUT2SOURCE_SHIFT 0
#define AM33XX_CLKOUT2SOURCE_MASK (0x02 << 0)
#define AM33XX_CLKOUT2SOURCE_WIDTH 3
#define AM33XX_CLKOUT2SOURCE_MASK (0x7 << 0)
/*
* Used by CLKSEL_GPIO0_DBCLK, CLKSEL_LCDC_PIXEL_CLK, CLKSEL_TIMER2_CLK,
@ -289,6 +354,7 @@
* CLKSEL_TIMER7_CLK
*/
#define AM33XX_CLKSEL_SHIFT 0
#define AM33XX_CLKSEL_WIDTH 1
#define AM33XX_CLKSEL_MASK (0x01 << 0)
/*
@ -296,17 +362,21 @@
* CM_CPTS_RFT_CLKSEL
*/
#define AM33XX_CLKSEL_0_0_SHIFT 0
#define AM33XX_CLKSEL_0_0_WIDTH 1
#define AM33XX_CLKSEL_0_0_MASK (1 << 0)
#define AM33XX_CLKSEL_0_1_SHIFT 0
#define AM33XX_CLKSEL_0_1_WIDTH 2
#define AM33XX_CLKSEL_0_1_MASK (3 << 0)
/* Renamed from CLKSEL Used by CLKSEL_TIMER1MS_CLK */
#define AM33XX_CLKSEL_0_2_SHIFT 0
#define AM33XX_CLKSEL_0_2_WIDTH 3
#define AM33XX_CLKSEL_0_2_MASK (7 << 0)
/* Used by CLKSEL_GFX_FCLK */
#define AM33XX_CLKSEL_GFX_FCLK_SHIFT 1
#define AM33XX_CLKSEL_GFX_FCLK_WIDTH 1
#define AM33XX_CLKSEL_GFX_FCLK_MASK (1 << 1)
/*
@ -318,6 +388,7 @@
* CM_GFX_L3_CLKSTCTRL, CM_GFX_L4LS_GFX_CLKSTCTRL__1, CM_CEFUSE_CLKSTCTRL
*/
#define AM33XX_CLKTRCTRL_SHIFT 0
#define AM33XX_CLKTRCTRL_WIDTH 2
#define AM33XX_CLKTRCTRL_MASK (0x3 << 0)
/*
@ -326,34 +397,42 @@
* CM_SSC_DELTAMSTEP_DPLL_PER
*/
#define AM33XX_DELTAMSTEP_SHIFT 0
#define AM33XX_DELTAMSTEP_MASK (0x19 << 0)
#define AM33XX_DELTAMSTEP_WIDTH 20
#define AM33XX_DELTAMSTEP_MASK (0xfffff << 0)
/* Used by CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, CM_CLKSEL_DPLL_MPU */
#define AM33XX_DPLL_BYP_CLKSEL_SHIFT 23
#define AM33XX_DPLL_BYP_CLKSEL_WIDTH 1
#define AM33XX_DPLL_BYP_CLKSEL_MASK (1 << 23)
/* Used by CM_CLKDCOLDO_DPLL_PER */
#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8
#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_WIDTH 1
#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8)
/* Used by CM_CLKDCOLDO_DPLL_PER */
#define AM33XX_DPLL_CLKDCOLDO_PWDN_SHIFT 12
#define AM33XX_DPLL_CLKDCOLDO_PWDN_WIDTH 1
#define AM33XX_DPLL_CLKDCOLDO_PWDN_MASK (1 << 12)
/* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
#define AM33XX_DPLL_CLKOUT_DIV_SHIFT 0
#define AM33XX_DPLL_CLKOUT_DIV_WIDTH 5
#define AM33XX_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
/* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_PER */
#define AM33XX_DPLL_CLKOUT_DIV_0_6_SHIFT 0
#define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK (0x06 << 0)
#define AM33XX_DPLL_CLKOUT_DIV_0_6_WIDTH 7
#define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0)
/* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
#define AM33XX_DPLL_CLKOUT_DIVCHACK_SHIFT 5
#define AM33XX_DPLL_CLKOUT_DIVCHACK_WIDTH 1
#define AM33XX_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5)
/* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_PER */
#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_SHIFT 7
#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_WIDTH 1
#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_MASK (1 << 7)
/*
@ -361,6 +440,7 @@
* CM_DIV_M2_DPLL_PER
*/
#define AM33XX_DPLL_CLKOUT_GATE_CTRL_SHIFT 8
#define AM33XX_DPLL_CLKOUT_GATE_CTRL_WIDTH 1
#define AM33XX_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8)
/*
@ -368,19 +448,22 @@
* CM_CLKSEL_DPLL_MPU
*/
#define AM33XX_DPLL_DIV_SHIFT 0
#define AM33XX_DPLL_DIV_WIDTH 7
#define AM33XX_DPLL_DIV_MASK (0x7f << 0)
#define AM33XX_DPLL_PER_DIV_MASK (0xff << 0)
/* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_PERIPH */
#define AM33XX_DPLL_DIV_0_7_SHIFT 0
#define AM33XX_DPLL_DIV_0_7_MASK (0x07 << 0)
#define AM33XX_DPLL_DIV_0_7_WIDTH 8
#define AM33XX_DPLL_DIV_0_7_MASK (0xff << 0)
/*
* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
* CM_CLKMODE_DPLL_MPU
*/
#define AM33XX_DPLL_DRIFTGUARD_EN_SHIFT 8
#define AM33XX_DPLL_DRIFTGUARD_EN_WIDTH 1
#define AM33XX_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
/*
@ -388,6 +471,7 @@
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
*/
#define AM33XX_DPLL_EN_SHIFT 0
#define AM33XX_DPLL_EN_WIDTH 3
#define AM33XX_DPLL_EN_MASK (0x7 << 0)
/*
@ -395,6 +479,7 @@
* CM_CLKMODE_DPLL_MPU
*/
#define AM33XX_DPLL_LPMODE_EN_SHIFT 10
#define AM33XX_DPLL_LPMODE_EN_WIDTH 1
#define AM33XX_DPLL_LPMODE_EN_MASK (1 << 10)
/*
@ -402,10 +487,12 @@
* CM_CLKSEL_DPLL_MPU
*/
#define AM33XX_DPLL_MULT_SHIFT 8
#define AM33XX_DPLL_MULT_WIDTH 11
#define AM33XX_DPLL_MULT_MASK (0x7ff << 8)
/* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_PERIPH */
#define AM33XX_DPLL_MULT_PERIPH_SHIFT 8
#define AM33XX_DPLL_MULT_PERIPH_WIDTH 12
#define AM33XX_DPLL_MULT_PERIPH_MASK (0xfff << 8)
/*
@ -413,17 +500,20 @@
* CM_CLKMODE_DPLL_MPU
*/
#define AM33XX_DPLL_REGM4XEN_SHIFT 11
#define AM33XX_DPLL_REGM4XEN_WIDTH 1
#define AM33XX_DPLL_REGM4XEN_MASK (1 << 11)
/* Used by CM_CLKSEL_DPLL_PERIPH */
#define AM33XX_DPLL_SD_DIV_SHIFT 24
#define AM33XX_DPLL_SD_DIV_MASK (24, 31)
#define AM33XX_DPLL_SD_DIV_WIDTH 8
#define AM33XX_DPLL_SD_DIV_MASK (0xff << 24)
/*
* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
*/
#define AM33XX_DPLL_SSC_ACK_SHIFT 13
#define AM33XX_DPLL_SSC_ACK_WIDTH 1
#define AM33XX_DPLL_SSC_ACK_MASK (1 << 13)
/*
@ -431,6 +521,7 @@
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
*/
#define AM33XX_DPLL_SSC_DOWNSPREAD_SHIFT 14
#define AM33XX_DPLL_SSC_DOWNSPREAD_WIDTH 1
#define AM33XX_DPLL_SSC_DOWNSPREAD_MASK (1 << 14)
/*
@ -438,54 +529,67 @@
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
*/
#define AM33XX_DPLL_SSC_EN_SHIFT 12
#define AM33XX_DPLL_SSC_EN_WIDTH 1
#define AM33XX_DPLL_SSC_EN_MASK (1 << 12)
/* Used by CM_DIV_M4_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT 0
#define AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH 5
#define AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0)
/* Used by CM_DIV_M4_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5
#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_WIDTH 1
#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5)
/* Used by CM_DIV_M4_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8
#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_WIDTH 1
#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8)
/* Used by CM_DIV_M4_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12
#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_WIDTH 1
#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12)
/* Used by CM_DIV_M5_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT 0
#define AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH 5
#define AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0)
/* Used by CM_DIV_M5_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5
#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_WIDTH 1
#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5)
/* Used by CM_DIV_M5_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8
#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_WIDTH 1
#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8)
/* Used by CM_DIV_M5_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12
#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_WIDTH 1
#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12)
/* Used by CM_DIV_M6_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT 0
#define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK (0x04 << 0)
#define AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH 5
#define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0)
/* Used by CM_DIV_M6_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5
#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_WIDTH 1
#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5)
/* Used by CM_DIV_M6_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8
#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_WIDTH 1
#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8)
/* Used by CM_DIV_M6_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12
#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_WIDTH 1
#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12)
/*
@ -522,11 +626,12 @@
* CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL
*/
#define AM33XX_IDLEST_SHIFT 16
#define AM33XX_IDLEST_WIDTH 2
#define AM33XX_IDLEST_MASK (0x3 << 16)
#define AM33XX_IDLEST_VAL 0x3
/* Used by CM_MAC_CLKSEL */
#define AM33XX_MII_CLK_SEL_SHIFT 2
#define AM33XX_MII_CLK_SEL_WIDTH 1
#define AM33XX_MII_CLK_SEL_MASK (1 << 2)
/*
@ -535,7 +640,8 @@
* CM_SSC_MODFREQDIV_DPLL_PER
*/
#define AM33XX_MODFREQDIV_EXPONENT_SHIFT 8
#define AM33XX_MODFREQDIV_EXPONENT_MASK (0x10 << 8)
#define AM33XX_MODFREQDIV_EXPONENT_WIDTH 3
#define AM33XX_MODFREQDIV_EXPONENT_MASK (0x7 << 8)
/*
* Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR,
@ -543,7 +649,8 @@
* CM_SSC_MODFREQDIV_DPLL_PER
*/
#define AM33XX_MODFREQDIV_MANTISSA_SHIFT 0
#define AM33XX_MODFREQDIV_MANTISSA_MASK (0x06 << 0)
#define AM33XX_MODFREQDIV_MANTISSA_WIDTH 7
#define AM33XX_MODFREQDIV_MANTISSA_MASK (0x7f << 0)
/*
* Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL,
@ -580,42 +687,52 @@
* CM_CEFUSE_CEFUSE_CLKCTRL
*/
#define AM33XX_MODULEMODE_SHIFT 0
#define AM33XX_MODULEMODE_WIDTH 2
#define AM33XX_MODULEMODE_MASK (0x3 << 0)
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
#define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT 30
#define AM33XX_OPTCLK_DEBUG_CLKA_WIDTH 1
#define AM33XX_OPTCLK_DEBUG_CLKA_MASK (1 << 30)
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
#define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT 19
#define AM33XX_OPTFCLKEN_DBGSYSCLK_WIDTH 1
#define AM33XX_OPTFCLKEN_DBGSYSCLK_MASK (1 << 19)
/* Used by CM_WKUP_GPIO0_CLKCTRL */
#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT 18
#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_WIDTH 1
#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_MASK (1 << 18)
/* Used by CM_PER_GPIO1_CLKCTRL */
#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT 18
#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_WIDTH 1
#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_MASK (1 << 18)
/* Used by CM_PER_GPIO2_CLKCTRL */
#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT 18
#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_WIDTH 1
#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_MASK (1 << 18)
/* Used by CM_PER_GPIO3_CLKCTRL */
#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT 18
#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_WIDTH 1
#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_MASK (1 << 18)
/* Used by CM_PER_GPIO4_CLKCTRL */
#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_SHIFT 18
#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_WIDTH 1
#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_MASK (1 << 18)
/* Used by CM_PER_GPIO5_CLKCTRL */
#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_SHIFT 18
#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_WIDTH 1
#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_MASK (1 << 18)
/* Used by CM_PER_GPIO6_CLKCTRL */
#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_SHIFT 18
#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_WIDTH 1
#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_MASK (1 << 18)
/*
@ -627,25 +744,30 @@
* CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL
*/
#define AM33XX_STBYST_SHIFT 18
#define AM33XX_STBYST_WIDTH 1
#define AM33XX_STBYST_MASK (1 << 18)
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
#define AM33XX_STM_PMD_CLKDIVSEL_SHIFT 27
#define AM33XX_STM_PMD_CLKDIVSEL_MASK (0x29 << 27)
#define AM33XX_STM_PMD_CLKDIVSEL_WIDTH 3
#define AM33XX_STM_PMD_CLKDIVSEL_MASK (0x7 << 27)
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
#define AM33XX_STM_PMD_CLKSEL_SHIFT 22
#define AM33XX_STM_PMD_CLKSEL_MASK (0x23 << 22)
#define AM33XX_STM_PMD_CLKSEL_WIDTH 2
#define AM33XX_STM_PMD_CLKSEL_MASK (0x3 << 22)
/*
* Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP,
* CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
*/
#define AM33XX_ST_DPLL_CLK_SHIFT 0
#define AM33XX_ST_DPLL_CLK_WIDTH 1
#define AM33XX_ST_DPLL_CLK_MASK (1 << 0)
/* Used by CM_CLKDCOLDO_DPLL_PER */
#define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT 8
#define AM33XX_ST_DPLL_CLKDCOLDO_WIDTH 1
#define AM33XX_ST_DPLL_CLKDCOLDO_MASK (1 << 8)
/*
@ -653,18 +775,22 @@
* CM_DIV_M2_DPLL_PER
*/
#define AM33XX_ST_DPLL_CLKOUT_SHIFT 9
#define AM33XX_ST_DPLL_CLKOUT_WIDTH 1
#define AM33XX_ST_DPLL_CLKOUT_MASK (1 << 9)
/* Used by CM_DIV_M4_DPLL_CORE */
#define AM33XX_ST_HSDIVIDER_CLKOUT1_SHIFT 9
#define AM33XX_ST_HSDIVIDER_CLKOUT1_WIDTH 1
#define AM33XX_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9)
/* Used by CM_DIV_M5_DPLL_CORE */
#define AM33XX_ST_HSDIVIDER_CLKOUT2_SHIFT 9
#define AM33XX_ST_HSDIVIDER_CLKOUT2_WIDTH 1
#define AM33XX_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9)
/* Used by CM_DIV_M6_DPLL_CORE */
#define AM33XX_ST_HSDIVIDER_CLKOUT3_SHIFT 9
#define AM33XX_ST_HSDIVIDER_CLKOUT3_WIDTH 1
#define AM33XX_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9)
/*
@ -672,16 +798,20 @@
* CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
*/
#define AM33XX_ST_MN_BYPASS_SHIFT 8
#define AM33XX_ST_MN_BYPASS_WIDTH 1
#define AM33XX_ST_MN_BYPASS_MASK (1 << 8)
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
#define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT 24
#define AM33XX_TRC_PMD_CLKDIVSEL_MASK (0x26 << 24)
#define AM33XX_TRC_PMD_CLKDIVSEL_WIDTH 3
#define AM33XX_TRC_PMD_CLKDIVSEL_MASK (0x7 << 24)
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
#define AM33XX_TRC_PMD_CLKSEL_SHIFT 20
#define AM33XX_TRC_PMD_CLKSEL_MASK (0x21 << 20)
#define AM33XX_TRC_PMD_CLKSEL_WIDTH 2
#define AM33XX_TRC_PMD_CLKSEL_MASK (0x3 << 20)
/* Used by CONTROL_SEC_CLK_CTRL */
#define AM33XX_TIMER0_CLKSEL_WIDTH 2
#define AM33XX_TIMER0_CLKSEL_MASK (0x3 << 4)
#endif

2
arch/arm/mach-omap2/cm-regbits-34xx.h
View File

@ -218,6 +218,8 @@
#define OMAP3430_ST_MAILBOXES_MASK (1 << 7)
#define OMAP3430_ST_OMAPCTRL_SHIFT 6
#define OMAP3430_ST_OMAPCTRL_MASK (1 << 6)
#define OMAP3430_ST_SAD2D_SHIFT 3
#define OMAP3430_ST_SAD2D_MASK (1 << 3)
#define OMAP3430_ST_SDMA_SHIFT 2
#define OMAP3430_ST_SDMA_MASK (1 << 2)
#define OMAP3430_ST_SDRC_SHIFT 1

411
arch/arm/mach-omap2/cm-regbits-44xx.h
View File

File diff suppressed because it is too large Load Diff

2
arch/arm/mach-omap2/cm2xxx_3xxx.c
View File

@ -35,7 +35,7 @@
#define OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP 0x3
static const u8 cm_idlest_offs[] = {
CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3, OMAP24XX_CM_IDLEST4
};
u32 omap2_cm_read_mod_reg(s16 module, u16 idx)

1
arch/arm/mach-omap2/cm2xxx_3xxx.h
View File

@ -71,6 +71,7 @@
#define OMAP24XX_CM_FCLKEN2 0x0004
#define OMAP24XX_CM_ICLKEN4 0x001c
#define OMAP24XX_CM_AUTOIDLE4 0x003c
#define OMAP24XX_CM_IDLEST4 0x002c
#define OMAP2430_CM_IDLEST3 0x0028

1
arch/arm/mach-omap2/control.h
View File

@ -354,6 +354,7 @@
/* AM33XX CONTROL_STATUS bitfields (partial) */
#define AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT 22
#define AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH 0x2
#define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK (0x3 << 22)
/* CONTROL OMAP STATUS register to identify OMAP3 features */

39
arch/arm/mach-omap2/devices.c
View File

@ -433,35 +433,24 @@ static void omap_init_mcspi(void)
static inline void omap_init_mcspi(void) {}
#endif
static struct resource omap2_pmu_resource = {
.start = 3 + OMAP_INTC_START,
.flags = IORESOURCE_IRQ,
};
static struct resource omap3_pmu_resource = {
.start = 3 + OMAP_INTC_START,
.flags = IORESOURCE_IRQ,
};
static struct platform_device omap_pmu_device = {
.name = "arm-pmu",
.id = -1,
.num_resources = 1,
};
static void omap_init_pmu(void)
/**
* omap_init_rng - bind the RNG hwmod to the RNG omap_device
*
* Bind the RNG hwmod to the RNG omap_device. No return value.
*/
static void omap_init_rng(void)
{
if (cpu_is_omap24xx())
omap_pmu_device.resource = &omap2_pmu_resource;
else if (cpu_is_omap34xx())
omap_pmu_device.resource = &omap3_pmu_resource;
else
struct omap_hwmod *oh;
struct platform_device *pdev;
oh = omap_hwmod_lookup("rng");
if (!oh)
return;
platform_device_register(&omap_pmu_device);
pdev = omap_device_build("omap_rng", -1, oh, NULL, 0, NULL, 0, 0);
WARN(IS_ERR(pdev), "Can't build omap_device for omap_rng\n");
}
#if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE)
#ifdef CONFIG_ARCH_OMAP2
@ -646,8 +635,8 @@ static int __init omap2_init_devices(void)
omap_init_mcpdm();
omap_init_mcspi();
}
omap_init_pmu();
omap_init_sti();
omap_init_rng();
omap_init_sham();
omap_init_aes();
omap_init_vout();

4
arch/arm/mach-omap2/display.c
View File

@ -488,7 +488,7 @@ int omap_dss_reset(struct omap_hwmod *oh)
for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
if (oc->_clk)
clk_enable(oc->_clk);
clk_prepare_enable(oc->_clk);
dispc_disable_outputs();
@ -515,7 +515,7 @@ int omap_dss_reset(struct omap_hwmod *oh)
for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
if (oc->_clk)
clk_disable(oc->_clk);
clk_disable_unprepare(oc->_clk);
r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;

48
arch/arm/mach-omap2/dpll3xxx.c
View File

@ -63,8 +63,10 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
const struct dpll_data *dd;
int i = 0;
int ret = -EINVAL;
const char *clk_name;
dd = clk->dpll_data;
clk_name = __clk_get_name(clk);
state <<= __ffs(dd->idlest_mask);
@ -76,10 +78,10 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
if (i == MAX_DPLL_WAIT_TRIES) {
printk(KERN_ERR "clock: %s failed transition to '%s'\n",
clk->name, (state) ? "locked" : "bypassed");
clk_name, (state) ? "locked" : "bypassed");
} else {
pr_debug("clock: %s transition to '%s' in %d loops\n",
clk->name, (state) ? "locked" : "bypassed", i);
clk_name, (state) ? "locked" : "bypassed", i);
ret = 0;
}
@ -93,7 +95,7 @@ static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
unsigned long fint;
u16 f = 0;
fint = clk->dpll_data->clk_ref->rate / n;
fint = __clk_get_rate(clk->dpll_data->clk_ref) / n;
pr_debug("clock: fint is %lu\n", fint);
@ -140,7 +142,7 @@ static int _omap3_noncore_dpll_lock(struct clk *clk)
u8 state = 1;
int r = 0;
pr_debug("clock: locking DPLL %s\n", clk->name);
pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk));
dd = clk->dpll_data;
state <<= __ffs(dd->idlest_mask);
@ -187,7 +189,7 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk)
return -EINVAL;
pr_debug("clock: configuring DPLL %s for low-power bypass\n",
clk->name);
__clk_get_name(clk));
ai = omap3_dpll_autoidle_read(clk);
@ -217,7 +219,7 @@ static int _omap3_noncore_dpll_stop(struct clk *clk)
if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
return -EINVAL;
pr_debug("clock: stopping DPLL %s\n", clk->name);
pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk));
ai = omap3_dpll_autoidle_read(clk);
@ -245,7 +247,7 @@ static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n)
{
unsigned long fint, clkinp; /* watch out for overflow */
clkinp = clk->parent->rate;
clkinp = __clk_get_rate(__clk_get_parent(clk));
fint = (clkinp / n) * m;
if (fint < 1000000000)
@ -271,7 +273,7 @@ static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n)
unsigned long clkinp, sd; /* watch out for overflow */
int mod1, mod2;
clkinp = clk->parent->rate;
clkinp = __clk_get_rate(__clk_get_parent(clk));
/*
* target sigma-delta to near 250MHz
@ -380,16 +382,19 @@ int omap3_noncore_dpll_enable(struct clk *clk)
{
int r;
struct dpll_data *dd;
struct clk *parent;
dd = clk->dpll_data;
if (!dd)
return -EINVAL;
if (clk->rate == dd->clk_bypass->rate) {
WARN_ON(clk->parent != dd->clk_bypass);
parent = __clk_get_parent(clk);
if (__clk_get_rate(clk) == __clk_get_rate(dd->clk_bypass)) {
WARN_ON(parent != dd->clk_bypass);
r = _omap3_noncore_dpll_bypass(clk);
} else {
WARN_ON(clk->parent != dd->clk_ref);
WARN_ON(parent != dd->clk_ref);
r = _omap3_noncore_dpll_lock(clk);
}
/*
@ -432,7 +437,7 @@ void omap3_noncore_dpll_disable(struct clk *clk)
int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
{
struct clk *new_parent = NULL;
unsigned long hw_rate;
unsigned long hw_rate, bypass_rate;
u16 freqsel = 0;
struct dpll_data *dd;
int ret;
@ -456,7 +461,8 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
omap2_clk_enable(dd->clk_bypass);
omap2_clk_enable(dd->clk_ref);
if (dd->clk_bypass->rate == rate &&
bypass_rate = __clk_get_rate(dd->clk_bypass);
if (bypass_rate == rate &&
(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
@ -479,7 +485,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
}
pr_debug("clock: %s: set rate: locking rate to %lu.\n",
clk->name, rate);
__clk_get_name(clk), rate);
ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
dd->last_rounded_n, freqsel);
@ -557,7 +563,7 @@ void omap3_dpll_allow_idle(struct clk *clk)
if (!dd->autoidle_reg) {
pr_debug("clock: DPLL %s: autoidle not supported\n",
clk->name);
__clk_get_name(clk));
return;
}
@ -591,7 +597,7 @@ void omap3_dpll_deny_idle(struct clk *clk)
if (!dd->autoidle_reg) {
pr_debug("clock: DPLL %s: autoidle not supported\n",
clk->name);
__clk_get_name(clk));
return;
}
@ -617,11 +623,12 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk)
unsigned long rate;
u32 v;
struct clk *pclk;
unsigned long parent_rate;
/* Walk up the parents of clk, looking for a DPLL */
pclk = clk->parent;
pclk = __clk_get_parent(clk);
while (pclk && !pclk->dpll_data)
pclk = pclk->parent;
pclk = __clk_get_parent(pclk);
/* clk does not have a DPLL as a parent? error in the clock data */
if (!pclk) {
@ -633,12 +640,13 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk)
WARN_ON(!dd->enable_mask);
parent_rate = __clk_get_rate(__clk_get_parent(clk));
v = __raw_readl(dd->control_reg) & dd->enable_mask;
v >>= __ffs(dd->enable_mask);
if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE))
rate = clk->parent->rate;
rate = parent_rate;
else
rate = clk->parent->rate * 2;
rate = parent_rate * 2;
return rate;
}

196
arch/arm/mach-omap2/gpmc.c
View File

@ -24,6 +24,7 @@
#include <linux/io.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <asm/mach-types.h>
#include <plat/gpmc.h>
@ -31,10 +32,13 @@
#include <plat/cpu.h>
#include <plat/gpmc.h>
#include <plat/sdrc.h>
#include <plat/omap_device.h>
#include "soc.h"
#include "common.h"
#define DEVICE_NAME "omap-gpmc"
/* GPMC register offsets */
#define GPMC_REVISION 0x00
#define GPMC_SYSCONFIG 0x10
@ -83,6 +87,12 @@
#define ENABLE_PREFETCH (0x1 << 7)
#define DMA_MPU_MODE 2
#define GPMC_REVISION_MAJOR(l) ((l >> 4) & 0xf)
#define GPMC_REVISION_MINOR(l) (l & 0xf)
#define GPMC_HAS_WR_ACCESS 0x1
#define GPMC_HAS_WR_DATA_MUX_BUS 0x2
/* XXX: Only NAND irq has been considered,currently these are the only ones used
*/
#define GPMC_NR_IRQ 2
@ -128,7 +138,10 @@ static struct resource gpmc_cs_mem[GPMC_CS_NUM];
static DEFINE_SPINLOCK(gpmc_mem_lock);
static unsigned int gpmc_cs_map; /* flag for cs which are initialized */
static int gpmc_ecc_used = -EINVAL; /* cs using ecc engine */
static struct device *gpmc_dev;
static int gpmc_irq;
static resource_size_t phys_base, mem_size;
static unsigned gpmc_capability;
static void __iomem *gpmc_base;
static struct clk *gpmc_l3_clk;
@ -318,10 +331,10 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
if (cpu_is_omap34xx()) {
if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
if (gpmc_capability & GPMC_HAS_WR_ACCESS)
GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
}
/* caller is expected to have initialized CONFIG1 to cover
* at least sync vs async
@ -431,6 +444,20 @@ static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
return r;
}
static int gpmc_cs_delete_mem(int cs)
{
struct resource *res = &gpmc_cs_mem[cs];
int r;
spin_lock(&gpmc_mem_lock);
r = release_resource(&gpmc_cs_mem[cs]);
res->start = 0;
res->end = 0;
spin_unlock(&gpmc_mem_lock);
return r;
}
int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
{
struct resource *res = &gpmc_cs_mem[cs];
@ -767,7 +794,7 @@ static void gpmc_irq_noop(struct irq_data *data) { }
static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; }
static int gpmc_setup_irq(int gpmc_irq)
static int gpmc_setup_irq(void)
{
int i;
u32 regval;
@ -811,7 +838,37 @@ static int gpmc_setup_irq(int gpmc_irq)
return request_irq(gpmc_irq, gpmc_handle_irq, 0, "gpmc", NULL);
}
static void __init gpmc_mem_init(void)
static __exit int gpmc_free_irq(void)
{
int i;
if (gpmc_irq)
free_irq(gpmc_irq, NULL);
for (i = 0; i < GPMC_NR_IRQ; i++) {
irq_set_handler(gpmc_client_irq[i].irq, NULL);
irq_set_chip(gpmc_client_irq[i].irq, &no_irq_chip);
irq_modify_status(gpmc_client_irq[i].irq, 0, 0);
}
irq_free_descs(gpmc_irq_start, GPMC_NR_IRQ);
return 0;
}
static void __devexit gpmc_mem_exit(void)
{
int cs;
for (cs = 0; cs < GPMC_CS_NUM; cs++) {
if (!gpmc_cs_mem_enabled(cs))
continue;
gpmc_cs_delete_mem(cs);
}
}
static void __devinit gpmc_mem_init(void)
{
int cs;
unsigned long boot_rom_space = 0;
@ -838,65 +895,104 @@ static void __init gpmc_mem_init(void)
}
}
static int __init gpmc_init(void)
static __devinit int gpmc_probe(struct platform_device *pdev)
{
u32 l;
int ret = -EINVAL;
int gpmc_irq;
char *ck = NULL;
struct resource *res;
if (cpu_is_omap24xx()) {
ck = "core_l3_ck";
if (cpu_is_omap2420())
l = OMAP2420_GPMC_BASE;
else
l = OMAP34XX_GPMC_BASE;
gpmc_irq = 20 + OMAP_INTC_START;
} else if (cpu_is_omap34xx()) {
ck = "gpmc_fck";
l = OMAP34XX_GPMC_BASE;
gpmc_irq = 20 + OMAP_INTC_START;
} else if (cpu_is_omap44xx() || soc_is_omap54xx()) {
/* Base address and irq number are same for OMAP4/5 */
ck = "gpmc_ck";
l = OMAP44XX_GPMC_BASE;
gpmc_irq = 20 + OMAP44XX_IRQ_GIC_START;
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (res == NULL)
return -ENOENT;
if (WARN_ON(!ck))
return ret;
phys_base = res->start;
mem_size = resource_size(res);
gpmc_l3_clk = clk_get(NULL, ck);
if (IS_ERR(gpmc_l3_clk)) {
printk(KERN_ERR "Could not get GPMC clock %s\n", ck);
BUG();
}
gpmc_base = ioremap(l, SZ_4K);
gpmc_base = devm_request_and_ioremap(&pdev->dev, res);
if (!gpmc_base) {
clk_put(gpmc_l3_clk);
printk(KERN_ERR "Could not get GPMC register memory\n");
BUG();
dev_err(&pdev->dev, "error: request memory / ioremap\n");
return -EADDRNOTAVAIL;
}
clk_enable(gpmc_l3_clk);
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
if (res == NULL)
dev_warn(&pdev->dev, "Failed to get resource: irq\n");
else
gpmc_irq = res->start;
gpmc_l3_clk = clk_get(&pdev->dev, "fck");
if (IS_ERR(gpmc_l3_clk)) {
dev_err(&pdev->dev, "error: clk_get\n");
gpmc_irq = 0;
return PTR_ERR(gpmc_l3_clk);
}
clk_prepare_enable(gpmc_l3_clk);
gpmc_dev = &pdev->dev;
l = gpmc_read_reg(GPMC_REVISION);
printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
/* Set smart idle mode and automatic L3 clock gating */
l = gpmc_read_reg(GPMC_SYSCONFIG);
l &= 0x03 << 3;
l |= (0x02 << 3) | (1 << 0);
gpmc_write_reg(GPMC_SYSCONFIG, l);
if (GPMC_REVISION_MAJOR(l) > 0x4)
gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
GPMC_REVISION_MINOR(l));
gpmc_mem_init();
ret = gpmc_setup_irq(gpmc_irq);
if (ret)
pr_err("gpmc: irq-%d could not claim: err %d\n",
gpmc_irq, ret);
return ret;
if (IS_ERR_VALUE(gpmc_setup_irq()))
dev_warn(gpmc_dev, "gpmc_setup_irq failed\n");
return 0;
}
static __exit int gpmc_remove(struct platform_device *pdev)
{
gpmc_free_irq();
gpmc_mem_exit();
gpmc_dev = NULL;
return 0;
}
static struct platform_driver gpmc_driver = {
.probe = gpmc_probe,
.remove = __devexit_p(gpmc_remove),
.driver = {
.name = DEVICE_NAME,
.owner = THIS_MODULE,
},
};
static __init int gpmc_init(void)
{
return platform_driver_register(&gpmc_driver);
}
static __exit void gpmc_exit(void)
{
platform_driver_unregister(&gpmc_driver);
}
postcore_initcall(gpmc_init);
module_exit(gpmc_exit);
static int __init omap_gpmc_init(void)
{
struct omap_hwmod *oh;
struct platform_device *pdev;
char *oh_name = "gpmc";
oh = omap_hwmod_lookup(oh_name);
if (!oh) {
pr_err("Could not look up %s\n", oh_name);
return -ENODEV;
}
pdev = omap_device_build(DEVICE_NAME, -1, oh, NULL, 0, NULL, 0, 0);
WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
}
postcore_initcall(omap_gpmc_init);
static irqreturn_t gpmc_handle_irq(int irq, void *dev)
{

138
arch/arm/mach-omap2/omap_hwmod.c
View File

@ -679,16 +679,25 @@ static int _init_main_clk(struct omap_hwmod *oh)
if (!oh->main_clk)
return 0;
oh->_clk = omap_clk_get_by_name(oh->main_clk);
if (!oh->_clk) {
oh->_clk = clk_get(NULL, oh->main_clk);
if (IS_ERR(oh->_clk)) {
pr_warning("omap_hwmod: %s: cannot clk_get main_clk %s\n",
oh->name, oh->main_clk);
return -EINVAL;
}
/*
* HACK: This needs a re-visit once clk_prepare() is implemented
* to do something meaningful. Today its just a no-op.
* If clk_prepare() is used at some point to do things like
* voltage scaling etc, then this would have to be moved to
* some point where subsystems like i2c and pmic become
* available.
*/
clk_prepare(oh->_clk);
if (!oh->_clk->clkdm)
pr_warning("omap_hwmod: %s: missing clockdomain for %s.\n",
oh->main_clk, oh->_clk->name);
pr_debug("omap_hwmod: %s: missing clockdomain for %s.\n",
oh->name, oh->main_clk);
return ret;
}
@ -715,13 +724,22 @@ static int _init_interface_clks(struct omap_hwmod *oh)
if (!os->clk)
continue;
c = omap_clk_get_by_name(os->clk);
if (!c) {
c = clk_get(NULL, os->clk);
if (IS_ERR(c)) {
pr_warning("omap_hwmod: %s: cannot clk_get interface_clk %s\n",
oh->name, os->clk);
ret = -EINVAL;
}
os->_clk = c;
/*
* HACK: This needs a re-visit once clk_prepare() is implemented
* to do something meaningful. Today its just a no-op.
* If clk_prepare() is used at some point to do things like
* voltage scaling etc, then this would have to be moved to
* some point where subsystems like i2c and pmic become
* available.
*/
clk_prepare(os->_clk);
}
return ret;
@ -742,13 +760,22 @@ static int _init_opt_clks(struct omap_hwmod *oh)
int ret = 0;
for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) {
c = omap_clk_get_by_name(oc->clk);
if (!c) {
c = clk_get(NULL, oc->clk);
if (IS_ERR(c)) {
pr_warning("omap_hwmod: %s: cannot clk_get opt_clk %s\n",
oh->name, oc->clk);
ret = -EINVAL;
}
oc->_clk = c;
/*
* HACK: This needs a re-visit once clk_prepare() is implemented
* to do something meaningful. Today its just a no-op.
* If clk_prepare() is used at some point to do things like
* voltage scaling etc, then this would have to be moved to
* some point where subsystems like i2c and pmic become
* available.
*/
clk_prepare(oc->_clk);
}
return ret;
@ -827,7 +854,7 @@ static void _enable_optional_clocks(struct omap_hwmod *oh)
for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
if (oc->_clk) {
pr_debug("omap_hwmod: enable %s:%s\n", oc->role,
oc->_clk->name);
__clk_get_name(oc->_clk));
clk_enable(oc->_clk);
}
}
@ -842,7 +869,7 @@ static void _disable_optional_clocks(struct omap_hwmod *oh)
for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
if (oc->_clk) {
pr_debug("omap_hwmod: disable %s:%s\n", oc->role,
oc->_clk->name);
__clk_get_name(oc->_clk));
clk_disable(oc->_clk);
}
}
@ -900,10 +927,10 @@ static void _am33xx_enable_module(struct omap_hwmod *oh)
*/
static int _omap4_wait_target_disable(struct omap_hwmod *oh)
{
if (!oh || !oh->clkdm)
if (!oh)
return -EINVAL;
if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
if (oh->_int_flags & _HWMOD_NO_MPU_PORT || !oh->clkdm)
return 0;
if (oh->flags & HWMOD_NO_IDLEST)
@ -1427,8 +1454,10 @@ static struct omap_hwmod *_lookup(const char *name)
*/
static int _init_clkdm(struct omap_hwmod *oh)
{
if (!oh->clkdm_name)
if (!oh->clkdm_name) {
pr_debug("omap_hwmod: %s: missing clockdomain\n", oh->name);
return 0;
}
oh->clkdm = clkdm_lookup(oh->clkdm_name);
if (!oh->clkdm) {
@ -1556,6 +1585,7 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
{
struct omap_hwmod_rst_info ohri;
int ret = -EINVAL;
int hwsup = 0;
if (!oh)
return -EINVAL;
@ -1567,10 +1597,46 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
if (IS_ERR_VALUE(ret))
return ret;
if (oh->clkdm) {
/*
* A clockdomain must be in SW_SUP otherwise reset
* might not be completed. The clockdomain can be set
* in HW_AUTO only when the module become ready.
*/
hwsup = clkdm_in_hwsup(oh->clkdm);
ret = clkdm_hwmod_enable(oh->clkdm, oh);
if (ret) {
WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n",
oh->name, oh->clkdm->name, ret);
return ret;
}
}
_enable_clocks(oh);
if (soc_ops.enable_module)
soc_ops.enable_module(oh);
ret = soc_ops.deassert_hardreset(oh, &ohri);
if (soc_ops.disable_module)
soc_ops.disable_module(oh);
_disable_clocks(oh);
if (ret == -EBUSY)
pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name);
if (!ret) {
/*
* Set the clockdomain to HW_AUTO, assuming that the
* previous state was HW_AUTO.
*/
if (oh->clkdm && hwsup)
clkdm_allow_idle(oh->clkdm);
} else {
if (oh->clkdm)
clkdm_hwmod_disable(oh->clkdm, oh);
}
return ret;
}
@ -1605,25 +1671,28 @@ static int _read_hardreset(struct omap_hwmod *oh, const char *name)
}
/**
* _are_any_hardreset_lines_asserted - return true if part of @oh is hard-reset
* _are_all_hardreset_lines_asserted - return true if the @oh is hard-reset
* @oh: struct omap_hwmod *
*
* If any hardreset line associated with @oh is asserted, then return true.
* Otherwise, if @oh has no hardreset lines associated with it, or if
* no hardreset lines associated with @oh are asserted, then return false.
* If all hardreset lines associated with @oh are asserted, then return true.
* Otherwise, if part of @oh is out hardreset or if no hardreset lines
* associated with @oh are asserted, then return false.
* This function is used to avoid executing some parts of the IP block
* enable/disable sequence if a hardreset line is set.
* enable/disable sequence if its hardreset line is set.
*/
static bool _are_any_hardreset_lines_asserted(struct omap_hwmod *oh)
static bool _are_all_hardreset_lines_asserted(struct omap_hwmod *oh)
{
int i;
int i, rst_cnt = 0;
if (oh->rst_lines_cnt == 0)
return false;
for (i = 0; i < oh->rst_lines_cnt; i++)
if (_read_hardreset(oh, oh->rst_lines[i].name) > 0)
return true;
rst_cnt++;
if (oh->rst_lines_cnt == rst_cnt)
return true;
return false;
}
@ -1642,6 +1711,13 @@ static int _omap4_disable_module(struct omap_hwmod *oh)
if (!oh->clkdm || !oh->prcm.omap4.modulemode)
return -EINVAL;
/*
* Since integration code might still be doing something, only
* disable if all lines are under hardreset.
*/
if (!_are_all_hardreset_lines_asserted(oh))
return 0;
pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__);
omap4_cminst_module_disable(oh->clkdm->prcm_partition,
@ -1649,9 +1725,6 @@ static int _omap4_disable_module(struct omap_hwmod *oh)
oh->clkdm->clkdm_offs,
oh->prcm.omap4.clkctrl_offs);
if (_are_any_hardreset_lines_asserted(oh))
return 0;
v = _omap4_wait_target_disable(oh);
if (v)
pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
@ -1679,7 +1752,7 @@ static int _am33xx_disable_module(struct omap_hwmod *oh)
am33xx_cm_module_disable(oh->clkdm->cm_inst, oh->clkdm->clkdm_offs,
oh->prcm.omap4.clkctrl_offs);
if (_are_any_hardreset_lines_asserted(oh))
if (_are_all_hardreset_lines_asserted(oh))
return 0;
v = _am33xx_wait_target_disable(oh);
@ -1907,7 +1980,7 @@ static int _enable(struct omap_hwmod *oh)
}
/*
* If an IP block contains HW reset lines and any of them are
* If an IP block contains HW reset lines and all of them are
* asserted, we let integration code associated with that
* block handle the enable. We've received very little
* information on what those driver authors need, and until
@ -1915,7 +1988,7 @@ static int _enable(struct omap_hwmod *oh)
* posted to the public lists, this is probably the best we
* can do.
*/
if (_are_any_hardreset_lines_asserted(oh))
if (_are_all_hardreset_lines_asserted(oh))
return 0;
/* Mux pins for device runtime if populated */
@ -1934,7 +2007,8 @@ static int _enable(struct omap_hwmod *oh)
* completely the module. The clockdomain can be set
* in HW_AUTO only when the module become ready.
*/
hwsup = clkdm_in_hwsup(oh->clkdm);
hwsup = clkdm_in_hwsup(oh->clkdm) &&
!clkdm_missing_idle_reporting(oh->clkdm);
r = clkdm_hwmod_enable(oh->clkdm, oh);
if (r) {
WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n",
@ -1996,7 +2070,7 @@ static int _idle(struct omap_hwmod *oh)
return -EINVAL;
}
if (_are_any_hardreset_lines_asserted(oh))
if (_are_all_hardreset_lines_asserted(oh))
return 0;
if (oh->class->sysc)
@ -2084,7 +2158,7 @@ static int _shutdown(struct omap_hwmod *oh)
return -EINVAL;
}
if (_are_any_hardreset_lines_asserted(oh))
if (_are_all_hardreset_lines_asserted(oh))
return 0;
pr_debug("omap_hwmod: %s: disabling\n", oh->name);
@ -2608,10 +2682,10 @@ static int _omap2_wait_target_ready(struct omap_hwmod *oh)
*/
static int _omap4_wait_target_ready(struct omap_hwmod *oh)
{
if (!oh || !oh->clkdm)
if (!oh)
return -EINVAL;
if (oh->flags & HWMOD_NO_IDLEST)
if (oh->flags & HWMOD_NO_IDLEST || !oh->clkdm)
return 0;
if (!_find_mpu_rt_port(oh))

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