arm64: dts: add imx8qxp gpmi-nand dts
add gpmi-nand dts for nand support on imx8qxp val Signed-off-by: Han Xu <han.xu@nxp.com>5.4-rM2-2.2.x-imx-squashed
parent
bb2b112553
commit
5e11a3cf27
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@ -54,5 +54,5 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb imx8qxp-mek-dsp.dtb imx8qxp-mek-ov5640
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imx8qxp-mek-rpmsg.dtb imx8qxp-mek-a0.dtb imx8qxp-lpddr4-val-a0.dtb \
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imx8qxp-mek-rpmsg.dtb imx8qxp-mek-a0.dtb imx8qxp-lpddr4-val-a0.dtb \
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imx8qxp-lpddr4-val.dtb imx8qxp-lpddr4-val-mqs.dtb imx8qxp-ddr3l-val.dtb \
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imx8qxp-lpddr4-val.dtb imx8qxp-lpddr4-val-mqs.dtb imx8qxp-ddr3l-val.dtb \
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imx8qxp-lpddr4-val-lpspi.dtb imx8qxp-lpddr4-val-lpspi-slave.dtb \
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imx8qxp-lpddr4-val-lpspi.dtb imx8qxp-lpddr4-val-lpspi-slave.dtb \
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imx8qxp-lpddr4-val-spdif.dtb imx8dxp-lpddr4-val.dtb imx8qxp-17x17-val.dtb \
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imx8qxp-lpddr4-val-spdif.dtb imx8qxp-lpddr4-val-gpmi-nand.dtb imx8dxp-lpddr4-val.dtb \
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imx8dx-lpddr4-val.dtb imx8dx-17x17-val.dtb
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imx8qxp-17x17-val.dtb imx8dx-lpddr4-val.dtb imx8dx-17x17-val.dtb
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@ -33,6 +33,13 @@ conn_subsys: bus@5b000000 {
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clock-output-names = "conn_ipg_clk";
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clock-output-names = "conn_ipg_clk";
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};
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};
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conn_bch_clk: clock-conn-bch {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <400000000>;
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clock-output-names = "conn_bch_clk";
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};
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usbotg1: usb@5b0d0000 {
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usbotg1: usb@5b0d0000 {
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compatible = "fsl,imx8qm-usb", "fsl,imx7ulp-usb",
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compatible = "fsl,imx8qm-usb", "fsl,imx7ulp-usb",
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"fsl,imx27-usb";
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"fsl,imx27-usb";
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@ -293,4 +300,67 @@ conn_subsys: bus@5b000000 {
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"usb3_aclk";
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"usb3_aclk";
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power-domains = <&pd IMX_SC_R_USB_2_PHY>;
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power-domains = <&pd IMX_SC_R_USB_2_PHY>;
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};
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};
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rawnand_0_lpcg: clock-controller@5b290000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5b290000 0x4>;
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#clock-cells = <1>;
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clocks = <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_PER>,
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<&clk IMX_SC_R_NAND IMX_SC_PM_CLK_MST_BUS>,
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<&conn_axi_clk>,
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<&conn_axi_clk>;
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bit-offset = <0 4 16 20>;
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clock-output-names = "bch_clk",
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"gpmi_clk",
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"gpmi_apb_clk",
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"bch_apb_clk";
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power-domains = <&pd IMX_SC_R_NAND>;
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};
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rawnand_4_lpcg: clock-controller@5b290004 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5b290004 0x10000>;
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#clock-cells = <1>;
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clocks = <&conn_axi_clk>;
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bit-offset = <16>;
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clock-output-names = "apbhdma_hclk";
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power-domains = <&pd IMX_SC_R_NAND>;
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};
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dma_apbh: dma-apbh@5b810000 {
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compatible = "fsl,imx28-dma-apbh";
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reg = <0x5b810000 0x2000>;
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interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
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#dma-cells = <1>;
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dma-channels = <4>;
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clocks = <&rawnand_4_lpcg 0>;
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clock-names = "apbhdma_hclk";
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power-domains = <&pd IMX_SC_R_NAND>;
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};
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gpmi: gpmi-nand@5b812000{
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compatible = "fsl,imx8qxp-gpmi-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x5b812000 0x2000>, <0x5b814000 0x2000>;
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reg-names = "gpmi-nand", "bch";
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interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "bch";
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clocks = <&rawnand_0_lpcg 1>,
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<&rawnand_0_lpcg 2>,
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<&rawnand_0_lpcg 0>,
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<&rawnand_0_lpcg 3>;
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clock-names = "gpmi_clk", "gpmi_apb_clk",
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"bch_clk", "bch_apb_clk";
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dmas = <&dma_apbh 0>;
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dma-names = "rx-tx";
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power-domains = <&pd IMX_SC_R_NAND>;
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assigned-clocks = <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_MST_BUS>;
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assigned-clock-rates = <50000000>;
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status = "disabled";
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};
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};
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};
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@ -0,0 +1,50 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2017 NXP
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*/
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#include "imx8qxp-lpddr4-val.dts"
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&iomuxc {
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pinctrl_gpmi_nand_1: gpmi-nand-1 {
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fsl,pins = <
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IMX8QXP_EMMC0_CLK_CONN_NAND_READY_B 0x0e00004c
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IMX8QXP_EMMC0_DATA0_CONN_NAND_DATA00 0x0e00004c
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IMX8QXP_EMMC0_DATA1_CONN_NAND_DATA01 0x0e00004c
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IMX8QXP_EMMC0_DATA2_CONN_NAND_DATA02 0x0e00004c
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IMX8QXP_EMMC0_DATA3_CONN_NAND_DATA03 0x0e00004c
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IMX8QXP_EMMC0_DATA4_CONN_NAND_DATA04 0x0e00004c
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IMX8QXP_EMMC0_DATA5_CONN_NAND_DATA05 0x0e00004c
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IMX8QXP_EMMC0_DATA6_CONN_NAND_DATA06 0x0e00004c
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IMX8QXP_EMMC0_DATA7_CONN_NAND_DATA07 0x0e00004c
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IMX8QXP_EMMC0_STROBE_CONN_NAND_CLE 0x0e00004c
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IMX8QXP_EMMC0_RESET_B_CONN_NAND_WP_B 0x0e00004c
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IMX8QXP_USDHC1_DATA0_CONN_NAND_CE1_B 0x0e00004c
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IMX8QXP_USDHC1_DATA2_CONN_NAND_WE_B 0x0e00004c
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IMX8QXP_USDHC1_DATA3_CONN_NAND_ALE 0x0e00004c
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IMX8QXP_USDHC1_CMD_CONN_NAND_CE0_B 0x0e00004c
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/* i.MX8QXP NAND use nand_re_dqs_pins */
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IMX8QXP_USDHC1_CD_B_CONN_NAND_DQS 0x0e00004c
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IMX8QXP_USDHC1_VSELECT_CONN_NAND_RE_B 0x0e00004c
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>;
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};
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};
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&gpmi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpmi_nand_1>;
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status = "okay";
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nand-on-flash-bbt;
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};
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/* Disabled the usdhc1/usdhc2 since pin conflict */
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&usdhc1 {
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status = "disabled";
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};
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&usdhc2 {
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status = "disabled";
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};
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