Merge branch 'soc-r8a7778' into boards-bockw-base
This commit is contained in:
Simon Horman
commit
5e3780ba6d
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@ -58,11 +58,13 @@ static struct clk *main_clks[] = {
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};
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enum {
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MSTP114,
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MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
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MSTP016, MSTP015,
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MSTP_NR };
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static struct clk mstp_clks[MSTP_NR] = {
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[MSTP114] = SH_CLK_MSTP32(&clkp, MSTPCR1, 14, 0), /* Ether */
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[MSTP026] = SH_CLK_MSTP32(&clkp, MSTPCR0, 26, 0), /* SCIF0 */
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[MSTP025] = SH_CLK_MSTP32(&clkp, MSTPCR0, 25, 0), /* SCIF1 */
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[MSTP024] = SH_CLK_MSTP32(&clkp, MSTPCR0, 24, 0), /* SCIF2 */
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@ -75,6 +77,7 @@ static struct clk mstp_clks[MSTP_NR] = {
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static struct clk_lookup lookups[] = {
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/* MSTP32 clocks */
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CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP114]), /* Ether */
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CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
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CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
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CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */
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@ -18,11 +18,15 @@
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#ifndef __ASM_R8A7778_H__
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#define __ASM_R8A7778_H__
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#include <linux/sh_eth.h>
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extern void r8a7778_add_standard_devices(void);
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extern void r8a7778_add_standard_devices_dt(void);
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extern void r8a7778_add_ether_device(struct sh_eth_plat_data *pdata);
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extern void r8a7778_init_delay(void);
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extern void r8a7778_init_irq(void);
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extern void r8a7778_init_irq_dt(void);
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extern void r8a7778_clock_init(void);
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extern void r8a7778_init_irq_extpin(int irlm);
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#endif /* __ASM_R8A7778_H__ */
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@ -3,6 +3,7 @@
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*
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* Copyright (C) 2013 Renesas Solutions Corp.
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* Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
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* Copyright (C) 2013 Cogent Embedded, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -23,6 +24,7 @@
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#include <linux/irqchip/arm-gic.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/platform_data/irq-renesas-intc-irqpin.h>
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#include <linux/platform_device.h>
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#include <linux/irqchip.h>
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#include <linux/serial_sci.h>
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@ -78,22 +80,20 @@ static struct sh_timer_config sh_tmu1_platform_data = {
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.clocksource_rating = 200,
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};
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#define PLATFORM_INFO(n, i) \
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{ \
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.parent = &platform_bus, \
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.name = #n, \
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.id = i, \
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.res = n ## i ## _resources, \
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.num_res = ARRAY_SIZE(n ## i ##_resources), \
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.data = &n ## i ##_platform_data, \
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.size_data = sizeof(n ## i ## _platform_data), \
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}
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struct platform_device_info platform_devinfo[] = {
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PLATFORM_INFO(sh_tmu, 0),
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PLATFORM_INFO(sh_tmu, 1),
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/* Ether */
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static struct resource ether_resources[] = {
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DEFINE_RES_MEM(0xfde00000, 0x400),
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DEFINE_RES_IRQ(gic_iid(0x89)),
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};
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#define r8a7778_register_tmu(idx) \
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platform_device_register_resndata( \
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&platform_bus, "sh_tmu", idx, \
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sh_tmu##idx##_resources, \
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ARRAY_SIZE(sh_tmu##idx##_resources), \
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&sh_tmu##idx##_platform_data, \
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sizeof(sh_tmu##idx##_platform_data))
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void __init r8a7778_add_standard_devices(void)
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{
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int i;
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@ -114,8 +114,59 @@ void __init r8a7778_add_standard_devices(void)
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&scif_platform_data[i],
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sizeof(struct plat_sci_port));
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for (i = 0; i < ARRAY_SIZE(platform_devinfo); i++)
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platform_device_register_full(&platform_devinfo[i]);
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r8a7778_register_tmu(0);
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r8a7778_register_tmu(1);
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}
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void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata)
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{
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platform_device_register_resndata(&platform_bus, "sh_eth", -1,
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ether_resources,
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ARRAY_SIZE(ether_resources),
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pdata, sizeof(*pdata));
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}
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static struct renesas_intc_irqpin_config irqpin_platform_data = {
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.irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
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.sense_bitfield_width = 2,
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};
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static struct resource irqpin_resources[] = {
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DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
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DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
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DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
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DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */
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DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */
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DEFINE_RES_IRQ(gic_iid(0x3b)), /* IRQ0 */
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DEFINE_RES_IRQ(gic_iid(0x3c)), /* IRQ1 */
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DEFINE_RES_IRQ(gic_iid(0x3d)), /* IRQ2 */
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DEFINE_RES_IRQ(gic_iid(0x3e)), /* IRQ3 */
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};
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void __init r8a7778_init_irq_extpin(int irlm)
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{
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void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
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unsigned long tmp;
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if (!icr0) {
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pr_warn("r8a7778: unable to setup external irq pin mode\n");
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return;
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}
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tmp = ioread32(icr0);
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if (irlm)
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tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */
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else
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tmp &= ~(1 << 23); /* IRL mode - not supported */
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tmp |= (1 << 21); /* LVLMODE = 1 */
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iowrite32(tmp, icr0);
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iounmap(icr0);
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if (irlm)
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platform_device_register_resndata(
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&platform_bus, "renesas_intc_irqpin", -1,
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irqpin_resources, ARRAY_SIZE(irqpin_resources),
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&irqpin_platform_data, sizeof(irqpin_platform_data));
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}
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#define INT2SMSKCR0 0x82288 /* 0xfe782288 */
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