arm64: capabilities: Clean up midr range helpers
We are about to introduce generic MIDR range helpers. Clean up the existing helpers in erratum handling, preparing them to use generic version. Cc: Will Deacon <will.deacon@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Dave Martin <dave.martin@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>hifive-unleashed-5.1
Suzuki K Poulose
Will Deacon
parent
830dcc9f9a
commit
5e7951ce19
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@ -237,23 +237,38 @@ qcom_enable_link_stack_sanitization(const struct arm64_cpu_capabilities *entry)
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}
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#endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */
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#define MIDR_RANGE(model, min, max) \
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.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
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.matches = is_affected_midr_range, \
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.midr_model = model, \
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.midr_range_min = min, \
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.midr_range_max = max
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#define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \
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.matches = is_affected_midr_range, \
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.midr_model = model, \
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.midr_range_min = MIDR_CPU_VAR_REV(v_min, r_min), \
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.midr_range_max = MIDR_CPU_VAR_REV(v_max, r_max)
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#define MIDR_ALL_VERSIONS(model) \
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.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
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.matches = is_affected_midr_range, \
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.midr_model = model, \
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.midr_range_min = 0, \
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#define CAP_MIDR_ALL_VERSIONS(model) \
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.matches = is_affected_midr_range, \
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.midr_model = model, \
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.midr_range_min = MIDR_CPU_VAR_REV(0, 0), \
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.midr_range_max = (MIDR_VARIANT_MASK | MIDR_REVISION_MASK)
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#define MIDR_FIXED(rev, revidr_mask) \
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.fixed_revs = (struct arm64_midr_revidr[]){{ (rev), (revidr_mask) }, {}}
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#define ERRATA_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \
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.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
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CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max)
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/* Errata affecting a range of revisions of given model variant */
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#define ERRATA_MIDR_REV_RANGE(m, var, r_min, r_max) \
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ERRATA_MIDR_RANGE(m, var, r_min, var, r_max)
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/* Errata affecting a single variant/revision of a model */
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#define ERRATA_MIDR_REV(model, var, rev) \
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ERRATA_MIDR_RANGE(model, var, rev, var, rev)
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/* Errata affecting all variants/revisions of a given a model */
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#define ERRATA_MIDR_ALL_VERSIONS(model) \
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.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
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CAP_MIDR_ALL_VERSIONS(model)
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const struct arm64_cpu_capabilities arm64_errata[] = {
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#if defined(CONFIG_ARM64_ERRATUM_826319) || \
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defined(CONFIG_ARM64_ERRATUM_827319) || \
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@ -262,7 +277,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
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/* Cortex-A53 r0p[012] */
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.desc = "ARM errata 826319, 827319, 824069",
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.capability = ARM64_WORKAROUND_CLEAN_CACHE,
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MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x02),
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ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2),
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.cpu_enable = cpu_enable_cache_maint_trap,
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},
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#endif
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@ -271,7 +286,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
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/* Cortex-A53 r0p[01] */
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.desc = "ARM errata 819472",
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.capability = ARM64_WORKAROUND_CLEAN_CACHE,
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MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x01),
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ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1),
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.cpu_enable = cpu_enable_cache_maint_trap,
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},
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#endif
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@ -280,9 +295,9 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
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/* Cortex-A57 r0p0 - r1p2 */
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.desc = "ARM erratum 832075",
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.capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,
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MIDR_RANGE(MIDR_CORTEX_A57,
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MIDR_CPU_VAR_REV(0, 0),
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MIDR_CPU_VAR_REV(1, 2)),
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ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
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0, 0,
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1, 2),
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},
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_834220
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@ -290,9 +305,9 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
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/* Cortex-A57 r0p0 - r1p2 */
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.desc = "ARM erratum 834220",
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.capability = ARM64_WORKAROUND_834220,
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MIDR_RANGE(MIDR_CORTEX_A57,
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MIDR_CPU_VAR_REV(0, 0),
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MIDR_CPU_VAR_REV(1, 2)),
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ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
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0, 0,
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1, 2),
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},
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_843419
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@ -300,7 +315,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
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/* Cortex-A53 r0p[01234] */
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.desc = "ARM erratum 843419",
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.capability = ARM64_WORKAROUND_843419,
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MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x04),
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ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
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MIDR_FIXED(0x4, BIT(8)),
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},
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#endif
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@ -309,7 +324,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
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/* Cortex-A53 r0p[01234] */
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.desc = "ARM erratum 845719",
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.capability = ARM64_WORKAROUND_845719,
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MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x04),
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ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
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},
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#endif
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#ifdef CONFIG_CAVIUM_ERRATUM_23154
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@ -317,7 +332,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
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/* Cavium ThunderX, pass 1.x */
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.desc = "Cavium erratum 23154",
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.capability = ARM64_WORKAROUND_CAVIUM_23154,
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MIDR_RANGE(MIDR_THUNDERX, 0x00, 0x01),
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ERRATA_MIDR_REV_RANGE(MIDR_THUNDERX, 0, 0, 1),
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},
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#endif
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#ifdef CONFIG_CAVIUM_ERRATUM_27456
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@ -325,15 +340,15 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
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/* Cavium ThunderX, T88 pass 1.x - 2.1 */
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.desc = "Cavium erratum 27456",
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.capability = ARM64_WORKAROUND_CAVIUM_27456,
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MIDR_RANGE(MIDR_THUNDERX,
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MIDR_CPU_VAR_REV(0, 0),
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MIDR_CPU_VAR_REV(1, 1)),
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ERRATA_MIDR_RANGE(MIDR_THUNDERX,
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0, 0,
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1, 1),
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},
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{
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/* Cavium ThunderX, T81 pass 1.0 */
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.desc = "Cavium erratum 27456",
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.capability = ARM64_WORKAROUND_CAVIUM_27456,
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MIDR_RANGE(MIDR_THUNDERX_81XX, 0x00, 0x00),
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ERRATA_MIDR_REV(MIDR_THUNDERX_81XX, 0, 0),
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},
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#endif
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#ifdef CONFIG_CAVIUM_ERRATUM_30115
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@ -341,20 +356,21 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
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/* Cavium ThunderX, T88 pass 1.x - 2.2 */
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.desc = "Cavium erratum 30115",
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.capability = ARM64_WORKAROUND_CAVIUM_30115,
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MIDR_RANGE(MIDR_THUNDERX, 0x00,
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(1 << MIDR_VARIANT_SHIFT) | 2),
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ERRATA_MIDR_RANGE(MIDR_THUNDERX,
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0, 0,
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1, 2),
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},
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{
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/* Cavium ThunderX, T81 pass 1.0 - 1.2 */
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.desc = "Cavium erratum 30115",
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.capability = ARM64_WORKAROUND_CAVIUM_30115,
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MIDR_RANGE(MIDR_THUNDERX_81XX, 0x00, 0x02),
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ERRATA_MIDR_REV_RANGE(MIDR_THUNDERX_81XX, 0, 0, 2),
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},
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{
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/* Cavium ThunderX, T83 pass 1.0 */
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.desc = "Cavium erratum 30115",
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.capability = ARM64_WORKAROUND_CAVIUM_30115,
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MIDR_RANGE(MIDR_THUNDERX_83XX, 0x00, 0x00),
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ERRATA_MIDR_REV(MIDR_THUNDERX_83XX, 0, 0),
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},
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#endif
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{
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@ -368,9 +384,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
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{
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.desc = "Qualcomm Technologies Falkor erratum 1003",
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.capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
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MIDR_RANGE(MIDR_QCOM_FALKOR_V1,
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MIDR_CPU_VAR_REV(0, 0),
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MIDR_CPU_VAR_REV(0, 0)),
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ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0),
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},
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{
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.desc = "Qualcomm Technologies Kryo erratum 1003",
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@ -384,9 +398,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
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{
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.desc = "Qualcomm Technologies Falkor erratum 1009",
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.capability = ARM64_WORKAROUND_REPEAT_TLBI,
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MIDR_RANGE(MIDR_QCOM_FALKOR_V1,
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MIDR_CPU_VAR_REV(0, 0),
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MIDR_CPU_VAR_REV(0, 0)),
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ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0),
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},
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_858921
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@ -394,56 +406,56 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
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/* Cortex-A73 all versions */
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.desc = "ARM erratum 858921",
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.capability = ARM64_WORKAROUND_858921,
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
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ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
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},
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#endif
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#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
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{
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.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
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ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
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.cpu_enable = enable_smccc_arch_workaround_1,
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},
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{
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.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
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ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
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.cpu_enable = enable_smccc_arch_workaround_1,
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},
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{
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.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
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ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
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.cpu_enable = enable_smccc_arch_workaround_1,
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},
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{
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.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A75),
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ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A75),
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.cpu_enable = enable_smccc_arch_workaround_1,
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},
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{
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.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
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MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),
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ERRATA_MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),
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.cpu_enable = qcom_enable_link_stack_sanitization,
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},
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{
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.capability = ARM64_HARDEN_BP_POST_GUEST_EXIT,
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MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),
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ERRATA_MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),
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},
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{
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.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
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MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR),
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ERRATA_MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR),
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.cpu_enable = qcom_enable_link_stack_sanitization,
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},
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{
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.capability = ARM64_HARDEN_BP_POST_GUEST_EXIT,
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MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR),
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ERRATA_MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR),
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},
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{
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.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
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MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
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ERRATA_MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
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.cpu_enable = enable_smccc_arch_workaround_1,
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},
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{
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.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
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MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
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ERRATA_MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
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.cpu_enable = enable_smccc_arch_workaround_1,
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},
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#endif
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