spi/bfin_spi: combine duplicate SPI_CTL read/write logic
While combining things, also switch to the proper SPI bit define names. This lets us punt the rarely used SPI defines. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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@ -11,18 +11,6 @@
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#define MIN_SPI_BAUD_VAL 2
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#define SPI_READ 0
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#define SPI_WRITE 1
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#define SPI_CTRL_OFF 0x0
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#define SPI_FLAG_OFF 0x4
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#define SPI_STAT_OFF 0x8
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#define SPI_TXBUFF_OFF 0xc
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#define SPI_RXBUFF_OFF 0x10
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#define SPI_BAUD_OFF 0x14
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#define SPI_SHAW_OFF 0x18
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#define BIT_CTL_ENABLE 0x4000
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#define BIT_CTL_OPENDRAIN 0x2000
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#define BIT_CTL_MASTER 0x1000
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@ -53,62 +41,6 @@
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#define BIT_STU_SENDOVER 0x0001
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#define BIT_STU_RECVFULL 0x0020
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#define CFG_SPI_ENABLE 1
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#define CFG_SPI_DISABLE 0
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#define CFG_SPI_OUTENABLE 1
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#define CFG_SPI_OUTDISABLE 0
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#define CFG_SPI_ACTLOW 1
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#define CFG_SPI_ACTHIGH 0
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#define CFG_SPI_PHASESTART 1
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#define CFG_SPI_PHASEMID 0
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#define CFG_SPI_MASTER 1
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#define CFG_SPI_SLAVE 0
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#define CFG_SPI_SENELAST 0
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#define CFG_SPI_SENDZERO 1
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#define CFG_SPI_RCVFLUSH 1
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#define CFG_SPI_RCVDISCARD 0
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#define CFG_SPI_LSBFIRST 1
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#define CFG_SPI_MSBFIRST 0
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#define CFG_SPI_WORDSIZE16 1
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#define CFG_SPI_WORDSIZE8 0
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#define CFG_SPI_MISOENABLE 1
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#define CFG_SPI_MISODISABLE 0
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#define CFG_SPI_READ 0x00
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#define CFG_SPI_WRITE 0x01
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#define CFG_SPI_DMAREAD 0x02
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#define CFG_SPI_DMAWRITE 0x03
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#define CFG_SPI_CSCLEARALL 0
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#define CFG_SPI_CHIPSEL1 1
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#define CFG_SPI_CHIPSEL2 2
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#define CFG_SPI_CHIPSEL3 3
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#define CFG_SPI_CHIPSEL4 4
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#define CFG_SPI_CHIPSEL5 5
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#define CFG_SPI_CHIPSEL6 6
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#define CFG_SPI_CHIPSEL7 7
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#define CFG_SPI_CS1VALUE 1
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#define CFG_SPI_CS2VALUE 2
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#define CFG_SPI_CS3VALUE 3
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#define CFG_SPI_CS4VALUE 4
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#define CFG_SPI_CS5VALUE 5
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#define CFG_SPI_CS6VALUE 6
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#define CFG_SPI_CS7VALUE 7
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#define CMD_SPI_SET_BAUDRATE 2
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#define CMD_SPI_GET_SYSTEMCLOCK 25
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#define CMD_SPI_SET_WRITECONTINUOUS 26
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#define MAX_CTRL_CS 8 /* cs in spi controller */
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/* device.platform_data for SSP controller devices */
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@ -560,8 +560,7 @@ static void bfin_spi_pump_transfers(unsigned long data)
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struct spi_transfer *previous = NULL;
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struct slave_data *chip = NULL;
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unsigned int bits_per_word;
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u8 width;
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u16 cr, dma_width, dma_config;
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u16 cr, cr_width, dma_width, dma_config;
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u32 tranf_success = 1;
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u8 full_duplex = 0;
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@ -642,22 +641,19 @@ static void bfin_spi_pump_transfers(unsigned long data)
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bits_per_word = transfer->bits_per_word ? : message->spi->bits_per_word;
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if (bits_per_word == 8) {
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drv_data->n_bytes = 1;
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width = CFG_SPI_WORDSIZE8;
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drv_data->len = transfer->len;
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cr_width = 0;
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drv_data->ops = &bfin_transfer_ops_u8;
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} else {
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drv_data->n_bytes = 2;
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width = CFG_SPI_WORDSIZE16;
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drv_data->len = (transfer->len) >> 1;
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cr_width = BIT_CTL_WORDSIZE;
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drv_data->ops = &bfin_transfer_ops_u16;
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}
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cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
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cr |= (width << 8);
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cr = read_CTRL(drv_data) & ~(BIT_CTL_TIMOD | BIT_CTL_WORDSIZE);
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cr |= cr_width;
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write_CTRL(drv_data, cr);
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if (width == CFG_SPI_WORDSIZE16) {
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drv_data->len = (transfer->len) >> 1;
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} else {
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drv_data->len = transfer->len;
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}
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dev_dbg(&drv_data->pdev->dev,
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"transfer: drv_data->ops is %p, chip->ops is %p, u8_ops is %p\n",
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drv_data->ops, chip->ops, &bfin_transfer_ops_u8);
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@ -672,13 +668,12 @@ static void bfin_spi_pump_transfers(unsigned long data)
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write_BAUD(drv_data, chip->baud);
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write_STAT(drv_data, BIT_STAT_CLR);
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cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
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if (drv_data->cs_change)
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bfin_spi_cs_active(drv_data, chip);
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dev_dbg(&drv_data->pdev->dev,
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"now pumping a transfer: width is %d, len is %d\n",
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width, transfer->len);
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cr_width, transfer->len);
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/*
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* Try to map dma buffer and do a dma transfer. If successful use,
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@ -697,7 +692,7 @@ static void bfin_spi_pump_transfers(unsigned long data)
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/* config dma channel */
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dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
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set_dma_x_count(drv_data->dma_channel, drv_data->len);
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if (width == CFG_SPI_WORDSIZE16) {
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if (cr_width == BIT_CTL_WORDSIZE) {
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set_dma_x_modify(drv_data->dma_channel, 2);
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dma_width = WDSIZE_16;
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} else {
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@ -786,10 +781,16 @@ static void bfin_spi_pump_transfers(unsigned long data)
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return;
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}
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/*
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* We always use SPI_WRITE mode (transfer starts with TDBR write).
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* SPI_READ mode (transfer starts with RDBR read) seems to have
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* problems with setting up the output value in TDBR prior to the
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* start of the transfer.
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*/
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write_CTRL(drv_data, cr | BIT_CTL_TXMOD);
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if (chip->pio_interrupt) {
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/* use write mode. spi irq should have been disabled */
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cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
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write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
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/* SPI irq should have been disabled by now */
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/* discard old RX data and clear RXS */
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bfin_spi_dummy_read(drv_data);
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@ -813,11 +814,6 @@ static void bfin_spi_pump_transfers(unsigned long data)
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/* IO mode */
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dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
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/* we always use SPI_WRITE mode. SPI_READ mode
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seems to have problems with setting up the
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output value in TDBR prior to the transfer. */
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write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
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if (full_duplex) {
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/* full duplex mode */
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BUG_ON((drv_data->tx_end - drv_data->tx) !=
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