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amdgpu and panel/misc fixes. 

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Merge tag 'drm-next-2018-08-24' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie:
 "Just a couple of fixes"

  One MAINTAINERS address change, two panels fixes, and set of amdgpu
  fixes (build fixes, display fixes and some others)"

* tag 'drm-next-2018-08-24' of git://anongit.freedesktop.org/drm/drm:
  drm/edid: Add 6 bpc quirk for SDC panel in Lenovo B50-80
  drm/amd/display: Don't build DCN1 when kcov is enabled
  Revert "drm/amdgpu/display: Replace CONFIG_DRM_AMD_DC_DCN1_0 with CONFIG_X86"
  drm/amdgpu/display: disable eDP fast boot optimization on DCE8
  drm/amdgpu: fix amdgpu_amdkfd_remove_eviction_fence v3
  drm/amdgpu: fix incorrect use of drm_file->pid
  drm/amdgpu: fix incorrect use of fcheck
  drm/powerplay: enable dpm under pass-through
  drm/amdgpu: access register without KIQ
  drm/amdgpu: set correct base for THM/NBIF/MP1 IP
  drm/amd/display: fix dentist did ranges
  drm/amd/display: make dp_ss_off optional
  drm/amd/display: fix dp_ss_control vbios flag parsing
  drm/amd/display: Do not retain link settings
  MAINTAINERS: drm-misc: Change seanpaul's email address
  drm/panel: simple: tv123wam: Add unprepare delay
hifive-unleashed-5.1
Linus Torvalds 2018-08-24 09:22:54 -07:00
parent 019cddc88f 3e20e97c2d
commit 5e8704ac1c
35 changed files with 166 additions and 147 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
MAINTAINERS
View File

@ -4752,7 +4752,7 @@ F: include/linux/vga*
DRM DRIVERS AND MISC GPU PATCHES DRM DRIVERS AND MISC GPU PATCHES
M: Gustavo Padovan <gustavo@padovan.org> M: Gustavo Padovan <gustavo@padovan.org>
M: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> M: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
M: Sean Paul <seanpaul@chromium.org> M: Sean Paul <sean@poorly.run>
W: https://01.org/linuxgraphics/gfx-docs/maintainer-tools/drm-misc.html W: https://01.org/linuxgraphics/gfx-docs/maintainer-tools/drm-misc.html
S: Maintained S: Maintained
T: git git://anongit.freedesktop.org/drm/drm-misc T: git git://anongit.freedesktop.org/drm/drm-misc

113
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
View File

@ -206,11 +206,9 @@ static int amdgpu_amdkfd_remove_eviction_fence(struct amdgpu_bo *bo,
struct amdgpu_amdkfd_fence ***ef_list, struct amdgpu_amdkfd_fence ***ef_list,
unsigned int *ef_count) unsigned int *ef_count)
{ {
struct reservation_object_list *fobj; struct reservation_object *resv = bo->tbo.resv;
struct reservation_object *resv; struct reservation_object_list *old, *new;
unsigned int i = 0, j = 0, k = 0, shared_count; unsigned int i, j, k;
unsigned int count = 0;
struct amdgpu_amdkfd_fence **fence_list;
if (!ef && !ef_list) if (!ef && !ef_list)
return -EINVAL; return -EINVAL;
@ -220,76 +218,67 @@ static int amdgpu_amdkfd_remove_eviction_fence(struct amdgpu_bo *bo,
*ef_count = 0; *ef_count = 0;
} }
resv = bo->tbo.resv; old = reservation_object_get_list(resv);
fobj = reservation_object_get_list(resv); if (!old)
if (!fobj)
return 0; return 0;
preempt_disable(); new = kmalloc(offsetof(typeof(*new), shared[old->shared_max]),
write_seqcount_begin(&resv->seq); GFP_KERNEL);
if (!new)
/* Go through all the shared fences in the resevation object. If
* ef is specified and it exists in the list, remove it and reduce the
* count. If ef is not specified, then get the count of eviction fences
* present.
*/
shared_count = fobj->shared_count;
for (i = 0; i < shared_count; ++i) {
struct dma_fence *f;
f = rcu_dereference_protected(fobj->shared[i],
reservation_object_held(resv));
if (ef) {
if (f->context == ef->base.context) {
dma_fence_put(f);
fobj->shared_count--;
} else {
RCU_INIT_POINTER(fobj->shared[j++], f);
}
} else if (to_amdgpu_amdkfd_fence(f))
count++;
}
write_seqcount_end(&resv->seq);
preempt_enable();
if (ef || !count)
return 0;
/* Alloc memory for count number of eviction fence pointers. Fill the
* ef_list array and ef_count
*/
fence_list = kcalloc(count, sizeof(struct amdgpu_amdkfd_fence *),
GFP_KERNEL);
if (!fence_list)
return -ENOMEM; return -ENOMEM;
preempt_disable(); /* Go through all the shared fences in the resevation object and sort
write_seqcount_begin(&resv->seq); * the interesting ones to the end of the list.
*/
j = 0; for (i = 0, j = old->shared_count, k = 0; i < old->shared_count; ++i) {
for (i = 0; i < shared_count; ++i) {
struct dma_fence *f; struct dma_fence *f;
struct amdgpu_amdkfd_fence *efence;
f = rcu_dereference_protected(fobj->shared[i], f = rcu_dereference_protected(old->shared[i],
reservation_object_held(resv)); reservation_object_held(resv));
efence = to_amdgpu_amdkfd_fence(f); if ((ef && f->context == ef->base.context) ||
if (efence) { (!ef && to_amdgpu_amdkfd_fence(f)))
fence_list[k++] = efence; RCU_INIT_POINTER(new->shared[--j], f);
fobj->shared_count--; else
} else { RCU_INIT_POINTER(new->shared[k++], f);
RCU_INIT_POINTER(fobj->shared[j++], f); }
new->shared_max = old->shared_max;
new->shared_count = k;
if (!ef) {
unsigned int count = old->shared_count - j;
/* Alloc memory for count number of eviction fence pointers.
* Fill the ef_list array and ef_count
*/
*ef_list = kcalloc(count, sizeof(**ef_list), GFP_KERNEL);
*ef_count = count;
if (!*ef_list) {
kfree(new);
return -ENOMEM;
} }
} }
/* Install the new fence list, seqcount provides the barriers */
preempt_disable();
write_seqcount_begin(&resv->seq);
RCU_INIT_POINTER(resv->fence, new);
write_seqcount_end(&resv->seq); write_seqcount_end(&resv->seq);
preempt_enable(); preempt_enable();
*ef_list = fence_list; /* Drop the references to the removed fences or move them to ef_list */
*ef_count = k; for (i = j, k = 0; i < old->shared_count; ++i) {
struct dma_fence *f;
f = rcu_dereference_protected(new->shared[i],
reservation_object_held(resv));
if (!ef)
(*ef_list)[k++] = to_amdgpu_amdkfd_fence(f);
else
dma_fence_put(f);
}
kfree_rcu(old, rcu);
return 0; return 0;
} }

2
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
View File

@ -2274,7 +2274,7 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
case CHIP_VEGA10: case CHIP_VEGA10:
case CHIP_VEGA12: case CHIP_VEGA12:
case CHIP_VEGA20: case CHIP_VEGA20:
#ifdef CONFIG_X86 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
case CHIP_RAVEN: case CHIP_RAVEN:
#endif #endif
return amdgpu_dc != 0; return amdgpu_dc != 0;

21
drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c
View File

@ -53,9 +53,8 @@ static int amdgpu_sched_process_priority_override(struct amdgpu_device *adev,
int fd, int fd,
enum drm_sched_priority priority) enum drm_sched_priority priority)
{ {
struct file *filp = fcheck(fd); struct file *filp = fget(fd);
struct drm_file *file; struct drm_file *file;
struct pid *pid;
struct amdgpu_fpriv *fpriv; struct amdgpu_fpriv *fpriv;
struct amdgpu_ctx *ctx; struct amdgpu_ctx *ctx;
uint32_t id; uint32_t id;
@ -63,20 +62,12 @@ static int amdgpu_sched_process_priority_override(struct amdgpu_device *adev,
if (!filp) if (!filp)
return -EINVAL; return -EINVAL;
pid = get_pid(((struct drm_file *)filp->private_data)->pid); file = filp->private_data;
fpriv = file->driver_priv;
idr_for_each_entry(&fpriv->ctx_mgr.ctx_handles, ctx, id)
amdgpu_ctx_priority_override(ctx, priority);
mutex_lock(&adev->ddev->filelist_mutex); fput(filp);
list_for_each_entry(file, &adev->ddev->filelist, lhead) {
if (file->pid != pid)
continue;
fpriv = file->driver_priv;
idr_for_each_entry(&fpriv->ctx_mgr.ctx_handles, ctx, id)
amdgpu_ctx_priority_override(ctx, priority);
}
mutex_unlock(&adev->ddev->filelist_mutex);
put_pid(pid);
return 0; return 0;
} }

3
drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
View File

@ -38,6 +38,7 @@ int vega20_reg_base_init(struct amdgpu_device *adev)
adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i]));
adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i])); adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i]));
adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
@ -46,6 +47,8 @@ int vega20_reg_base_init(struct amdgpu_device *adev)
adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i])); adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i]));
adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(SDMA1_BASE.instance[i])); adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(SDMA1_BASE.instance[i]));
adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i])); adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
adev->reg_offset[NBIF_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
} }
return 0; return 0;
} }

4
drivers/gpu/drm/amd/amdgpu/vi.c
View File

@ -112,8 +112,8 @@ static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg)
u32 r; u32 r;
spin_lock_irqsave(&adev->smc_idx_lock, flags); spin_lock_irqsave(&adev->smc_idx_lock, flags);
WREG32(mmSMC_IND_INDEX_11, (reg)); WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg));
r = RREG32(mmSMC_IND_DATA_11); r = RREG32_NO_KIQ(mmSMC_IND_DATA_11);
spin_unlock_irqrestore(&adev->smc_idx_lock, flags); spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
return r; return r;
} }

6
drivers/gpu/drm/amd/display/Kconfig
View File

@ -4,11 +4,17 @@ menu "Display Engine Configuration"
config DRM_AMD_DC config DRM_AMD_DC
bool "AMD DC - Enable new display engine" bool "AMD DC - Enable new display engine"
default y default y
select DRM_AMD_DC_DCN1_0 if X86 && !(KCOV_INSTRUMENT_ALL && KCOV_ENABLE_COMPARISONS)
help help
Choose this option if you want to use the new display engine Choose this option if you want to use the new display engine
support for AMDGPU. This adds required support for Vega and support for AMDGPU. This adds required support for Vega and
Raven ASICs. Raven ASICs.
config DRM_AMD_DC_DCN1_0
def_bool n
help
RV family support for display engine
config DEBUG_KERNEL_DC config DEBUG_KERNEL_DC
bool "Enable kgdb break in DC" bool "Enable kgdb break in DC"
depends on DRM_AMD_DC depends on DRM_AMD_DC

10
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
View File

@ -58,9 +58,7 @@
#include <drm/drm_fb_helper.h> #include <drm/drm_fb_helper.h>
#include <drm/drm_edid.h> #include <drm/drm_edid.h>
#include "modules/inc/mod_freesync.h" #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
#ifdef CONFIG_X86
#include "ivsrcid/irqsrcs_dcn_1_0.h" #include "ivsrcid/irqsrcs_dcn_1_0.h"
#include "dcn/dcn_1_0_offset.h" #include "dcn/dcn_1_0_offset.h"
@ -1192,7 +1190,7 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev)
return 0; return 0;
} }
#ifdef CONFIG_X86 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
/* Register IRQ sources and initialize IRQ callbacks */ /* Register IRQ sources and initialize IRQ callbacks */
static int dcn10_register_irq_handlers(struct amdgpu_device *adev) static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
{ {
@ -1532,7 +1530,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
goto fail; goto fail;
} }
break; break;
#ifdef CONFIG_X86 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
case CHIP_RAVEN: case CHIP_RAVEN:
if (dcn10_register_irq_handlers(dm->adev)) { if (dcn10_register_irq_handlers(dm->adev)) {
DRM_ERROR("DM: Failed to initialize IRQ\n"); DRM_ERROR("DM: Failed to initialize IRQ\n");
@ -1716,7 +1714,7 @@ static int dm_early_init(void *handle)
adev->mode_info.num_dig = 6; adev->mode_info.num_dig = 6;
adev->mode_info.plane_type = dm_plane_type_default; adev->mode_info.plane_type = dm_plane_type_default;
break; break;
#ifdef CONFIG_X86 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
case CHIP_RAVEN: case CHIP_RAVEN:
adev->mode_info.num_crtc = 4; adev->mode_info.num_crtc = 4;
adev->mode_info.num_hpd = 4; adev->mode_info.num_hpd = 4;

2
drivers/gpu/drm/amd/display/dc/Makefile
View File

@ -25,7 +25,7 @@
DC_LIBS = basics bios calcs dce gpio i2caux irq virtual DC_LIBS = basics bios calcs dce gpio i2caux irq virtual
ifdef CONFIG_X86 ifdef CONFIG_DRM_AMD_DC_DCN1_0
DC_LIBS += dcn10 dml DC_LIBS += dcn10 dml
endif endif

2
drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
View File

@ -55,7 +55,7 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
case DCE_VERSION_11_22: case DCE_VERSION_11_22:
*h = dal_cmd_tbl_helper_dce112_get_table2(); *h = dal_cmd_tbl_helper_dce112_get_table2();
return true; return true;
#ifdef CONFIG_X86 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
case DCN_VERSION_1_0: case DCN_VERSION_1_0:
*h = dal_cmd_tbl_helper_dce112_get_table2(); *h = dal_cmd_tbl_helper_dce112_get_table2();
return true; return true;

2
drivers/gpu/drm/amd/display/dc/calcs/Makefile
View File

@ -38,7 +38,7 @@ CFLAGS_dcn_calc_math.o := $(calcs_ccflags) -Wno-tautological-compare
BW_CALCS = dce_calcs.o bw_fixed.o custom_float.o BW_CALCS = dce_calcs.o bw_fixed.o custom_float.o
ifdef CONFIG_X86 ifdef CONFIG_DRM_AMD_DC_DCN1_0
BW_CALCS += dcn_calcs.o dcn_calc_math.o dcn_calc_auto.o BW_CALCS += dcn_calcs.o dcn_calc_math.o dcn_calc_auto.o
endif endif

21
drivers/gpu/drm/amd/display/dc/core/dc.c
View File

@ -52,6 +52,8 @@
#include "dm_helpers.h" #include "dm_helpers.h"
#include "mem_input.h" #include "mem_input.h"
#include "hubp.h" #include "hubp.h"
#include "dc_link_dp.h"
#define DC_LOGGER \ #define DC_LOGGER \
dc->ctx->logger dc->ctx->logger
@ -419,8 +421,17 @@ void dc_link_set_preferred_link_settings(struct dc *dc,
struct dc_link_settings *link_setting, struct dc_link_settings *link_setting,
struct dc_link *link) struct dc_link *link)
{ {
link->preferred_link_setting = *link_setting; struct dc_link_settings store_settings = *link_setting;
dp_retrain_link_dp_test(link, link_setting, false); struct dc_stream_state *link_stream =
link->dc->current_state->res_ctx.pipe_ctx[0].stream;
link->preferred_link_setting = store_settings;
if (link_stream)
decide_link_settings(link_stream, &store_settings);
if ((store_settings.lane_count != LANE_COUNT_UNKNOWN) &&
(store_settings.link_rate != LINK_RATE_UNKNOWN))
dp_retrain_link_dp_test(link, &store_settings, false);
} }
void dc_link_enable_hpd(const struct dc_link *link) void dc_link_enable_hpd(const struct dc_link *link)
@ -476,7 +487,7 @@ static void destruct(struct dc *dc)
kfree(dc->bw_dceip); kfree(dc->bw_dceip);
dc->bw_dceip = NULL; dc->bw_dceip = NULL;
#ifdef CONFIG_X86 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
kfree(dc->dcn_soc); kfree(dc->dcn_soc);
dc->dcn_soc = NULL; dc->dcn_soc = NULL;
@ -492,7 +503,7 @@ static bool construct(struct dc *dc,
struct dc_context *dc_ctx; struct dc_context *dc_ctx;
struct bw_calcs_dceip *dc_dceip; struct bw_calcs_dceip *dc_dceip;
struct bw_calcs_vbios *dc_vbios; struct bw_calcs_vbios *dc_vbios;
#ifdef CONFIG_X86 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
struct dcn_soc_bounding_box *dcn_soc; struct dcn_soc_bounding_box *dcn_soc;
struct dcn_ip_params *dcn_ip; struct dcn_ip_params *dcn_ip;
#endif #endif
@ -514,7 +525,7 @@ static bool construct(struct dc *dc,
} }
dc->bw_vbios = dc_vbios; dc->bw_vbios = dc_vbios;
#ifdef CONFIG_X86 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
dcn_soc = kzalloc(sizeof(*dcn_soc), GFP_KERNEL); dcn_soc = kzalloc(sizeof(*dcn_soc), GFP_KERNEL);
if (!dcn_soc) { if (!dcn_soc) {
dm_error("%s: failed to create dcn_soc\n", __func__); dm_error("%s: failed to create dcn_soc\n", __func__);

2
drivers/gpu/drm/amd/display/dc/core/dc_debug.c
View File

@ -348,7 +348,7 @@ void context_clock_trace(
struct dc *dc, struct dc *dc,
struct dc_state *context) struct dc_state *context)
{ {
#ifdef CONFIG_X86 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
DC_LOGGER_INIT(dc->ctx->logger); DC_LOGGER_INIT(dc->ctx->logger);
CLOCK_TRACE("Current: dispclk_khz:%d max_dppclk_khz:%d dcfclk_khz:%d\n" CLOCK_TRACE("Current: dispclk_khz:%d max_dppclk_khz:%d dcfclk_khz:%d\n"
"dcfclk_deep_sleep_khz:%d fclk_khz:%d socclk_khz:%d\n", "dcfclk_deep_sleep_khz:%d fclk_khz:%d socclk_khz:%d\n",

6
drivers/gpu/drm/amd/display/dc/core/dc_link.c
View File

@ -1039,9 +1039,6 @@ static bool construct(
link->link_id = bios->funcs->get_connector_id(bios, init_params->connector_index); link->link_id = bios->funcs->get_connector_id(bios, init_params->connector_index);
if (dc_ctx->dc_bios->integrated_info)
link->dp_ss_off = !!dc_ctx->dc_bios->integrated_info->dp_ss_control;
if (link->link_id.type != OBJECT_TYPE_CONNECTOR) { if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
dm_error("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n", dm_error("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n",
__func__, init_params->connector_index, __func__, init_params->connector_index,
@ -1049,6 +1046,9 @@ static bool construct(
goto create_fail; goto create_fail;
} }
if (link->dc->res_pool->funcs->link_init)
link->dc->res_pool->funcs->link_init(link);
hpd_gpio = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service); hpd_gpio = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
if (hpd_gpio != NULL) if (hpd_gpio != NULL)

12
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
View File

@ -41,7 +41,7 @@
#include "dce100/dce100_resource.h" #include "dce100/dce100_resource.h"
#include "dce110/dce110_resource.h" #include "dce110/dce110_resource.h"
#include "dce112/dce112_resource.h" #include "dce112/dce112_resource.h"
#ifdef CONFIG_X86 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
#include "dcn10/dcn10_resource.h" #include "dcn10/dcn10_resource.h"
#endif #endif
#include "dce120/dce120_resource.h" #include "dce120/dce120_resource.h"
@ -85,7 +85,7 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
case FAMILY_AI: case FAMILY_AI:
dc_version = DCE_VERSION_12_0; dc_version = DCE_VERSION_12_0;
break; break;
#ifdef CONFIG_X86 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
case FAMILY_RV: case FAMILY_RV:
dc_version = DCN_VERSION_1_0; dc_version = DCN_VERSION_1_0;
break; break;
@ -136,7 +136,7 @@ struct resource_pool *dc_create_resource_pool(
num_virtual_links, dc); num_virtual_links, dc);
break; break;
#ifdef CONFIG_X86 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
case DCN_VERSION_1_0: case DCN_VERSION_1_0:
res_pool = dcn10_create_resource_pool( res_pool = dcn10_create_resource_pool(
num_virtual_links, dc); num_virtual_links, dc);
@ -1251,7 +1251,7 @@ static struct pipe_ctx *acquire_free_pipe_for_stream(
} }
#ifdef CONFIG_X86 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
static int acquire_first_split_pipe( static int acquire_first_split_pipe(
struct resource_context *res_ctx, struct resource_context *res_ctx,
const struct resource_pool *pool, const struct resource_pool *pool,
@ -1322,7 +1322,7 @@ bool dc_add_plane_to_context(
free_pipe = acquire_free_pipe_for_stream(context, pool, stream); free_pipe = acquire_free_pipe_for_stream(context, pool, stream);
#ifdef CONFIG_X86 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
if (!free_pipe) { if (!free_pipe) {
int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream); int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
if (pipe_idx >= 0) if (pipe_idx >= 0)
@ -1920,7 +1920,7 @@ enum dc_status resource_map_pool_resources(
/* acquire new resources */ /* acquire new resources */
pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream); pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream);
#ifdef CONFIG_X86 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
if (pipe_idx < 0) if (pipe_idx < 0)
pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream); pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
#endif #endif

2
drivers/gpu/drm/amd/display/dc/dc.h
View File

@ -294,7 +294,7 @@ struct dc {
/* Inputs into BW and WM calculations. */ /* Inputs into BW and WM calculations. */
struct bw_calcs_dceip *bw_dceip; struct bw_calcs_dceip *bw_dceip;
struct bw_calcs_vbios *bw_vbios; struct bw_calcs_vbios *bw_vbios;
#ifdef CONFIG_X86 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
struct dcn_soc_bounding_box *dcn_soc; struct dcn_soc_bounding_box *dcn_soc;
struct dcn_ip_params *dcn_ip; struct dcn_ip_params *dcn_ip;
struct display_mode_lib dml; struct display_mode_lib dml;

6
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
View File

@ -592,7 +592,7 @@ static uint32_t dce110_get_pix_clk_dividers(
case DCE_VERSION_11_2: case DCE_VERSION_11_2:
case DCE_VERSION_11_22: case DCE_VERSION_11_22:
case DCE_VERSION_12_0: case DCE_VERSION_12_0:
#ifdef CONFIG_X86 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
case DCN_VERSION_1_0: case DCN_VERSION_1_0:
#endif #endif
@ -909,7 +909,7 @@ static bool dce110_program_pix_clk(
struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
struct bp_pixel_clock_parameters bp_pc_params = {0}; struct bp_pixel_clock_parameters bp_pc_params = {0};
#ifdef CONFIG_X86 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
if (IS_FPGA_MAXIMUS_DC(clock_source->ctx->dce_environment)) { if (IS_FPGA_MAXIMUS_DC(clock_source->ctx->dce_environment)) {
unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
unsigned dp_dto_ref_kHz = 700000; unsigned dp_dto_ref_kHz = 700000;
@ -982,7 +982,7 @@ static bool dce110_program_pix_clk(
case DCE_VERSION_11_2: case DCE_VERSION_11_2:
case DCE_VERSION_11_22: case DCE_VERSION_11_22:
case DCE_VERSION_12_0: case DCE_VERSION_12_0:
#ifdef CONFIG_X86 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
case DCN_VERSION_1_0: case DCN_VERSION_1_0:
#endif #endif

2
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
View File

@ -55,7 +55,7 @@
CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\ CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\
CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, mask_sh) CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, mask_sh)
#ifdef CONFIG_X86 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
#define CS_COMMON_REG_LIST_DCN1_0(index, pllid) \ #define CS_COMMON_REG_LIST_DCN1_0(index, pllid) \
SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\

18
drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
View File

@ -30,7 +30,7 @@
#include "bios_parser_interface.h" #include "bios_parser_interface.h"
#include "dc.h" #include "dc.h"
#include "dmcu.h" #include "dmcu.h"
#ifdef CONFIG_X86 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
#include "dcn_calcs.h" #include "dcn_calcs.h"
#endif #endif
#include "core_types.h" #include "core_types.h"
@ -106,7 +106,8 @@ enum dentist_base_divider_id {
DENTIST_BASE_DID_1 = 0x08, DENTIST_BASE_DID_1 = 0x08,
DENTIST_BASE_DID_2 = 0x40, DENTIST_BASE_DID_2 = 0x40,
DENTIST_BASE_DID_3 = 0x60, DENTIST_BASE_DID_3 = 0x60,
DENTIST_MAX_DID = 0x80 DENTIST_BASE_DID_4 = 0x7e,
DENTIST_MAX_DID = 0x7f
}; };
/* Starting point and step size for each divider range.*/ /* Starting point and step size for each divider range.*/
@ -117,6 +118,8 @@ enum dentist_divider_range {
DENTIST_DIVIDER_RANGE_2_STEP = 2, /* 0.50 */ DENTIST_DIVIDER_RANGE_2_STEP = 2, /* 0.50 */
DENTIST_DIVIDER_RANGE_3_START = 128, /* 32.00 */ DENTIST_DIVIDER_RANGE_3_START = 128, /* 32.00 */
DENTIST_DIVIDER_RANGE_3_STEP = 4, /* 1.00 */ DENTIST_DIVIDER_RANGE_3_STEP = 4, /* 1.00 */
DENTIST_DIVIDER_RANGE_4_START = 248, /* 62.00 */
DENTIST_DIVIDER_RANGE_4_STEP = 264, /* 66.00 */
DENTIST_DIVIDER_RANGE_SCALE_FACTOR = 4 DENTIST_DIVIDER_RANGE_SCALE_FACTOR = 4
}; };
@ -133,9 +136,12 @@ static int dentist_get_divider_from_did(int did)
} else if (did < DENTIST_BASE_DID_3) { } else if (did < DENTIST_BASE_DID_3) {
return DENTIST_DIVIDER_RANGE_2_START + DENTIST_DIVIDER_RANGE_2_STEP return DENTIST_DIVIDER_RANGE_2_START + DENTIST_DIVIDER_RANGE_2_STEP
* (did - DENTIST_BASE_DID_2); * (did - DENTIST_BASE_DID_2);
} else { } else if (did < DENTIST_BASE_DID_4) {
return DENTIST_DIVIDER_RANGE_3_START + DENTIST_DIVIDER_RANGE_3_STEP return DENTIST_DIVIDER_RANGE_3_START + DENTIST_DIVIDER_RANGE_3_STEP
* (did - DENTIST_BASE_DID_3); * (did - DENTIST_BASE_DID_3);
} else {
return DENTIST_DIVIDER_RANGE_4_START + DENTIST_DIVIDER_RANGE_4_STEP
* (did - DENTIST_BASE_DID_4);
} }
} }
@ -478,7 +484,7 @@ static void dce12_update_clocks(struct dccg *dccg,
} }
} }
#ifdef CONFIG_X86 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
static int dcn1_determine_dppclk_threshold(struct dccg *dccg, struct dc_clocks *new_clocks) static int dcn1_determine_dppclk_threshold(struct dccg *dccg, struct dc_clocks *new_clocks)
{ {
bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz; bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz;
@ -668,7 +674,7 @@ static void dce_update_clocks(struct dccg *dccg,
} }
} }
#ifdef CONFIG_X86 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
static const struct display_clock_funcs dcn1_funcs = { static const struct display_clock_funcs dcn1_funcs = {
.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
.set_dispclk = dce112_set_clock, .set_dispclk = dce112_set_clock,
@ -823,7 +829,7 @@ struct dccg *dce120_dccg_create(struct dc_context *ctx)
return &clk_dce->base; return &clk_dce->base;
} }
#ifdef CONFIG_X86 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
struct dccg *dcn1_dccg_create(struct dc_context *ctx) struct dccg *dcn1_dccg_create(struct dc_context *ctx)
{ {
struct dc_debug_options *debug = &ctx->dc->debug; struct dc_debug_options *debug = &ctx->dc->debug;

2
drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h
View File

@ -111,7 +111,7 @@ struct dccg *dce112_dccg_create(
struct dccg *dce120_dccg_create(struct dc_context *ctx); struct dccg *dce120_dccg_create(struct dc_context *ctx);
#ifdef CONFIG_X86 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
struct dccg *dcn1_dccg_create(struct dc_context *ctx); struct dccg *dcn1_dccg_create(struct dc_context *ctx);
#endif #endif

6
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
View File

@ -316,7 +316,7 @@ static void dce_get_psr_wait_loop(
return; return;
} }
#ifdef CONFIG_X86 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
static void dcn10_get_dmcu_state(struct dmcu *dmcu) static void dcn10_get_dmcu_state(struct dmcu *dmcu)
{ {
struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
@ -743,7 +743,7 @@ static const struct dmcu_funcs dce_funcs = {
.is_dmcu_initialized = dce_is_dmcu_initialized .is_dmcu_initialized = dce_is_dmcu_initialized
}; };
#ifdef CONFIG_X86 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
static const struct dmcu_funcs dcn10_funcs = { static const struct dmcu_funcs dcn10_funcs = {
.dmcu_init = dcn10_dmcu_init, .dmcu_init = dcn10_dmcu_init,
.load_iram = dcn10_dmcu_load_iram, .load_iram = dcn10_dmcu_load_iram,
@ -795,7 +795,7 @@ struct dmcu *dce_dmcu_create(
return &dmcu_dce->base; return &dmcu_dce->base;
} }
#ifdef CONFIG_X86 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
struct dmcu *dcn10_dmcu_create( struct dmcu *dcn10_dmcu_create(
struct dc_context *ctx, struct dc_context *ctx,
const struct dce_dmcu_registers *regs, const struct dce_dmcu_registers *regs,

20
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
View File

@ -135,7 +135,7 @@ static void dce110_update_generic_info_packet(
AFMT_GENERIC0_UPDATE, (packet_index == 0), AFMT_GENERIC0_UPDATE, (packet_index == 0),
AFMT_GENERIC2_UPDATE, (packet_index == 2)); AFMT_GENERIC2_UPDATE, (packet_index == 2));
} }
#ifdef CONFIG_X86 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
if (REG(AFMT_VBI_PACKET_CONTROL1)) { if (REG(AFMT_VBI_PACKET_CONTROL1)) {
switch (packet_index) { switch (packet_index) {
case 0: case 0:
@ -229,7 +229,7 @@ static void dce110_update_hdmi_info_packet(
HDMI_GENERIC1_SEND, send, HDMI_GENERIC1_SEND, send,
HDMI_GENERIC1_LINE, line); HDMI_GENERIC1_LINE, line);
break; break;
#ifdef CONFIG_X86 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
case 4: case 4:
if (REG(HDMI_GENERIC_PACKET_CONTROL2)) if (REG(HDMI_GENERIC_PACKET_CONTROL2))
REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2, REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
@ -274,7 +274,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
struct dc_crtc_timing *crtc_timing, struct dc_crtc_timing *crtc_timing,
enum dc_color_space output_color_space) enum dc_color_space output_color_space)
{ {
#ifdef CONFIG_X86 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
uint32_t h_active_start; uint32_t h_active_start;
uint32_t v_active_start; uint32_t v_active_start;
uint32_t misc0 = 0; uint32_t misc0 = 0;
@ -317,7 +317,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
if (enc110->se_mask->DP_VID_M_DOUBLE_VALUE_EN) if (enc110->se_mask->DP_VID_M_DOUBLE_VALUE_EN)
REG_UPDATE(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, 1); REG_UPDATE(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, 1);
#ifdef CONFIG_X86 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
if (enc110->se_mask->DP_VID_N_MUL) if (enc110->se_mask->DP_VID_N_MUL)
REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1); REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1);
#endif #endif
@ -328,7 +328,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
break; break;
} }
#ifdef CONFIG_X86 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
if (REG(DP_MSA_MISC)) if (REG(DP_MSA_MISC))
misc1 = REG_READ(DP_MSA_MISC); misc1 = REG_READ(DP_MSA_MISC);
#endif #endif
@ -362,7 +362,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
/* set dynamic range and YCbCr range */ /* set dynamic range and YCbCr range */
#ifdef CONFIG_X86 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
switch (crtc_timing->display_color_depth) { switch (crtc_timing->display_color_depth) {
case COLOR_DEPTH_666: case COLOR_DEPTH_666:
colorimetry_bpc = 0; colorimetry_bpc = 0;
@ -441,7 +441,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
DP_DYN_RANGE, dynamic_range_rgb, DP_DYN_RANGE, dynamic_range_rgb,
DP_YCBCR_RANGE, dynamic_range_ycbcr); DP_YCBCR_RANGE, dynamic_range_ycbcr);
#ifdef CONFIG_X86 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
if (REG(DP_MSA_COLORIMETRY)) if (REG(DP_MSA_COLORIMETRY))
REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0); REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0);
@ -476,7 +476,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
crtc_timing->v_front_porch; crtc_timing->v_front_porch;
#ifdef CONFIG_X86 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
/* start at begining of left border */ /* start at begining of left border */
if (REG(DP_MSA_TIMING_PARAM2)) if (REG(DP_MSA_TIMING_PARAM2))
REG_SET_2(DP_MSA_TIMING_PARAM2, 0, REG_SET_2(DP_MSA_TIMING_PARAM2, 0,
@ -751,7 +751,7 @@ static void dce110_stream_encoder_update_hdmi_info_packets(
dce110_update_hdmi_info_packet(enc110, 3, &info_frame->hdrsmd); dce110_update_hdmi_info_packet(enc110, 3, &info_frame->hdrsmd);
} }
#ifdef CONFIG_X86 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
if (enc110->se_mask->HDMI_DB_DISABLE) { if (enc110->se_mask->HDMI_DB_DISABLE) {
/* for bring up, disable dp double TODO */ /* for bring up, disable dp double TODO */
if (REG(HDMI_DB_CONTROL)) if (REG(HDMI_DB_CONTROL))
@ -789,7 +789,7 @@ static void dce110_stream_encoder_stop_hdmi_info_packets(
HDMI_GENERIC1_LINE, 0, HDMI_GENERIC1_LINE, 0,
HDMI_GENERIC1_SEND, 0); HDMI_GENERIC1_SEND, 0);
#ifdef CONFIG_X86 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
/* stop generic packets 2 & 3 on HDMI */ /* stop generic packets 2 & 3 on HDMI */
if (REG(HDMI_GENERIC_PACKET_CONTROL2)) if (REG(HDMI_GENERIC_PACKET_CONTROL2))
REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0, REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0,

10
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
View File

@ -1250,7 +1250,7 @@ static void program_scaler(const struct dc *dc,
{ {
struct tg_color color = {0}; struct tg_color color = {0};
#ifdef CONFIG_X86 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
/* TOFPGA */ /* TOFPGA */
if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL) if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL)
return; return;
@ -1588,7 +1588,13 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
bool can_eDP_fast_boot_optimize = false; bool can_eDP_fast_boot_optimize = false;
if (edp_link) { if (edp_link) {
can_eDP_fast_boot_optimize = /* this seems to cause blank screens on DCE8 */
if ((dc->ctx->dce_version == DCE_VERSION_8_0) ||
(dc->ctx->dce_version == DCE_VERSION_8_1) ||
(dc->ctx->dce_version == DCE_VERSION_8_3))
can_eDP_fast_boot_optimize = false;
else
can_eDP_fast_boot_optimize =
edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc); edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc);
} }

2
drivers/gpu/drm/amd/display/dc/gpio/Makefile
View File

@ -61,7 +61,7 @@ AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCE120)
############################################################################### ###############################################################################
# DCN 1x # DCN 1x
############################################################################### ###############################################################################
ifdef CONFIG_X86 ifdef CONFIG_DRM_AMD_DC_DCN1_0
GPIO_DCN10 = hw_translate_dcn10.o hw_factory_dcn10.o GPIO_DCN10 = hw_translate_dcn10.o hw_factory_dcn10.o
AMD_DAL_GPIO_DCN10 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn10/,$(GPIO_DCN10)) AMD_DAL_GPIO_DCN10 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn10/,$(GPIO_DCN10))

4
drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
View File

@ -43,7 +43,7 @@
#include "dce80/hw_factory_dce80.h" #include "dce80/hw_factory_dce80.h"
#include "dce110/hw_factory_dce110.h" #include "dce110/hw_factory_dce110.h"
#include "dce120/hw_factory_dce120.h" #include "dce120/hw_factory_dce120.h"
#ifdef CONFIG_X86 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
#include "dcn10/hw_factory_dcn10.h" #include "dcn10/hw_factory_dcn10.h"
#endif #endif
@ -81,7 +81,7 @@ bool dal_hw_factory_init(
case DCE_VERSION_12_0: case DCE_VERSION_12_0:
dal_hw_factory_dce120_init(factory); dal_hw_factory_dce120_init(factory);
return true; return true;
#ifdef CONFIG_X86 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
case DCN_VERSION_1_0: case DCN_VERSION_1_0:
dal_hw_factory_dcn10_init(factory); dal_hw_factory_dcn10_init(factory);
return true; return true;

4
drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
View File

@ -43,7 +43,7 @@
#include "dce80/hw_translate_dce80.h" #include "dce80/hw_translate_dce80.h"
#include "dce110/hw_translate_dce110.h" #include "dce110/hw_translate_dce110.h"
#include "dce120/hw_translate_dce120.h" #include "dce120/hw_translate_dce120.h"
#ifdef CONFIG_X86 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
#include "dcn10/hw_translate_dcn10.h" #include "dcn10/hw_translate_dcn10.h"
#endif #endif
@ -78,7 +78,7 @@ bool dal_hw_translate_init(
case DCE_VERSION_12_0: case DCE_VERSION_12_0:
dal_hw_translate_dce120_init(translate); dal_hw_translate_dce120_init(translate);
return true; return true;
#ifdef CONFIG_X86 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
case DCN_VERSION_1_0: case DCN_VERSION_1_0:
dal_hw_translate_dcn10_init(translate); dal_hw_translate_dcn10_init(translate);
return true; return true;

2
drivers/gpu/drm/amd/display/dc/i2caux/Makefile
View File

@ -71,7 +71,7 @@ AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX_DCE112)
############################################################################### ###############################################################################
# DCN 1.0 family # DCN 1.0 family
############################################################################### ###############################################################################
ifdef CONFIG_X86 ifdef CONFIG_DRM_AMD_DC_DCN1_0
I2CAUX_DCN1 = i2caux_dcn10.o I2CAUX_DCN1 = i2caux_dcn10.o
AMD_DAL_I2CAUX_DCN1 = $(addprefix $(AMDDALPATH)/dc/i2caux/dcn10/,$(I2CAUX_DCN1)) AMD_DAL_I2CAUX_DCN1 = $(addprefix $(AMDDALPATH)/dc/i2caux/dcn10/,$(I2CAUX_DCN1))

4
drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c
View File

@ -59,7 +59,7 @@
#include "dce120/i2caux_dce120.h" #include "dce120/i2caux_dce120.h"
#ifdef CONFIG_X86 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
#include "dcn10/i2caux_dcn10.h" #include "dcn10/i2caux_dcn10.h"
#endif #endif
@ -91,7 +91,7 @@ struct i2caux *dal_i2caux_create(
return dal_i2caux_dce100_create(ctx); return dal_i2caux_dce100_create(ctx);
case DCE_VERSION_12_0: case DCE_VERSION_12_0:
return dal_i2caux_dce120_create(ctx); return dal_i2caux_dce120_create(ctx);
#ifdef CONFIG_X86 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
case DCN_VERSION_1_0: case DCN_VERSION_1_0:
return dal_i2caux_dcn10_create(ctx); return dal_i2caux_dcn10_create(ctx);
#endif #endif

7
drivers/gpu/drm/amd/display/dc/inc/core_types.h
View File

@ -33,7 +33,7 @@
#include "dc_bios_types.h" #include "dc_bios_types.h"
#include "mem_input.h" #include "mem_input.h"
#include "hubp.h" #include "hubp.h"
#ifdef CONFIG_X86 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
#include "mpc.h" #include "mpc.h"
#endif #endif
@ -92,6 +92,7 @@ struct resource_context;
struct resource_funcs { struct resource_funcs {
void (*destroy)(struct resource_pool **pool); void (*destroy)(struct resource_pool **pool);
void (*link_init)(struct dc_link *link);
struct link_encoder *(*link_enc_create)( struct link_encoder *(*link_enc_create)(
const struct encoder_init_data *init); const struct encoder_init_data *init);
@ -221,7 +222,7 @@ struct pipe_ctx {
struct pipe_ctx *top_pipe; struct pipe_ctx *top_pipe;
struct pipe_ctx *bottom_pipe; struct pipe_ctx *bottom_pipe;
#ifdef CONFIG_X86 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
struct _vcs_dpi_display_dlg_regs_st dlg_regs; struct _vcs_dpi_display_dlg_regs_st dlg_regs;
struct _vcs_dpi_display_ttu_regs_st ttu_regs; struct _vcs_dpi_display_ttu_regs_st ttu_regs;
struct _vcs_dpi_display_rq_regs_st rq_regs; struct _vcs_dpi_display_rq_regs_st rq_regs;
@ -276,7 +277,7 @@ struct dc_state {
/* Note: these are big structures, do *not* put on stack! */ /* Note: these are big structures, do *not* put on stack! */
struct dm_pp_display_configuration pp_display_cfg; struct dm_pp_display_configuration pp_display_cfg;
#ifdef CONFIG_X86 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
struct dcn_bw_internal_vars dcn_bw_vars; struct dcn_bw_internal_vars dcn_bw_vars;
#endif #endif

2
drivers/gpu/drm/amd/display/dc/irq/Makefile
View File

@ -60,7 +60,7 @@ AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCE12)
############################################################################### ###############################################################################
# DCN 1x # DCN 1x
############################################################################### ###############################################################################
ifdef CONFIG_X86 ifdef CONFIG_DRM_AMD_DC_DCN1_0
IRQ_DCN1 = irq_service_dcn10.o IRQ_DCN1 = irq_service_dcn10.o
AMD_DAL_IRQ_DCN1 = $(addprefix $(AMDDALPATH)/dc/irq/dcn10/,$(IRQ_DCN1)) AMD_DAL_IRQ_DCN1 = $(addprefix $(AMDDALPATH)/dc/irq/dcn10/,$(IRQ_DCN1))

2
drivers/gpu/drm/amd/display/dc/irq/irq_service.c
View File

@ -36,7 +36,7 @@
#include "dce120/irq_service_dce120.h" #include "dce120/irq_service_dce120.h"
#ifdef CONFIG_X86 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
#include "dcn10/irq_service_dcn10.h" #include "dcn10/irq_service_dcn10.h"
#endif #endif

2
drivers/gpu/drm/amd/display/dc/os_types.h
View File

@ -48,7 +48,7 @@
#define dm_error(fmt, ...) DRM_ERROR(fmt, ##__VA_ARGS__) #define dm_error(fmt, ...) DRM_ERROR(fmt, ##__VA_ARGS__)
#ifdef CONFIG_X86 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
#include <asm/fpu/api.h> #include <asm/fpu/api.h>
#endif #endif

4
drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
View File

@ -75,10 +75,12 @@ int phm_set_power_state(struct pp_hwmgr *hwmgr,
int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr) int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
{ {
struct amdgpu_device *adev = NULL;
int ret = -EINVAL;; int ret = -EINVAL;;
PHM_FUNC_CHECK(hwmgr); PHM_FUNC_CHECK(hwmgr);
adev = hwmgr->adev;
if (smum_is_dpm_running(hwmgr)) { if (smum_is_dpm_running(hwmgr) && !amdgpu_passthrough(adev)) {
pr_info("dpm has been enabled\n"); pr_info("dpm has been enabled\n");
return 0; return 0;
} }

3
drivers/gpu/drm/drm_edid.c
View File

@ -116,6 +116,9 @@ static const struct edid_quirk {
/* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
{ "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC }, { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC },
/* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
{ "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC },
/* Belinea 10 15 55 */ /* Belinea 10 15 55 */
{ "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
{ "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },

3
drivers/gpu/drm/panel/panel-simple.c
View File

@ -1385,6 +1385,9 @@ static const struct panel_desc innolux_tv123wam = {
.width = 259, .width = 259,
.height = 173, .height = 173,
}, },
.delay = {
.unprepare = 500,
},
}; };
static const struct drm_display_mode innolux_zj070na_01p_mode = { static const struct drm_display_mode innolux_zj070na_01p_mode = {