Blackfin arch: Fix BUG -- BF533 + 0.5 silicon + MPU + UART PIO -> crash
Apply ANOMALY_05000283 & ANOMALY_05000315 Workaround also to the EXCEPTION path. Cover evt_ivhw also with ANOMALY_05000315 The Workaround needs to be prior to accesses (either read or write) to any system MMR. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
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@ -484,6 +484,15 @@ ENTRY(_trap) /* Exception: 4th entry into system event table(supervisor mode)*/
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[--sp] = ASTAT;
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[--sp] = (R7:6,P5:4);
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#if ANOMALY_05000283 || ANOMALY_05000315
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cc = r7 == r7;
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p5.h = HI(CHIPID);
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p5.l = LO(CHIPID);
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if cc jump 1f;
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r7.l = W[p5];
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1:
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#endif
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#ifdef CONFIG_DEBUG_DOUBLEFAULT
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/*
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* Save these registers, as they are only valid in exception context
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@ -1020,6 +1029,15 @@ ENTRY(_early_trap)
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SAVE_ALL_SYS
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trace_buffer_stop(p0,r0);
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#if ANOMALY_05000283 || ANOMALY_05000315
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cc = r5 == r5;
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p4.h = HI(CHIPID);
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p4.l = LO(CHIPID);
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if cc jump 1f;
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r5.l = W[p4];
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1:
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#endif
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/* Turn caches off, to ensure we don't get double exceptions */
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P4.L = LO(IMEM_CONTROL);
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@ -143,7 +143,7 @@ ENTRY(_evt_ivhw)
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fp = 0;
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#endif
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#if ANOMALY_05000283
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#if ANOMALY_05000283 || ANOMALY_05000315
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cc = r7 == r7;
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p5.h = HI(CHIPID);
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p5.l = LO(CHIPID);
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