Staging: et131x: PHY loopback cannot be set (and isn't useful for us anyway)
Remove the stuff that falls out from this always being zero. Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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abc449970a
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@ -221,13 +221,8 @@ void ConfigMACRegs2(struct et131x_adapter *etdev)
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*/
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cfg2.bits.len_check = 0x1;
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if (etdev->RegistryPhyLoopbk == false) {
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cfg2.bits.pad_crc = 0x1;
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cfg2.bits.crc_enable = 0x1;
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} else {
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cfg2.bits.pad_crc = 0;
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cfg2.bits.crc_enable = 0;
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}
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/* 1 - full duplex, 0 - half-duplex */
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cfg2.bits.full_duplex = etdev->duplex_mode;
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@ -469,8 +469,6 @@ void et131x_Mii_check(struct et131x_adapter *etdev,
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spin_unlock_irqrestore(&etdev->Lock, flags);
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/* Don't indicate state if we're in loopback mode */
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if (etdev->RegistryPhyLoopbk == false)
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netif_carrier_on(etdev->netdev);
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} else {
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dev_warn(&etdev->pdev->dev,
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@ -504,10 +502,6 @@ void et131x_Mii_check(struct et131x_adapter *etdev,
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spin_unlock_irqrestore(&etdev->Lock,
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flags);
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/* Only indicate state if we're in loopback
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* mode
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*/
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if (etdev->RegistryPhyLoopbk == false)
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netif_carrier_off(etdev->netdev);
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}
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@ -807,10 +807,6 @@ void et131x_rx_dma_disable(struct et131x_adapter *etdev)
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*/
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void et131x_rx_dma_enable(struct et131x_adapter *etdev)
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{
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if (etdev->RegistryPhyLoopbk)
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/* RxDMA is disabled for loopback operation. */
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writel(0x1, &etdev->regs->rxdma.csr.value);
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else {
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/* Setup the receive dma configuration register for normal operation */
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RXDMA_CSR_t csr = { 0 };
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@ -843,7 +839,6 @@ void et131x_rx_dma_enable(struct et131x_adapter *etdev)
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}
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}
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}
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}
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/**
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* nic_rx_pkts - Checks the hardware for available packets
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@ -279,16 +279,11 @@ void et131x_tx_dma_disable(struct et131x_adapter *etdev)
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*/
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void et131x_tx_dma_enable(struct et131x_adapter *etdev)
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{
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u32 csr = ET_TXDMA_SNGL_EPKT;
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if (etdev->RegistryPhyLoopbk)
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/* TxDMA is disabled for loopback operation. */
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csr |= ET_TXDMA_CSR_HALT;
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else
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/* Setup the transmit dma configuration register for normal
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* operation
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*/
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csr |= PARM_DMA_CACHE_DEF << ET_TXDMA_CACHE_SHIFT;
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writel(csr, &etdev->regs->txdma.csr);
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writel(ET_TXDMA_SNGL_EPKT|(PARM_DMA_CACHE_DEF << ET_TXDMA_CACHE_SHIFT),
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&etdev->regs->txdma.csr);
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}
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/**
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@ -234,8 +234,6 @@ struct et131x_adapter {
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u32 RegistryRxMemEnd; /* Size of internal rx memory */
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u32 RegistryJumboPacket; /* Max supported ethernet packet size */
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/* Validation helpers */
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u8 RegistryPhyLoopbk; /* Enable Phy loopback */
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/* Derived from the registry: */
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u8 AiForceDpx; /* duplex setting */
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@ -329,51 +329,33 @@ void ConfigGlobalRegs(struct et131x_adapter *etdev)
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{
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struct _GLOBAL_t __iomem *regs = &etdev->regs->global;
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if (etdev->RegistryPhyLoopbk == false) {
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writel(0, ®s->rxq_start_addr);
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writel(INTERNAL_MEM_SIZE - 1, ®s->txq_end_addr);
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if (etdev->RegistryJumboPacket < 2048) {
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/* Tx / RxDMA and Tx/Rx MAC interfaces have a 1k word
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* block of RAM that the driver can split between Tx
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* and Rx as it desires. Our default is to split it
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* 50/50:
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*/
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writel(0, ®s->rxq_start_addr);
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writel(PARM_RX_MEM_END_DEF, ®s->rxq_end_addr);
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writel(PARM_RX_MEM_END_DEF + 1, ®s->txq_start_addr);
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writel(INTERNAL_MEM_SIZE - 1, ®s->txq_end_addr);
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} else if (etdev->RegistryJumboPacket < 8192) {
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/* For jumbo packets > 2k but < 8k, split 50-50. */
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writel(0, ®s->rxq_start_addr);
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writel(INTERNAL_MEM_RX_OFFSET, ®s->rxq_end_addr);
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writel(INTERNAL_MEM_RX_OFFSET + 1, ®s->txq_start_addr);
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writel(INTERNAL_MEM_SIZE - 1, ®s->txq_end_addr);
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} else {
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/* 9216 is the only packet size greater than 8k that
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* is available. The Tx buffer has to be big enough
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* for one whole packet on the Tx side. We'll make
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* the Tx 9408, and give the rest to Rx
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*/
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writel(0x0000, ®s->rxq_start_addr);
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writel(0x01b3, ®s->rxq_end_addr);
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writel(0x01b4, ®s->txq_start_addr);
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writel(INTERNAL_MEM_SIZE - 1,®s->txq_end_addr);
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}
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/* Initialize the loopback register. Disable all loopbacks. */
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writel(0, ®s->loopback);
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} else {
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/* For PHY Line loopback, the memory is configured as if Tx
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* and Rx both have all the memory. This is because the
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* RxMAC will write data into the space, and the TxMAC will
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* read it out.
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*/
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writel(0, ®s->rxq_start_addr);
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writel(INTERNAL_MEM_SIZE - 1, ®s->rxq_end_addr);
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writel(0, ®s->txq_start_addr);
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writel(INTERNAL_MEM_SIZE - 1, ®s->txq_end_addr);
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/* Initialize the loopback register (MAC loopback). */
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writel(ET_LOOP_MAC, ®s->loopback);
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}
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/* MSI Register */
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writel(0, ®s->msi_config);
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