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drm fixes for 4.8-rc6 

i915, vc4 and atmel.
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Merge tag 'drm-fixes-for-4.8-rc6' of git://people.freedesktop.org/~airlied/linux

Pull drm fixes from Dave Airlie:
 "Two sets of i915 fixes, one set of vc4 crasher fixes, and a couple of
  atmel fixes.

  Nothing too out there at this stage, though I think some people are
  holidaying so it's been quiet enough"

* tag 'drm-fixes-for-4.8-rc6' of git://people.freedesktop.org/~airlied/linux:
  drm/i915: Ignore OpRegion panel type except on select machines
  Revert "drm/i915/psr: Make idle_frames sensible again"
  drm/i915: Restore lost "Initialized i915" welcome message
  drm/vc4: mark vc4_bo_cache_purge() static
  drm/i915: Add GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE to SNB
  drm/i915: disable 48bit full PPGTT when vGPU is active
  drm/i915: enable vGPU detection for all
  drm/atmel-hlcdc: Make ->reset() implementation static
  drm: atmel-hlcdc: Fix vertical scaling
  drm/vc4: Allow some more signals to be packed with uniform resets.
  drm/i915/dvo: Remove dangling call to drm_encoder_cleanup()
hifive-unleashed-5.1
Linus Torvalds 2016-09-16 16:27:30 -07:00
parent 095f5cfaea 09cb5b78af
commit 5fbf3e3275
11 changed files with 61 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
View File

@ -387,7 +387,7 @@ void atmel_hlcdc_crtc_irq(struct drm_crtc *c)
atmel_hlcdc_crtc_finish_page_flip(drm_crtc_to_atmel_hlcdc_crtc(c));
}
void atmel_hlcdc_crtc_reset(struct drm_crtc *crtc)
static void atmel_hlcdc_crtc_reset(struct drm_crtc *crtc)
{
struct atmel_hlcdc_crtc_state *state;

10
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c
View File

@ -320,19 +320,19 @@ atmel_hlcdc_plane_update_pos_and_size(struct atmel_hlcdc_plane *plane,
u32 *coeff_tab = heo_upscaling_ycoef;
u32 max_memsize;
if (state->crtc_w < state->src_w)
if (state->crtc_h < state->src_h)
coeff_tab = heo_downscaling_ycoef;
for (i = 0; i < ARRAY_SIZE(heo_upscaling_ycoef); i++)
atmel_hlcdc_layer_update_cfg(&plane->layer,
33 + i,
0xffffffff,
coeff_tab[i]);
factor = ((8 * 256 * state->src_w) - (256 * 4)) /
state->crtc_w;
factor = ((8 * 256 * state->src_h) - (256 * 4)) /
state->crtc_h;
factor++;
max_memsize = ((factor * state->crtc_w) + (256 * 4)) /
max_memsize = ((factor * state->crtc_h) + (256 * 4)) /
2048;
if (max_memsize > state->src_w)
if (max_memsize > state->src_h)
factor--;
factor_reg |= (factor << 16) | 0x80000000;
}

5
drivers/gpu/drm/i915/i915_drv.c
View File

@ -1281,6 +1281,11 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
intel_runtime_pm_enable(dev_priv);
/* Everything is in place, we can now relax! */
DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
driver.name, driver.major, driver.minor, driver.patchlevel,
driver.date, pci_name(pdev), dev_priv->drm.primary->index);
intel_runtime_pm_put(dev_priv);
return 0;

9
drivers/gpu/drm/i915/i915_gem_gtt.c
View File

@ -122,8 +122,11 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
has_full_48bit_ppgtt =
IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9;
if (intel_vgpu_active(dev_priv))
has_full_ppgtt = false; /* emulation is too hard */
if (intel_vgpu_active(dev_priv)) {
/* emulation is too hard */
has_full_ppgtt = false;
has_full_48bit_ppgtt = false;
}
if (!has_aliasing_ppgtt)
return 0;
@ -158,7 +161,7 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
return 0;
}
if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists)
if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists && has_full_ppgtt)
return has_full_48bit_ppgtt ? 3 : 2;
else
return has_aliasing_ppgtt ? 1 : 0;

3
drivers/gpu/drm/i915/i915_vgpu.c
View File

@ -65,9 +65,6 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
BUILD_BUG_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
if (!IS_HASWELL(dev_priv))
return;
magic = __raw_i915_read64(dev_priv, vgtif_reg(magic));
if (magic != VGT_MAGIC)
return;

1
drivers/gpu/drm/i915/intel_dvo.c
View File

@ -554,7 +554,6 @@ void intel_dvo_init(struct drm_device *dev)
return;
}
drm_encoder_cleanup(&intel_encoder->base);
kfree(intel_dvo);
kfree(intel_connector);
}

27
drivers/gpu/drm/i915/intel_opregion.c
View File

@ -1047,6 +1047,23 @@ err_out:
return err;
}
static int intel_use_opregion_panel_type_callback(const struct dmi_system_id *id)
{
DRM_INFO("Using panel type from OpRegion on %s\n", id->ident);
return 1;
}
static const struct dmi_system_id intel_use_opregion_panel_type[] = {
{
.callback = intel_use_opregion_panel_type_callback,
.ident = "Conrac GmbH IX45GM2",
.matches = {DMI_MATCH(DMI_SYS_VENDOR, "Conrac GmbH"),
DMI_MATCH(DMI_PRODUCT_NAME, "IX45GM2"),
},
},
{ }
};
int
intel_opregion_get_panel_type(struct drm_i915_private *dev_priv)
{
@ -1072,6 +1089,16 @@ intel_opregion_get_panel_type(struct drm_i915_private *dev_priv)
return -ENODEV;
}
/*
* So far we know that some machined must use it, others must not use it.
* There doesn't seem to be any way to determine which way to go, except
* via a quirk list :(
*/
if (!dmi_check_system(intel_use_opregion_panel_type)) {
DRM_DEBUG_KMS("Ignoring OpRegion panel type (%d)\n", ret - 1);
return -ENODEV;
}
/*
* FIXME On Dell XPS 13 9350 the OpRegion panel type (0) gives us
* low vswing for eDP, whereas the VBT panel type (2) gives us normal

1
drivers/gpu/drm/i915/intel_pm.c
View File

@ -7859,6 +7859,7 @@ static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
case GEN6_PCODE_ILLEGAL_CMD:
return -ENXIO;
case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
return -EOVERFLOW;
case GEN6_PCODE_TIMEOUT:
return -ETIMEDOUT;

14
drivers/gpu/drm/i915/intel_psr.c
View File

@ -255,14 +255,14 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = to_i915(dev);
uint32_t max_sleep_time = 0x1f;
/* Lately it was identified that depending on panel idle frame count
* calculated at HW can be off by 1. So let's use what came
* from VBT + 1.
* There are also other cases where panel demands at least 4
* but VBT is not being set. To cover these 2 cases lets use
* at least 5 when VBT isn't set to be on the safest side.
/*
* Let's respect VBT in case VBT asks a higher idle_frame value.
* Let's use 6 as the minimum to cover all known cases including
* the off-by-one issue that HW has in some cases. Also there are
* cases where sink should be able to train
* with the 5 or 6 idle patterns.
*/
uint32_t idle_frames = dev_priv->vbt.psr.idle_frames + 1;
uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
uint32_t val = EDP_PSR_ENABLE;
val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;

2
drivers/gpu/drm/vc4/vc4_bo.c
View File

@ -144,7 +144,7 @@ static struct list_head *vc4_get_cache_list_for_size(struct drm_device *dev,
return &vc4->bo_cache.size_list[page_index];
}
void vc4_bo_cache_purge(struct drm_device *dev)
static void vc4_bo_cache_purge(struct drm_device *dev)
{
struct vc4_dev *vc4 = to_vc4_dev(dev);

10
drivers/gpu/drm/vc4/vc4_validate_shaders.c
View File

@ -309,8 +309,14 @@ validate_uniform_address_write(struct vc4_validated_shader_info *validated_shade
* of uniforms on each side. However, this scheme is easy to
* validate so it's all we allow for now.
*/
if (QPU_GET_FIELD(inst, QPU_SIG) != QPU_SIG_NONE) {
switch (QPU_GET_FIELD(inst, QPU_SIG)) {
case QPU_SIG_NONE:
case QPU_SIG_SCOREBOARD_UNLOCK:
case QPU_SIG_COLOR_LOAD:
case QPU_SIG_LOAD_TMU0:
case QPU_SIG_LOAD_TMU1:
break;
default:
DRM_ERROR("uniforms address change must be "
"normal math\n");
return false;