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amd64_edac: fix K8 chip select reporting 

Fix the case when amd64_debug_display_dimm_sizes() reports only half the
amount of DRAM on it because it doesn't account for when the single DCT
operates in 128-bit mode and merges chip selects from different DIMMs.

Reported-by: Johannes Hirte <johannes.hirte@fem.tu-ilmenau.de>
LKML-Reference: <200912112202.48173.johannes.hirte@fem.tu-ilmenau.de>
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
hifive-unleashed-5.1
Borislav Petkov 2009-12-21 14:52:53 +01:00
parent 2f99f5c8f0
commit 603adaf6b3
1 changed files with 6 additions and 2 deletions
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8
drivers/edac/amd64_edac.c
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@ -1700,11 +1700,14 @@ static void f10_map_sysaddr_to_csrow(struct mem_ctl_info *mci,
*/
static void amd64_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt)
{
int dimm, size0, size1;
int dimm, size0, size1, factor = 0;
u32 dbam;
u32 *dcsb;
if (boot_cpu_data.x86 == 0xf) {
if (pvt->dclr0 & F10_WIDTH_128)
factor = 1;
/* K8 families < revF not supported yet */
if (pvt->ext_model < K8_REV_F)
return;
@ -1732,7 +1735,8 @@ static void amd64_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt)
size1 = pvt->ops->dbam_to_cs(pvt, DBAM_DIMM(dimm, dbam));
edac_printk(KERN_DEBUG, EDAC_MC, " %d: %5dMB %d: %5dMB\n",
dimm * 2, size0, dimm * 2 + 1, size1);
dimm * 2, size0 << factor,
dimm * 2 + 1, size1 << factor);
}
}