drm/amdgpu: Fix 32bit x86 compilation warning
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c:187:2: warning: right shift count >= width of type [enabled by default] drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c:173:2: warning: right shift count >= width of type [enabled by default] drivers/gpu/drm/amd/amdgpu/vega10_ih.c:106:3: warning: right shift count >= width of type [enabled by default] v2: Add a space between "&" and "0xff" Reported by: kbuild-all@01.org Signed-off-by: Alex Xie <AlexBin.Xie@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -172,7 +172,7 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
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(u32)(adev->dummy_page.addr >> 12));
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WREG32(SOC15_REG_OFFSET(GC, 0,
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mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),
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(u32)(adev->dummy_page.addr >> 44));
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(u32)((u64)adev->dummy_page.addr >> 44));
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tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL2));
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tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,
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@ -186,7 +186,7 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
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(u32)(adev->dummy_page.addr >> 12));
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WREG32(SOC15_REG_OFFSET(MMHUB, 0,
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mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),
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(u32)(adev->dummy_page.addr >> 44));
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(u32)((u64)adev->dummy_page.addr >> 44));
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tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2));
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tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,
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@ -103,7 +103,7 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)
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/* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
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if (adev->irq.ih.use_bus_addr) {
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WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE), adev->irq.ih.rb_dma_addr >> 8);
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WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI), (adev->irq.ih.rb_dma_addr >> 40) &0xff);
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WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI), ((u64)adev->irq.ih.rb_dma_addr >> 40) & 0xff);
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ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE, 1);
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} else {
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WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE), adev->irq.ih.gpu_addr >> 8);
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