drm/i915: split clock gating init into per-chipset functions
This helps contain the mess to init_display() instead. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Keith Packard <keithp@keithp.com> Signed-off-by: Keith Packard <keithp@keithp.com>
This commit is contained in:
parent
90711d50d0
commit
6067aaeadb
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@ -209,12 +209,12 @@ struct drm_i915_display_funcs {
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int x, int y,
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struct drm_framebuffer *old_fb);
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void (*fdi_link_train)(struct drm_crtc *crtc);
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void (*init_clock_gating)(struct drm_device *dev);
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/* clock updates for mode set */
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/* cursor updates */
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/* render clock increase/decrease */
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/* display clock increase/decrease */
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/* pll clock increase/decrease */
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/* clock gating init */
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};
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struct intel_device_info {
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@ -864,7 +864,7 @@ int i915_restore_state(struct drm_device *dev)
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}
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/* Clock gating state */
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intel_enable_clock_gating(dev);
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dev_priv->display.init_clock_gating(dev);
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if (IS_IRONLAKE_M(dev)) {
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ironlake_enable_drps(dev);
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@ -7211,161 +7211,194 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
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mutex_unlock(&dev_priv->dev->struct_mutex);
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}
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void intel_enable_clock_gating(struct drm_device *dev)
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static void ironlake_init_clock_gating(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
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/* Required for FBC */
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dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
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DPFCRUNIT_CLOCK_GATE_DISABLE |
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DPFDUNIT_CLOCK_GATE_DISABLE;
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/* Required for CxSR */
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dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
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I915_WRITE(PCH_3DCGDIS0,
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MARIUNIT_CLOCK_GATE_DISABLE |
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SVSMUNIT_CLOCK_GATE_DISABLE);
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I915_WRITE(PCH_3DCGDIS1,
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VFMUNIT_CLOCK_GATE_DISABLE);
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I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
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/*
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* On Ibex Peak and Cougar Point, we need to disable clock
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* gating for the panel power sequencer or it will fail to
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* start up when no ports are active.
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*/
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I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
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/*
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* According to the spec the following bits should be set in
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* order to enable memory self-refresh
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* The bit 22/21 of 0x42004
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* The bit 5 of 0x42020
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* The bit 15 of 0x45000
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*/
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I915_WRITE(ILK_DISPLAY_CHICKEN2,
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(I915_READ(ILK_DISPLAY_CHICKEN2) |
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ILK_DPARB_GATE | ILK_VSDPFD_FULL));
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I915_WRITE(ILK_DSPCLK_GATE,
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(I915_READ(ILK_DSPCLK_GATE) |
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ILK_DPARB_CLK_GATE));
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I915_WRITE(DISP_ARB_CTL,
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(I915_READ(DISP_ARB_CTL) |
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DISP_FBC_WM_DIS));
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I915_WRITE(WM3_LP_ILK, 0);
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I915_WRITE(WM2_LP_ILK, 0);
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I915_WRITE(WM1_LP_ILK, 0);
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/*
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* Based on the document from hardware guys the following bits
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* should be set unconditionally in order to enable FBC.
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* The bit 22 of 0x42000
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* The bit 22 of 0x42004
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* The bit 7,8,9 of 0x42020.
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*/
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if (IS_IRONLAKE_M(dev)) {
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I915_WRITE(ILK_DISPLAY_CHICKEN1,
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I915_READ(ILK_DISPLAY_CHICKEN1) |
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ILK_FBCQ_DIS);
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I915_WRITE(ILK_DISPLAY_CHICKEN2,
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I915_READ(ILK_DISPLAY_CHICKEN2) |
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ILK_DPARB_GATE);
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I915_WRITE(ILK_DSPCLK_GATE,
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I915_READ(ILK_DSPCLK_GATE) |
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ILK_DPFC_DIS1 |
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ILK_DPFC_DIS2 |
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ILK_CLK_FBC);
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}
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I915_WRITE(ILK_DISPLAY_CHICKEN2,
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I915_READ(ILK_DISPLAY_CHICKEN2) |
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ILK_ELPIN_409_SELECT);
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I915_WRITE(_3D_CHICKEN2,
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_3D_CHICKEN2_WM_READ_PIPELINED << 16 |
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_3D_CHICKEN2_WM_READ_PIPELINED);
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}
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static void gen6_init_clock_gating(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int pipe;
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uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
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I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
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/*
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* Disable clock gating reported to work incorrectly according to the
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* specs, but enable as much else as we can.
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* On Ibex Peak and Cougar Point, we need to disable clock
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* gating for the panel power sequencer or it will fail to
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* start up when no ports are active.
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*/
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if (HAS_PCH_SPLIT(dev)) {
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uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
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I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
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if (IS_GEN5(dev)) {
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/* Required for FBC */
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dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
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DPFCRUNIT_CLOCK_GATE_DISABLE |
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DPFDUNIT_CLOCK_GATE_DISABLE;
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/* Required for CxSR */
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dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
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I915_WRITE(ILK_DISPLAY_CHICKEN2,
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I915_READ(ILK_DISPLAY_CHICKEN2) |
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ILK_ELPIN_409_SELECT);
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I915_WRITE(PCH_3DCGDIS0,
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MARIUNIT_CLOCK_GATE_DISABLE |
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SVSMUNIT_CLOCK_GATE_DISABLE);
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I915_WRITE(PCH_3DCGDIS1,
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VFMUNIT_CLOCK_GATE_DISABLE);
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}
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I915_WRITE(WM3_LP_ILK, 0);
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I915_WRITE(WM2_LP_ILK, 0);
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I915_WRITE(WM1_LP_ILK, 0);
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I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
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/*
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* According to the spec the following bits should be
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* set in order to enable memory self-refresh and fbc:
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* The bit21 and bit22 of 0x42000
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* The bit21 and bit22 of 0x42004
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* The bit5 and bit7 of 0x42020
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* The bit14 of 0x70180
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* The bit14 of 0x71180
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*/
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I915_WRITE(ILK_DISPLAY_CHICKEN1,
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I915_READ(ILK_DISPLAY_CHICKEN1) |
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ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
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I915_WRITE(ILK_DISPLAY_CHICKEN2,
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I915_READ(ILK_DISPLAY_CHICKEN2) |
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ILK_DPARB_GATE | ILK_VSDPFD_FULL);
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I915_WRITE(ILK_DSPCLK_GATE,
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I915_READ(ILK_DSPCLK_GATE) |
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ILK_DPARB_CLK_GATE |
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ILK_DPFD_CLK_GATE);
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/*
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* On Ibex Peak and Cougar Point, we need to disable clock
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* gating for the panel power sequencer or it will fail to
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* start up when no ports are active.
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*/
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I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
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for_each_pipe(pipe)
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I915_WRITE(DSPCNTR(pipe),
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I915_READ(DSPCNTR(pipe)) |
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DISPPLANE_TRICKLE_FEED_DISABLE);
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}
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/*
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* According to the spec the following bits should be set in
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* order to enable memory self-refresh
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* The bit 22/21 of 0x42004
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* The bit 5 of 0x42020
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* The bit 15 of 0x45000
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*/
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if (IS_GEN5(dev)) {
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I915_WRITE(ILK_DISPLAY_CHICKEN2,
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(I915_READ(ILK_DISPLAY_CHICKEN2) |
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ILK_DPARB_GATE | ILK_VSDPFD_FULL));
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I915_WRITE(ILK_DSPCLK_GATE,
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(I915_READ(ILK_DSPCLK_GATE) |
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ILK_DPARB_CLK_GATE));
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I915_WRITE(DISP_ARB_CTL,
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(I915_READ(DISP_ARB_CTL) |
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DISP_FBC_WM_DIS));
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I915_WRITE(WM3_LP_ILK, 0);
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I915_WRITE(WM2_LP_ILK, 0);
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I915_WRITE(WM1_LP_ILK, 0);
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}
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/*
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* Based on the document from hardware guys the following bits
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* should be set unconditionally in order to enable FBC.
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* The bit 22 of 0x42000
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* The bit 22 of 0x42004
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* The bit 7,8,9 of 0x42020.
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*/
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if (IS_IRONLAKE_M(dev)) {
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I915_WRITE(ILK_DISPLAY_CHICKEN1,
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I915_READ(ILK_DISPLAY_CHICKEN1) |
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ILK_FBCQ_DIS);
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I915_WRITE(ILK_DISPLAY_CHICKEN2,
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I915_READ(ILK_DISPLAY_CHICKEN2) |
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ILK_DPARB_GATE);
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I915_WRITE(ILK_DSPCLK_GATE,
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I915_READ(ILK_DSPCLK_GATE) |
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ILK_DPFC_DIS1 |
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ILK_DPFC_DIS2 |
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ILK_CLK_FBC);
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}
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static void g4x_init_clock_gating(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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uint32_t dspclk_gate;
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I915_WRITE(ILK_DISPLAY_CHICKEN2,
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I915_READ(ILK_DISPLAY_CHICKEN2) |
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ILK_ELPIN_409_SELECT);
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I915_WRITE(RENCLK_GATE_D1, 0);
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I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
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GS_UNIT_CLOCK_GATE_DISABLE |
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CL_UNIT_CLOCK_GATE_DISABLE);
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I915_WRITE(RAMCLK_GATE_D, 0);
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dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
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OVRUNIT_CLOCK_GATE_DISABLE |
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OVCUNIT_CLOCK_GATE_DISABLE;
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if (IS_GM45(dev))
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dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
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I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
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}
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if (IS_GEN5(dev)) {
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I915_WRITE(_3D_CHICKEN2,
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_3D_CHICKEN2_WM_READ_PIPELINED << 16 |
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_3D_CHICKEN2_WM_READ_PIPELINED);
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}
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static void crestline_init_clock_gating(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
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I915_WRITE(WM3_LP_ILK, 0);
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I915_WRITE(WM2_LP_ILK, 0);
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I915_WRITE(WM1_LP_ILK, 0);
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I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
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I915_WRITE(RENCLK_GATE_D2, 0);
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I915_WRITE(DSPCLK_GATE_D, 0);
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I915_WRITE(RAMCLK_GATE_D, 0);
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I915_WRITE16(DEUC, 0);
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}
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/*
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* According to the spec the following bits should be
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* set in order to enable memory self-refresh and fbc:
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* The bit21 and bit22 of 0x42000
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* The bit21 and bit22 of 0x42004
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* The bit5 and bit7 of 0x42020
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* The bit14 of 0x70180
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* The bit14 of 0x71180
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*/
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I915_WRITE(ILK_DISPLAY_CHICKEN1,
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I915_READ(ILK_DISPLAY_CHICKEN1) |
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ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
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I915_WRITE(ILK_DISPLAY_CHICKEN2,
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I915_READ(ILK_DISPLAY_CHICKEN2) |
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ILK_DPARB_GATE | ILK_VSDPFD_FULL);
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I915_WRITE(ILK_DSPCLK_GATE,
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I915_READ(ILK_DSPCLK_GATE) |
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ILK_DPARB_CLK_GATE |
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ILK_DPFD_CLK_GATE);
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static void broadwater_init_clock_gating(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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for_each_pipe(pipe)
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I915_WRITE(DSPCNTR(pipe),
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I915_READ(DSPCNTR(pipe)) |
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DISPPLANE_TRICKLE_FEED_DISABLE);
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}
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} else if (IS_G4X(dev)) {
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uint32_t dspclk_gate;
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I915_WRITE(RENCLK_GATE_D1, 0);
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I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
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GS_UNIT_CLOCK_GATE_DISABLE |
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CL_UNIT_CLOCK_GATE_DISABLE);
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I915_WRITE(RAMCLK_GATE_D, 0);
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dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
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OVRUNIT_CLOCK_GATE_DISABLE |
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OVCUNIT_CLOCK_GATE_DISABLE;
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if (IS_GM45(dev))
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dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
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I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
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} else if (IS_CRESTLINE(dev)) {
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I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
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I915_WRITE(RENCLK_GATE_D2, 0);
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I915_WRITE(DSPCLK_GATE_D, 0);
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I915_WRITE(RAMCLK_GATE_D, 0);
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I915_WRITE16(DEUC, 0);
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} else if (IS_BROADWATER(dev)) {
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I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
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I965_RCC_CLOCK_GATE_DISABLE |
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I965_RCPB_CLOCK_GATE_DISABLE |
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I965_ISC_CLOCK_GATE_DISABLE |
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I965_FBC_CLOCK_GATE_DISABLE);
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I915_WRITE(RENCLK_GATE_D2, 0);
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} else if (IS_GEN3(dev)) {
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u32 dstate = I915_READ(D_STATE);
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I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
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I965_RCC_CLOCK_GATE_DISABLE |
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I965_RCPB_CLOCK_GATE_DISABLE |
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I965_ISC_CLOCK_GATE_DISABLE |
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I965_FBC_CLOCK_GATE_DISABLE);
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I915_WRITE(RENCLK_GATE_D2, 0);
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}
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dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
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DSTATE_DOT_CLOCK_GATING;
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I915_WRITE(D_STATE, dstate);
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} else if (IS_I85X(dev) || IS_I865G(dev)) {
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I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
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} else if (IS_I830(dev)) {
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I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
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}
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static void gen3_init_clock_gating(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 dstate = I915_READ(D_STATE);
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dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
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DSTATE_DOT_CLOCK_GATING;
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I915_WRITE(D_STATE, dstate);
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}
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static void i85x_init_clock_gating(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
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}
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static void i830_init_clock_gating(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
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}
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static void ironlake_teardown_rc6(struct drm_device *dev)
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@ -7549,6 +7582,7 @@ static void intel_init_display(struct drm_device *dev)
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dev_priv->display.update_wm = NULL;
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}
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dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
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dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
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} else if (IS_GEN6(dev)) {
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if (SNB_READ_WM0_LATENCY()) {
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dev_priv->display.update_wm = sandybridge_update_wm;
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@ -7558,6 +7592,7 @@ static void intel_init_display(struct drm_device *dev)
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dev_priv->display.update_wm = NULL;
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}
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dev_priv->display.fdi_link_train = gen6_fdi_link_train;
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dev_priv->display.init_clock_gating = gen6_init_clock_gating;
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} else if (IS_IVYBRIDGE(dev)) {
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/* FIXME: detect B0+ stepping and use auto training */
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dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
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@ -7568,6 +7603,8 @@ static void intel_init_display(struct drm_device *dev)
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"Disable CxSR\n");
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dev_priv->display.update_wm = NULL;
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}
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dev_priv->display.init_clock_gating = gen6_init_clock_gating;
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} else
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dev_priv->display.update_wm = NULL;
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} else if (IS_PINEVIEW(dev)) {
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@ -7585,18 +7622,30 @@ static void intel_init_display(struct drm_device *dev)
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dev_priv->display.update_wm = NULL;
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} else
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dev_priv->display.update_wm = pineview_update_wm;
|
||||
} else if (IS_G4X(dev))
|
||||
} else if (IS_G4X(dev)) {
|
||||
dev_priv->display.update_wm = g4x_update_wm;
|
||||
else if (IS_GEN4(dev))
|
||||
dev_priv->display.init_clock_gating = g4x_init_clock_gating;
|
||||
} else if (IS_GEN4(dev)) {
|
||||
dev_priv->display.update_wm = i965_update_wm;
|
||||
else if (IS_GEN3(dev)) {
|
||||
if (IS_CRESTLINE(dev))
|
||||
dev_priv->display.init_clock_gating = crestline_init_clock_gating;
|
||||
else if (IS_BROADWATER(dev))
|
||||
dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
|
||||
} else if (IS_GEN3(dev)) {
|
||||
dev_priv->display.update_wm = i9xx_update_wm;
|
||||
dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
|
||||
dev_priv->display.init_clock_gating = gen3_init_clock_gating;
|
||||
} else if (IS_I865G(dev)) {
|
||||
dev_priv->display.update_wm = i830_update_wm;
|
||||
dev_priv->display.init_clock_gating = i85x_init_clock_gating;
|
||||
dev_priv->display.get_fifo_size = i830_get_fifo_size;
|
||||
} else if (IS_I85X(dev)) {
|
||||
dev_priv->display.update_wm = i9xx_update_wm;
|
||||
dev_priv->display.get_fifo_size = i85x_get_fifo_size;
|
||||
dev_priv->display.init_clock_gating = i85x_init_clock_gating;
|
||||
} else {
|
||||
dev_priv->display.update_wm = i830_update_wm;
|
||||
dev_priv->display.init_clock_gating = i830_init_clock_gating;
|
||||
if (IS_845G(dev))
|
||||
dev_priv->display.get_fifo_size = i845_get_fifo_size;
|
||||
else
|
||||
|
@ -7726,7 +7775,7 @@ void intel_modeset_init(struct drm_device *dev)
|
|||
i915_disable_vga(dev);
|
||||
intel_setup_outputs(dev);
|
||||
|
||||
intel_enable_clock_gating(dev);
|
||||
dev_priv->display.init_clock_gating(dev);
|
||||
|
||||
if (IS_IRONLAKE_M(dev)) {
|
||||
ironlake_enable_drps(dev);
|
||||
|
|
Loading…
Reference in a new issue