MIPS: CPS: Early debug using an ns16550-compatible UART
Provide support for outputting early debug information, in the form of various register values should an exception occur, during the early bringup of secondary cores. This code requires an ns16550-compatible UART accessible from the secondary core, and is written in assembly due to the environment in which such early exceptions occur where way may not have a stack, be coherent or even have initialised caches. [ralf@linux-mips.org: Fix merge conflict.] Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: Jason Cooper <jason@lakedaemon.net> Cc: linux-kernel@vger.kernel.org Cc: James Hogan <james.hogan@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/11202/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>hifive-unleashed-5.1
Paul Burton
Ralf Baechle
parent
195cee92af
commit
609cf6f229
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@ -159,4 +159,30 @@ config SCACHE_DEBUGFS
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If unsure, say N.
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menuconfig MIPS_CPS_NS16550
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bool "CPS SMP NS16550 UART output"
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depends on MIPS_CPS
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help
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Output debug information via an ns16550 compatible UART if exceptions
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occur early in the boot process of a secondary core.
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if MIPS_CPS_NS16550
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config MIPS_CPS_NS16550_BASE
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hex "UART Base Address"
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default 0x1b0003f8 if MIPS_MALTA
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help
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The base address of the ns16550 compatible UART on which to output
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debug information from the early stages of core startup.
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config MIPS_CPS_NS16550_SHIFT
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int "UART Register Shift"
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default 0 if MIPS_MALTA
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help
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The number of bits to shift ns16550 register indices by in order to
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form their addresses. That is, log base 2 of the span between
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adjacent ns16550 registers in the system.
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endif # MIPS_CPS_NS16550
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endmenu
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@ -52,6 +52,7 @@
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#define CP0_INFO $7
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#define CP0_HWRENA $7, 0
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#define CP0_BADVADDR $8
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#define CP0_BADINSTR $8, 1
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#define CP0_COUNT $9
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#define CP0_ENTRYHI $10
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#define CP0_COMPARE $11
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@ -59,6 +60,8 @@
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#define CP0_CAUSE $13
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#define CP0_EPC $14
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#define CP0_PRID $15
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#define CP0_EBASE $15, 1
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#define CP0_CMGCRBASE $15, 3
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#define CP0_CONFIG $16
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#define CP0_CONFIG3 $16, 3
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#define CP0_CONFIG5 $16, 5
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@ -51,6 +51,7 @@ obj-$(CONFIG_MIPS_MT_FPAFF) += mips-mt-fpaff.o
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obj-$(CONFIG_MIPS_MT_SMP) += smp-mt.o
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obj-$(CONFIG_MIPS_CMP) += smp-cmp.o
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obj-$(CONFIG_MIPS_CPS) += smp-cps.o cps-vec.o
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obj-$(CONFIG_MIPS_CPS_NS16550) += cps-vec-ns16550.o
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obj-$(CONFIG_MIPS_GIC_IPI) += smp-gic.o
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obj-$(CONFIG_MIPS_SPRAM) += spram.o
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@ -0,0 +1,202 @@
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/*
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* Copyright (C) 2015 Imagination Technologies
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* Author: Paul Burton <paul.burton@imgtec.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <asm/addrspace.h>
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#include <asm/asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/mipsregs.h>
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#include <asm/regdef.h>
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#include <linux/serial_reg.h>
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#define UART_TX_OFS (UART_TX << CONFIG_MIPS_CPS_NS16550_SHIFT)
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#define UART_LSR_OFS (UART_LSR << CONFIG_MIPS_CPS_NS16550_SHIFT)
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/**
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* _mips_cps_putc() - write a character to the UART
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* @a0: ASCII character to write
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* @t9: UART base address
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*/
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LEAF(_mips_cps_putc)
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1: lw t0, UART_LSR_OFS(t9)
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andi t0, t0, UART_LSR_TEMT
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beqz t0, 1b
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sb a0, UART_TX_OFS(t9)
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jr ra
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END(_mips_cps_putc)
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/**
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* _mips_cps_puts() - write a string to the UART
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* @a0: pointer to NULL-terminated ASCII string
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* @t9: UART base address
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*
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* Write a null-terminated ASCII string to the UART.
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*/
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NESTED(_mips_cps_puts, 0, ra)
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move s7, ra
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move s6, a0
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1: lb a0, 0(s6)
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beqz a0, 2f
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jal _mips_cps_putc
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PTR_ADDIU s6, s6, 1
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b 1b
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2: jr s7
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END(_mips_cps_puts)
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/**
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* _mips_cps_putx4 - write a 4b hex value to the UART
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* @a0: the 4b value to write to the UART
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* @t9: UART base address
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*
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* Write a single hexadecimal character to the UART.
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*/
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NESTED(_mips_cps_putx4, 0, ra)
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andi a0, a0, 0xf
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li t0, '0'
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blt a0, 10, 1f
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li t0, 'a'
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addiu a0, a0, -10
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1: addu a0, a0, t0
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b _mips_cps_putc
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END(_mips_cps_putx4)
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/**
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* _mips_cps_putx8 - write an 8b hex value to the UART
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* @a0: the 8b value to write to the UART
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* @t9: UART base address
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*
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* Write an 8 bit value (ie. 2 hexadecimal characters) to the UART.
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*/
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NESTED(_mips_cps_putx8, 0, ra)
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move s3, ra
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move s2, a0
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srl a0, a0, 4
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jal _mips_cps_putx4
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move a0, s2
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move ra, s3
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b _mips_cps_putx4
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END(_mips_cps_putx8)
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/**
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* _mips_cps_putx16 - write a 16b hex value to the UART
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* @a0: the 16b value to write to the UART
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* @t9: UART base address
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*
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* Write a 16 bit value (ie. 4 hexadecimal characters) to the UART.
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*/
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NESTED(_mips_cps_putx16, 0, ra)
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move s5, ra
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move s4, a0
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srl a0, a0, 8
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jal _mips_cps_putx8
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move a0, s4
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move ra, s5
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b _mips_cps_putx8
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END(_mips_cps_putx16)
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/**
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* _mips_cps_putx32 - write a 32b hex value to the UART
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* @a0: the 32b value to write to the UART
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* @t9: UART base address
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*
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* Write a 32 bit value (ie. 8 hexadecimal characters) to the UART.
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*/
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NESTED(_mips_cps_putx32, 0, ra)
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move s7, ra
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move s6, a0
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srl a0, a0, 16
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jal _mips_cps_putx16
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move a0, s6
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move ra, s7
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b _mips_cps_putx16
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END(_mips_cps_putx32)
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#ifdef CONFIG_64BIT
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/**
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* _mips_cps_putx64 - write a 64b hex value to the UART
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* @a0: the 64b value to write to the UART
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* @t9: UART base address
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*
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* Write a 64 bit value (ie. 16 hexadecimal characters) to the UART.
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*/
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NESTED(_mips_cps_putx64, 0, ra)
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move sp, ra
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move s8, a0
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dsrl32 a0, a0, 0
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jal _mips_cps_putx32
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move a0, s8
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move ra, sp
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b _mips_cps_putx32
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END(_mips_cps_putx64)
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#define _mips_cps_putxlong _mips_cps_putx64
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#else /* !CONFIG_64BIT */
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#define _mips_cps_putxlong _mips_cps_putx32
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#endif /* !CONFIG_64BIT */
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/**
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* mips_cps_bev_dump() - dump relevant exception state to UART
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* @a0: pointer to NULL-terminated ASCII string naming the exception
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*
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* Write information that may be useful in debugging an exception to the
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* UART configured by CONFIG_MIPS_CPS_NS16550_*. As this BEV exception
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* will only be run if something goes horribly wrong very early during
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* the bringup of a core and it is very likely to be unsafe to perform
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* memory accesses at that point (cache state indeterminate, EVA may not
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* be configured, coherence may be disabled) let alone have a stack,
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* this is all written in assembly using only registers & unmapped
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* uncached access to the UART registers.
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*/
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LEAF(mips_cps_bev_dump)
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move s0, ra
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move s1, a0
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li t9, CKSEG1ADDR(CONFIG_MIPS_CPS_NS16550_BASE)
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PTR_LA a0, str_newline
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jal _mips_cps_puts
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PTR_LA a0, str_bev
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jal _mips_cps_puts
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move a0, s1
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jal _mips_cps_puts
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PTR_LA a0, str_newline
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jal _mips_cps_puts
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PTR_LA a0, str_newline
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jal _mips_cps_puts
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#define DUMP_COP0_REG(reg, name, sz, _mfc0) \
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PTR_LA a0, 8f; \
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jal _mips_cps_puts; \
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_mfc0 a0, reg; \
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jal _mips_cps_putx##sz; \
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PTR_LA a0, str_newline; \
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jal _mips_cps_puts; \
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TEXT(name)
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DUMP_COP0_REG(CP0_CAUSE, "Cause: 0x", 32, mfc0)
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DUMP_COP0_REG(CP0_STATUS, "Status: 0x", 32, mfc0)
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DUMP_COP0_REG(CP0_EBASE, "EBase: 0x", long, MFC0)
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DUMP_COP0_REG(CP0_BADVADDR, "BadVAddr: 0x", long, MFC0)
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DUMP_COP0_REG(CP0_BADINSTR, "BadInstr: 0x", 32, mfc0)
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PTR_LA a0, str_newline
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jal _mips_cps_puts
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jr s0
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END(mips_cps_bev_dump)
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.pushsection .data
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str_bev: .asciiz "BEV Exception: "
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str_newline: .asciiz "\r\n"
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.popsection
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@ -31,6 +31,20 @@
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# define STATUS_BITDEPS 0
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#endif
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#ifdef CONFIG_MIPS_CPS_NS16550
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#define DUMP_EXCEP(name) \
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PTR_LA a0, 8f; \
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jal mips_cps_bev_dump; \
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nop; \
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TEXT(name)
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#else /* !CONFIG_MIPS_CPS_NS16550 */
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#define DUMP_EXCEP(name)
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#endif /* !CONFIG_MIPS_CPS_NS16550 */
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/*
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* Set dest to non-zero if the core supports the MT ASE, else zero. If
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* MT is not supported then branch to nomt.
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@ -194,36 +208,42 @@ dcache_done:
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.org 0x200
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LEAF(excep_tlbfill)
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DUMP_EXCEP("TLB Fill")
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b .
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nop
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END(excep_tlbfill)
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.org 0x280
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LEAF(excep_xtlbfill)
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DUMP_EXCEP("XTLB Fill")
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b .
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nop
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END(excep_xtlbfill)
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.org 0x300
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LEAF(excep_cache)
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DUMP_EXCEP("Cache")
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b .
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nop
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END(excep_cache)
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.org 0x380
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LEAF(excep_genex)
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DUMP_EXCEP("General")
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b .
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nop
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END(excep_genex)
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.org 0x400
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LEAF(excep_intex)
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DUMP_EXCEP("Interrupt")
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b .
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nop
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END(excep_intex)
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.org 0x480
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LEAF(excep_ejtag)
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DUMP_EXCEP("EJTAG")
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PTR_LA k0, ejtag_debug_handler
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jr k0
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nop
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