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ASoC: rt5677: fixed wrong DMIC ref clock 

DMIC clock source is not from codec system clock directly. it is
generated from the division of system clock. And it should be 256 *
sample rate of AIF1.

Signed-off-by: Bard Liao <bardliao@realtek.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Cc: stable@vger.kernel.org
hifive-unleashed-5.1
Bard Liao 2015-04-28 11:27:39 +08:00 committed by Mark Brown
parent 74d6ea52ae
commit 60a8d62b84
1 changed files with 1 additions and 1 deletions
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2
sound/soc/codecs/rt5677.c
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@ -904,7 +904,7 @@ static int set_dmic_clk(struct snd_soc_dapm_widget *w,
{
struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
int idx = rl6231_calc_dmic_clk(rt5677->sysclk);
int idx = rl6231_calc_dmic_clk(rt5677->lrck[RT5677_AIF1] << 8);
if (idx < 0)
dev_err(codec->dev, "Failed to set DMIC clock\n");