i2c: imx: support slave mode for imx I2C driver
The patch supports slave mode for imx I2C driver Reviewed-by: Clark Wang <xiaoning.wang@nxp.com> Signed-off-by: Biwen Li <biwen.li@nxp.com>5.4-rM2-2.2.x-imx-squashed
Biwen Li
parent
a4c08f327f
commit
60c97c96b5
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@ -265,6 +265,9 @@ struct imx_i2c_struct {
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int pmuxcr_set;
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int pmuxcr_endian;
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void __iomem *pmuxcr_addr;
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#if IS_ENABLED(CONFIG_I2C_SLAVE)
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struct i2c_client *slave;
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#endif
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};
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static const struct imx_i2c_hwdata imx1_i2c_hwdata = {
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@ -357,6 +360,14 @@ static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx,
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return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
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}
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/* Set up i2c controller register and i2c status register to default value. */
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static void i2c_imx_reset_regs(struct imx_i2c_struct *i2c_imx)
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{
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imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
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i2c_imx, IMX_I2C_I2CR);
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imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
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}
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/* Functions for DMA support */
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static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx,
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dma_addr_t phy_addr)
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@ -681,23 +692,33 @@ static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx)
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imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
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}
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static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
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/* Clear interrupt flag bit */
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static void i2c_imx_clr_if_bit(unsigned int status, struct imx_i2c_struct *i2c_imx)
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{
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struct imx_i2c_struct *i2c_imx = dev_id;
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unsigned int temp;
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status &= ~I2SR_IIF;
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status |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IIF);
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imx_i2c_write_reg(status, i2c_imx, IMX_I2C_I2SR);
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}
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temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
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if (temp & I2SR_IIF) {
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/* save status register */
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i2c_imx->i2csr = temp;
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temp &= ~I2SR_IIF;
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temp |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IIF);
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imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
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wake_up(&i2c_imx->queue);
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return IRQ_HANDLED;
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}
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/* Clear arbitration lost bit */
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static void i2c_imx_clr_al_bit(unsigned int status, struct imx_i2c_struct *i2c_imx)
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{
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status &= ~I2SR_IAL;
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status |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IAL);
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imx_i2c_write_reg(status, i2c_imx, IMX_I2C_I2SR);
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}
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return IRQ_NONE;
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static irqreturn_t i2c_imx_master_isr(struct imx_i2c_struct *i2c_imx)
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{
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unsigned int status;
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/* Save status register */
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status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
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i2c_imx->i2csr = status | I2SR_IIF;
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wake_up(&i2c_imx->queue);
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return IRQ_HANDLED;
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}
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static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx,
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@ -1066,6 +1087,13 @@ static int i2c_imx_xfer(struct i2c_adapter *adapter,
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dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
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#if IS_ENABLED(CONFIG_I2C_SLAVE)
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if (i2c_imx->slave) {
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dev_err(&i2c_imx->adapter.dev, "Please not do operations of master mode in slave mode");
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return -EBUSY;
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}
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#endif
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if (!pm_runtime_enabled(i2c_imx->adapter.dev.parent)) {
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pm_runtime_enable(i2c_imx->adapter.dev.parent);
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enable_runtime_pm = true;
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@ -1279,11 +1307,169 @@ static u32 i2c_imx_func(struct i2c_adapter *adapter)
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| I2C_FUNC_SMBUS_READ_BLOCK_DATA;
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}
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#if IS_ENABLED(CONFIG_I2C_SLAVE)
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static int i2c_imx_slave_init(struct imx_i2c_struct *i2c_imx)
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{
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int temp;
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/* Resume */
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temp = pm_runtime_get_sync(i2c_imx->adapter.dev.parent);
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if (temp < 0) {
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dev_err(&i2c_imx->adapter.dev, "failed to resume i2c controller");
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return temp;
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}
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/* Set slave addr. */
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imx_i2c_write_reg((i2c_imx->slave->addr << 1), i2c_imx, IMX_I2C_IADR);
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i2c_imx_reset_regs(i2c_imx);
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/* Enable module */
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temp = i2c_imx->hwdata->i2cr_ien_opcode;
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imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
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/* Enable interrupt from i2c module */
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temp |= I2CR_IIEN;
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imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
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/* Wait controller to be stable */
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usleep_range(50, 150);
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return 0;
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}
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static irqreturn_t i2c_imx_slave_isr(struct imx_i2c_struct *i2c_imx)
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{
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unsigned int status, ctl;
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u8 value;
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if (!i2c_imx->slave) {
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dev_err(&i2c_imx->adapter.dev, "cannot deal with slave irq,i2c_imx->slave is null");
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return IRQ_NONE;
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}
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status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
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ctl = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
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if (status & I2SR_IAL) { /* Arbitration lost */
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i2c_imx_clr_al_bit(status, i2c_imx);
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} else if (status & I2SR_IAAS) { /* Addressed as a slave */
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if (status & I2SR_SRW) { /* Master wants to read from us*/
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dev_dbg(&i2c_imx->adapter.dev, "read requested");
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i2c_slave_event(i2c_imx->slave, I2C_SLAVE_READ_REQUESTED, &value);
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/* Slave transmit */
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ctl |= I2CR_MTX;
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imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
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/* Send data */
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imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR);
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} else { /* Master wants to write to us */
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dev_dbg(&i2c_imx->adapter.dev, "write requested");
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i2c_slave_event(i2c_imx->slave, I2C_SLAVE_WRITE_REQUESTED, &value);
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/* Slave receive */
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ctl &= ~I2CR_MTX;
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imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
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/* Dummy read */
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imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
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}
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} else if (!(ctl & I2CR_MTX)) { /* Receive mode */
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if (status & I2SR_IBB) { /* No STOP signal detected */
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ctl &= ~I2CR_MTX;
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imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
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value = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
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i2c_slave_event(i2c_imx->slave, I2C_SLAVE_WRITE_RECEIVED, &value);
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} else { /* STOP signal is detected */
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dev_dbg(&i2c_imx->adapter.dev,
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"STOP signal detected");
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i2c_slave_event(i2c_imx->slave, I2C_SLAVE_STOP, &value);
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}
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} else if (!(status & I2SR_RXAK)) { /* Transmit mode received ACK */
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ctl |= I2CR_MTX;
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imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
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i2c_slave_event(i2c_imx->slave, I2C_SLAVE_READ_PROCESSED, &value);
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imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR);
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} else { /* Transmit mode received NAK */
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ctl &= ~I2CR_MTX;
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imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
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imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
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}
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return IRQ_HANDLED;
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}
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static int i2c_imx_reg_slave(struct i2c_client *client)
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{
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struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter);
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int ret;
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if (i2c_imx->slave)
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return -EBUSY;
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i2c_imx->slave = client;
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ret = i2c_imx_slave_init(i2c_imx);
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if (ret < 0)
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dev_err(&i2c_imx->adapter.dev, "failed to switch to slave mode");
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return ret;
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}
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static int i2c_imx_unreg_slave(struct i2c_client *client)
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{
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struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter);
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int ret;
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if (!i2c_imx->slave)
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return -EINVAL;
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/* Reset slave address. */
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imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR);
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i2c_imx_reset_regs(i2c_imx);
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i2c_imx->slave = NULL;
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/* Suspend */
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ret = pm_runtime_put_sync(i2c_imx->adapter.dev.parent);
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if (ret < 0)
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dev_err(&i2c_imx->adapter.dev, "failed to suspend i2c controller");
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return ret;
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}
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#endif
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static const struct i2c_algorithm i2c_imx_algo = {
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.master_xfer = i2c_imx_xfer,
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.functionality = i2c_imx_func,
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#if IS_ENABLED(CONFIG_I2C_SLAVE)
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.reg_slave = i2c_imx_reg_slave,
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.unreg_slave = i2c_imx_unreg_slave,
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#endif
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};
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static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
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{
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struct imx_i2c_struct *i2c_imx = dev_id;
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unsigned int status, ctl;
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irqreturn_t irq_status = IRQ_NONE;
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status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
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ctl = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
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if (status & I2SR_IIF) {
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i2c_imx_clr_if_bit(status, i2c_imx);
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if (ctl & I2CR_MSTA)
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irq_status = i2c_imx_master_isr(i2c_imx);
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#if IS_ENABLED(CONFIG_I2C_SLAVE)
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else
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irq_status = i2c_imx_slave_isr(i2c_imx);
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#endif
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}
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return irq_status;
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}
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static int i2c_imx_probe(struct platform_device *pdev)
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{
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struct imx_i2c_struct *i2c_imx;
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@ -1392,10 +1578,7 @@ static int i2c_imx_probe(struct platform_device *pdev)
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if (is_imx7d_i2c(i2c_imx) && i2c_imx->bitrate > IMX_I2C_MAX_E_BIT_RATE)
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i2c_imx->bitrate = IMX_I2C_MAX_E_BIT_RATE;
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/* Set up chip registers to defaults */
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imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
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i2c_imx, IMX_I2C_I2CR);
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imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
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i2c_imx_reset_regs(i2c_imx);
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/* Init optional bus recovery */
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if (of_match_node(pinmux_of_match, pdev->dev.of_node))
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