drm/i915/skl: Add GEN8_L3SQCREG4 to HW whitelist
Required for WaDisableLSQCROPERFforOCL:skl This register is added to HW whitelist to support WA required for future enabling of pre-emptive command execution, WA implementation will be in userspace and it cannot program this register if it is not on HW whitelist. v2: explain purpose of changes (Chris) Reviewed-by: Nick Hoath <nicholas.hoath@intel.com> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1453412634-29238-7-git-send-email-arun.siluvery@linux.intel.com Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -1098,6 +1098,11 @@ static int skl_init_workarounds(struct intel_engine_cs *ring)
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GEN7_HALF_SLICE_CHICKEN1,
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GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
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/* WaDisableLSQCROPERFforOCL:skl */
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ret = wa_ring_whitelist_reg(ring, GEN8_L3SQCREG4);
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if (ret)
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return ret;
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return skl_tune_iz_hashing(ring);
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}
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